1 /* 2 * OMAP LCD controller. 3 * 4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/irq.h" 22 #include "ui/console.h" 23 #include "hw/arm/omap.h" 24 #include "framebuffer.h" 25 #include "ui/pixel_ops.h" 26 27 struct omap_lcd_panel_s { 28 MemoryRegion *sysmem; 29 MemoryRegion iomem; 30 MemoryRegionSection fbsection; 31 qemu_irq irq; 32 QemuConsole *con; 33 34 int plm; 35 int tft; 36 int mono; 37 int enable; 38 int width; 39 int height; 40 int interrupts; 41 uint32_t timing[3]; 42 uint32_t subpanel; 43 uint32_t ctrl; 44 45 struct omap_dma_lcd_channel_s *dma; 46 uint16_t palette[256]; 47 int palette_done; 48 int frame_done; 49 int invalidate; 50 int sync_error; 51 }; 52 53 static void omap_lcd_interrupts(struct omap_lcd_panel_s *s) 54 { 55 if (s->frame_done && (s->interrupts & 1)) { 56 qemu_irq_raise(s->irq); 57 return; 58 } 59 60 if (s->palette_done && (s->interrupts & 2)) { 61 qemu_irq_raise(s->irq); 62 return; 63 } 64 65 if (s->sync_error) { 66 qemu_irq_raise(s->irq); 67 return; 68 } 69 70 qemu_irq_lower(s->irq); 71 } 72 73 #define draw_line_func drawfn 74 75 /* 76 * 2-bit colour 77 */ 78 static void draw_line2_32(void *opaque, uint8_t *d, const uint8_t *s, 79 int width, int deststep) 80 { 81 uint16_t *pal = opaque; 82 uint8_t v, r, g, b; 83 84 do { 85 v = ldub_p((void *) s); 86 r = (pal[v & 3] >> 4) & 0xf0; 87 g = pal[v & 3] & 0xf0; 88 b = (pal[v & 3] << 4) & 0xf0; 89 ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); 90 d += 4; 91 v >>= 2; 92 r = (pal[v & 3] >> 4) & 0xf0; 93 g = pal[v & 3] & 0xf0; 94 b = (pal[v & 3] << 4) & 0xf0; 95 ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); 96 d += 4; 97 v >>= 2; 98 r = (pal[v & 3] >> 4) & 0xf0; 99 g = pal[v & 3] & 0xf0; 100 b = (pal[v & 3] << 4) & 0xf0; 101 ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); 102 d += 4; 103 v >>= 2; 104 r = (pal[v & 3] >> 4) & 0xf0; 105 g = pal[v & 3] & 0xf0; 106 b = (pal[v & 3] << 4) & 0xf0; 107 ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); 108 d += 4; 109 s++; 110 width -= 4; 111 } while (width > 0); 112 } 113 114 /* 115 * 4-bit colour 116 */ 117 static void draw_line4_32(void *opaque, uint8_t *d, const uint8_t *s, 118 int width, int deststep) 119 { 120 uint16_t *pal = opaque; 121 uint8_t v, r, g, b; 122 123 do { 124 v = ldub_p((void *) s); 125 r = (pal[v & 0xf] >> 4) & 0xf0; 126 g = pal[v & 0xf] & 0xf0; 127 b = (pal[v & 0xf] << 4) & 0xf0; 128 ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); 129 d += 4; 130 v >>= 4; 131 r = (pal[v & 0xf] >> 4) & 0xf0; 132 g = pal[v & 0xf] & 0xf0; 133 b = (pal[v & 0xf] << 4) & 0xf0; 134 ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); 135 d += 4; 136 s++; 137 width -= 2; 138 } while (width > 0); 139 } 140 141 /* 142 * 8-bit colour 143 */ 144 static void draw_line8_32(void *opaque, uint8_t *d, const uint8_t *s, 145 int width, int deststep) 146 { 147 uint16_t *pal = opaque; 148 uint8_t v, r, g, b; 149 150 do { 151 v = ldub_p((void *) s); 152 r = (pal[v] >> 4) & 0xf0; 153 g = pal[v] & 0xf0; 154 b = (pal[v] << 4) & 0xf0; 155 ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); 156 s++; 157 d += 4; 158 } while (-- width != 0); 159 } 160 161 /* 162 * 12-bit colour 163 */ 164 static void draw_line12_32(void *opaque, uint8_t *d, const uint8_t *s, 165 int width, int deststep) 166 { 167 uint16_t v; 168 uint8_t r, g, b; 169 170 do { 171 v = lduw_le_p((void *) s); 172 r = (v >> 4) & 0xf0; 173 g = v & 0xf0; 174 b = (v << 4) & 0xf0; 175 ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); 176 s += 2; 177 d += 4; 178 } while (-- width != 0); 179 } 180 181 /* 182 * 16-bit colour 183 */ 184 static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s, 185 int width, int deststep) 186 { 187 uint16_t v; 188 uint8_t r, g, b; 189 190 do { 191 v = lduw_le_p((void *) s); 192 r = (v >> 8) & 0xf8; 193 g = (v >> 3) & 0xfc; 194 b = (v << 3) & 0xf8; 195 ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); 196 s += 2; 197 d += 4; 198 } while (-- width != 0); 199 } 200 201 static void omap_update_display(void *opaque) 202 { 203 struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque; 204 DisplaySurface *surface; 205 draw_line_func draw_line; 206 int size, height, first, last; 207 int width, linesize, step, bpp, frame_offset; 208 hwaddr frame_base; 209 210 if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable) { 211 return; 212 } 213 214 surface = qemu_console_surface(omap_lcd->con); 215 if (!surface_bits_per_pixel(surface)) { 216 return; 217 } 218 219 frame_offset = 0; 220 if (omap_lcd->plm != 2) { 221 cpu_physical_memory_read( 222 omap_lcd->dma->phys_framebuffer[omap_lcd->dma->current_frame], 223 omap_lcd->palette, 0x200); 224 switch (omap_lcd->palette[0] >> 12 & 7) { 225 case 3 ... 7: 226 frame_offset += 0x200; 227 break; 228 default: 229 frame_offset += 0x20; 230 } 231 } 232 233 /* Colour depth */ 234 switch ((omap_lcd->palette[0] >> 12) & 7) { 235 case 1: 236 draw_line = draw_line2_32; 237 bpp = 2; 238 break; 239 240 case 2: 241 draw_line = draw_line4_32; 242 bpp = 4; 243 break; 244 245 case 3: 246 draw_line = draw_line8_32; 247 bpp = 8; 248 break; 249 250 case 4 ... 7: 251 if (!omap_lcd->tft) 252 draw_line = draw_line12_32; 253 else 254 draw_line = draw_line16_32; 255 bpp = 16; 256 break; 257 258 default: 259 /* Unsupported at the moment. */ 260 return; 261 } 262 263 /* Resolution */ 264 width = omap_lcd->width; 265 if (width != surface_width(surface) || 266 omap_lcd->height != surface_height(surface)) { 267 qemu_console_resize(omap_lcd->con, 268 omap_lcd->width, omap_lcd->height); 269 surface = qemu_console_surface(omap_lcd->con); 270 omap_lcd->invalidate = 1; 271 } 272 273 if (omap_lcd->dma->current_frame == 0) 274 size = omap_lcd->dma->src_f1_bottom - omap_lcd->dma->src_f1_top; 275 else 276 size = omap_lcd->dma->src_f2_bottom - omap_lcd->dma->src_f2_top; 277 278 if (frame_offset + ((width * omap_lcd->height * bpp) >> 3) > size + 2) { 279 omap_lcd->sync_error = 1; 280 omap_lcd_interrupts(omap_lcd); 281 omap_lcd->enable = 0; 282 return; 283 } 284 285 /* Content */ 286 frame_base = omap_lcd->dma->phys_framebuffer[ 287 omap_lcd->dma->current_frame] + frame_offset; 288 omap_lcd->dma->condition |= 1 << omap_lcd->dma->current_frame; 289 if (omap_lcd->dma->interrupts & 1) 290 qemu_irq_raise(omap_lcd->dma->irq); 291 if (omap_lcd->dma->dual) 292 omap_lcd->dma->current_frame ^= 1; 293 294 if (!surface_bits_per_pixel(surface)) { 295 return; 296 } 297 298 first = 0; 299 height = omap_lcd->height; 300 if (omap_lcd->subpanel & (1 << 31)) { 301 if (omap_lcd->subpanel & (1 << 29)) 302 first = (omap_lcd->subpanel >> 16) & 0x3ff; 303 else 304 height = (omap_lcd->subpanel >> 16) & 0x3ff; 305 /* TODO: fill the rest of the panel with DPD */ 306 } 307 308 step = width * bpp >> 3; 309 linesize = surface_stride(surface); 310 if (omap_lcd->invalidate) { 311 framebuffer_update_memory_section(&omap_lcd->fbsection, 312 omap_lcd->sysmem, frame_base, 313 height, step); 314 } 315 316 framebuffer_update_display(surface, &omap_lcd->fbsection, 317 width, height, 318 step, linesize, 0, 319 omap_lcd->invalidate, 320 draw_line, omap_lcd->palette, 321 &first, &last); 322 323 if (first >= 0) { 324 dpy_gfx_update(omap_lcd->con, 0, first, width, last - first + 1); 325 } 326 omap_lcd->invalidate = 0; 327 } 328 329 static void omap_invalidate_display(void *opaque) { 330 struct omap_lcd_panel_s *omap_lcd = opaque; 331 omap_lcd->invalidate = 1; 332 } 333 334 static void omap_lcd_update(struct omap_lcd_panel_s *s) { 335 if (!s->enable) { 336 s->dma->current_frame = -1; 337 s->sync_error = 0; 338 if (s->plm != 1) 339 s->frame_done = 1; 340 omap_lcd_interrupts(s); 341 return; 342 } 343 344 if (s->dma->current_frame == -1) { 345 s->frame_done = 0; 346 s->palette_done = 0; 347 s->dma->current_frame = 0; 348 } 349 350 if (!s->dma->mpu->port[s->dma->src].addr_valid(s->dma->mpu, 351 s->dma->src_f1_top) || 352 !s->dma->mpu->port[ 353 s->dma->src].addr_valid(s->dma->mpu, 354 s->dma->src_f1_bottom) || 355 (s->dma->dual && 356 (!s->dma->mpu->port[ 357 s->dma->src].addr_valid(s->dma->mpu, 358 s->dma->src_f2_top) || 359 !s->dma->mpu->port[ 360 s->dma->src].addr_valid(s->dma->mpu, 361 s->dma->src_f2_bottom)))) { 362 s->dma->condition |= 1 << 2; 363 if (s->dma->interrupts & (1 << 1)) 364 qemu_irq_raise(s->dma->irq); 365 s->enable = 0; 366 return; 367 } 368 369 s->dma->phys_framebuffer[0] = s->dma->src_f1_top; 370 s->dma->phys_framebuffer[1] = s->dma->src_f2_top; 371 372 if (s->plm != 2 && !s->palette_done) { 373 cpu_physical_memory_read( 374 s->dma->phys_framebuffer[s->dma->current_frame], 375 s->palette, 0x200); 376 s->palette_done = 1; 377 omap_lcd_interrupts(s); 378 } 379 } 380 381 static uint64_t omap_lcdc_read(void *opaque, hwaddr addr, 382 unsigned size) 383 { 384 struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque; 385 386 switch (addr) { 387 case 0x00: /* LCD_CONTROL */ 388 return (s->tft << 23) | (s->plm << 20) | 389 (s->tft << 7) | (s->interrupts << 3) | 390 (s->mono << 1) | s->enable | s->ctrl | 0xfe000c34; 391 392 case 0x04: /* LCD_TIMING0 */ 393 return (s->timing[0] << 10) | (s->width - 1) | 0x0000000f; 394 395 case 0x08: /* LCD_TIMING1 */ 396 return (s->timing[1] << 10) | (s->height - 1); 397 398 case 0x0c: /* LCD_TIMING2 */ 399 return s->timing[2] | 0xfc000000; 400 401 case 0x10: /* LCD_STATUS */ 402 return (s->palette_done << 6) | (s->sync_error << 2) | s->frame_done; 403 404 case 0x14: /* LCD_SUBPANEL */ 405 return s->subpanel; 406 407 default: 408 break; 409 } 410 OMAP_BAD_REG(addr); 411 return 0; 412 } 413 414 static void omap_lcdc_write(void *opaque, hwaddr addr, 415 uint64_t value, unsigned size) 416 { 417 struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque; 418 419 switch (addr) { 420 case 0x00: /* LCD_CONTROL */ 421 s->plm = (value >> 20) & 3; 422 s->tft = (value >> 7) & 1; 423 s->interrupts = (value >> 3) & 3; 424 s->mono = (value >> 1) & 1; 425 s->ctrl = value & 0x01cff300; 426 if (s->enable != (value & 1)) { 427 s->enable = value & 1; 428 omap_lcd_update(s); 429 } 430 break; 431 432 case 0x04: /* LCD_TIMING0 */ 433 s->timing[0] = value >> 10; 434 s->width = (value & 0x3ff) + 1; 435 break; 436 437 case 0x08: /* LCD_TIMING1 */ 438 s->timing[1] = value >> 10; 439 s->height = (value & 0x3ff) + 1; 440 break; 441 442 case 0x0c: /* LCD_TIMING2 */ 443 s->timing[2] = value; 444 break; 445 446 case 0x10: /* LCD_STATUS */ 447 break; 448 449 case 0x14: /* LCD_SUBPANEL */ 450 s->subpanel = value & 0xa1ffffff; 451 break; 452 453 default: 454 OMAP_BAD_REG(addr); 455 } 456 } 457 458 static const MemoryRegionOps omap_lcdc_ops = { 459 .read = omap_lcdc_read, 460 .write = omap_lcdc_write, 461 .endianness = DEVICE_NATIVE_ENDIAN, 462 }; 463 464 void omap_lcdc_reset(struct omap_lcd_panel_s *s) 465 { 466 s->dma->current_frame = -1; 467 s->plm = 0; 468 s->tft = 0; 469 s->mono = 0; 470 s->enable = 0; 471 s->width = 0; 472 s->height = 0; 473 s->interrupts = 0; 474 s->timing[0] = 0; 475 s->timing[1] = 0; 476 s->timing[2] = 0; 477 s->subpanel = 0; 478 s->palette_done = 0; 479 s->frame_done = 0; 480 s->sync_error = 0; 481 s->invalidate = 1; 482 s->subpanel = 0; 483 s->ctrl = 0; 484 } 485 486 static const GraphicHwOps omap_ops = { 487 .invalidate = omap_invalidate_display, 488 .gfx_update = omap_update_display, 489 }; 490 491 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, 492 hwaddr base, 493 qemu_irq irq, 494 struct omap_dma_lcd_channel_s *dma, 495 omap_clk clk) 496 { 497 struct omap_lcd_panel_s *s = g_new0(struct omap_lcd_panel_s, 1); 498 499 s->irq = irq; 500 s->dma = dma; 501 s->sysmem = sysmem; 502 omap_lcdc_reset(s); 503 504 memory_region_init_io(&s->iomem, NULL, &omap_lcdc_ops, s, "omap.lcdc", 0x100); 505 memory_region_add_subregion(sysmem, base, &s->iomem); 506 507 s->con = graphic_console_init(NULL, 0, &omap_ops, s); 508 509 return s; 510 } 511