1 /* 2 * OMAP2 Display Subsystem. 3 * 4 * Copyright (C) 2008 Nokia Corporation 5 * Written by Andrzej Zaborowski <andrew@openedhand.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 #include "qemu/osdep.h" 21 #include "hw/hw.h" 22 #include "ui/console.h" 23 #include "hw/arm/omap.h" 24 25 struct omap_dss_s { 26 qemu_irq irq; 27 qemu_irq drq; 28 DisplayState *state; 29 MemoryRegion iomem_diss1, iomem_disc1, iomem_rfbi1, iomem_venc1, iomem_im3; 30 31 int autoidle; 32 int control; 33 int enable; 34 35 struct omap_dss_panel_s { 36 int enable; 37 int nx; 38 int ny; 39 40 int x; 41 int y; 42 } dig, lcd; 43 44 struct { 45 uint32_t idlemode; 46 uint32_t irqst; 47 uint32_t irqen; 48 uint32_t control; 49 uint32_t config; 50 uint32_t capable; 51 uint32_t timing[4]; 52 int line; 53 uint32_t bg[2]; 54 uint32_t trans[2]; 55 56 struct omap_dss_plane_s { 57 int enable; 58 int bpp; 59 int posx; 60 int posy; 61 int nx; 62 int ny; 63 64 hwaddr addr[3]; 65 66 uint32_t attr; 67 uint32_t tresh; 68 int rowinc; 69 int colinc; 70 int wininc; 71 } l[3]; 72 73 int invalidate; 74 uint16_t palette[256]; 75 } dispc; 76 77 struct { 78 int idlemode; 79 uint32_t control; 80 int enable; 81 int pixels; 82 int busy; 83 int skiplines; 84 uint16_t rxbuf; 85 uint32_t config[2]; 86 uint32_t time[4]; 87 uint32_t data[6]; 88 uint16_t vsync; 89 uint16_t hsync; 90 struct rfbi_chip_s *chip[2]; 91 } rfbi; 92 }; 93 94 static void omap_dispc_interrupt_update(struct omap_dss_s *s) 95 { 96 qemu_set_irq(s->irq, s->dispc.irqst & s->dispc.irqen); 97 } 98 99 static void omap_rfbi_reset(struct omap_dss_s *s) 100 { 101 s->rfbi.idlemode = 0; 102 s->rfbi.control = 2; 103 s->rfbi.enable = 0; 104 s->rfbi.pixels = 0; 105 s->rfbi.skiplines = 0; 106 s->rfbi.busy = 0; 107 s->rfbi.config[0] = 0x00310000; 108 s->rfbi.config[1] = 0x00310000; 109 s->rfbi.time[0] = 0; 110 s->rfbi.time[1] = 0; 111 s->rfbi.time[2] = 0; 112 s->rfbi.time[3] = 0; 113 s->rfbi.data[0] = 0; 114 s->rfbi.data[1] = 0; 115 s->rfbi.data[2] = 0; 116 s->rfbi.data[3] = 0; 117 s->rfbi.data[4] = 0; 118 s->rfbi.data[5] = 0; 119 s->rfbi.vsync = 0; 120 s->rfbi.hsync = 0; 121 } 122 123 void omap_dss_reset(struct omap_dss_s *s) 124 { 125 s->autoidle = 0; 126 s->control = 0; 127 s->enable = 0; 128 129 s->dig.enable = 0; 130 s->dig.nx = 1; 131 s->dig.ny = 1; 132 133 s->lcd.enable = 0; 134 s->lcd.nx = 1; 135 s->lcd.ny = 1; 136 137 s->dispc.idlemode = 0; 138 s->dispc.irqst = 0; 139 s->dispc.irqen = 0; 140 s->dispc.control = 0; 141 s->dispc.config = 0; 142 s->dispc.capable = 0x161; 143 s->dispc.timing[0] = 0; 144 s->dispc.timing[1] = 0; 145 s->dispc.timing[2] = 0; 146 s->dispc.timing[3] = 0; 147 s->dispc.line = 0; 148 s->dispc.bg[0] = 0; 149 s->dispc.bg[1] = 0; 150 s->dispc.trans[0] = 0; 151 s->dispc.trans[1] = 0; 152 153 s->dispc.l[0].enable = 0; 154 s->dispc.l[0].bpp = 0; 155 s->dispc.l[0].addr[0] = 0; 156 s->dispc.l[0].addr[1] = 0; 157 s->dispc.l[0].addr[2] = 0; 158 s->dispc.l[0].posx = 0; 159 s->dispc.l[0].posy = 0; 160 s->dispc.l[0].nx = 1; 161 s->dispc.l[0].ny = 1; 162 s->dispc.l[0].attr = 0; 163 s->dispc.l[0].tresh = 0; 164 s->dispc.l[0].rowinc = 1; 165 s->dispc.l[0].colinc = 1; 166 s->dispc.l[0].wininc = 0; 167 168 omap_rfbi_reset(s); 169 omap_dispc_interrupt_update(s); 170 } 171 172 static uint64_t omap_diss_read(void *opaque, hwaddr addr, 173 unsigned size) 174 { 175 struct omap_dss_s *s = (struct omap_dss_s *) opaque; 176 177 if (size != 4) { 178 return omap_badwidth_read32(opaque, addr); 179 } 180 181 switch (addr) { 182 case 0x00: /* DSS_REVISIONNUMBER */ 183 return 0x20; 184 185 case 0x10: /* DSS_SYSCONFIG */ 186 return s->autoidle; 187 188 case 0x14: /* DSS_SYSSTATUS */ 189 return 1; /* RESETDONE */ 190 191 case 0x40: /* DSS_CONTROL */ 192 return s->control; 193 194 case 0x50: /* DSS_PSA_LCD_REG_1 */ 195 case 0x54: /* DSS_PSA_LCD_REG_2 */ 196 case 0x58: /* DSS_PSA_VIDEO_REG */ 197 /* TODO: fake some values when appropriate s->control bits are set */ 198 return 0; 199 200 case 0x5c: /* DSS_STATUS */ 201 return 1 + (s->control & 1); 202 203 default: 204 break; 205 } 206 OMAP_BAD_REG(addr); 207 return 0; 208 } 209 210 static void omap_diss_write(void *opaque, hwaddr addr, 211 uint64_t value, unsigned size) 212 { 213 struct omap_dss_s *s = (struct omap_dss_s *) opaque; 214 215 if (size != 4) { 216 omap_badwidth_write32(opaque, addr, value); 217 return; 218 } 219 220 switch (addr) { 221 case 0x00: /* DSS_REVISIONNUMBER */ 222 case 0x14: /* DSS_SYSSTATUS */ 223 case 0x50: /* DSS_PSA_LCD_REG_1 */ 224 case 0x54: /* DSS_PSA_LCD_REG_2 */ 225 case 0x58: /* DSS_PSA_VIDEO_REG */ 226 case 0x5c: /* DSS_STATUS */ 227 OMAP_RO_REG(addr); 228 break; 229 230 case 0x10: /* DSS_SYSCONFIG */ 231 if (value & 2) /* SOFTRESET */ 232 omap_dss_reset(s); 233 s->autoidle = value & 1; 234 break; 235 236 case 0x40: /* DSS_CONTROL */ 237 s->control = value & 0x3dd; 238 break; 239 240 default: 241 OMAP_BAD_REG(addr); 242 } 243 } 244 245 static const MemoryRegionOps omap_diss_ops = { 246 .read = omap_diss_read, 247 .write = omap_diss_write, 248 .endianness = DEVICE_NATIVE_ENDIAN, 249 }; 250 251 static uint64_t omap_disc_read(void *opaque, hwaddr addr, 252 unsigned size) 253 { 254 struct omap_dss_s *s = (struct omap_dss_s *) opaque; 255 256 if (size != 4) { 257 return omap_badwidth_read32(opaque, addr); 258 } 259 260 switch (addr) { 261 case 0x000: /* DISPC_REVISION */ 262 return 0x20; 263 264 case 0x010: /* DISPC_SYSCONFIG */ 265 return s->dispc.idlemode; 266 267 case 0x014: /* DISPC_SYSSTATUS */ 268 return 1; /* RESETDONE */ 269 270 case 0x018: /* DISPC_IRQSTATUS */ 271 return s->dispc.irqst; 272 273 case 0x01c: /* DISPC_IRQENABLE */ 274 return s->dispc.irqen; 275 276 case 0x040: /* DISPC_CONTROL */ 277 return s->dispc.control; 278 279 case 0x044: /* DISPC_CONFIG */ 280 return s->dispc.config; 281 282 case 0x048: /* DISPC_CAPABLE */ 283 return s->dispc.capable; 284 285 case 0x04c: /* DISPC_DEFAULT_COLOR0 */ 286 return s->dispc.bg[0]; 287 case 0x050: /* DISPC_DEFAULT_COLOR1 */ 288 return s->dispc.bg[1]; 289 case 0x054: /* DISPC_TRANS_COLOR0 */ 290 return s->dispc.trans[0]; 291 case 0x058: /* DISPC_TRANS_COLOR1 */ 292 return s->dispc.trans[1]; 293 294 case 0x05c: /* DISPC_LINE_STATUS */ 295 return 0x7ff; 296 case 0x060: /* DISPC_LINE_NUMBER */ 297 return s->dispc.line; 298 299 case 0x064: /* DISPC_TIMING_H */ 300 return s->dispc.timing[0]; 301 case 0x068: /* DISPC_TIMING_V */ 302 return s->dispc.timing[1]; 303 case 0x06c: /* DISPC_POL_FREQ */ 304 return s->dispc.timing[2]; 305 case 0x070: /* DISPC_DIVISOR */ 306 return s->dispc.timing[3]; 307 308 case 0x078: /* DISPC_SIZE_DIG */ 309 return ((s->dig.ny - 1) << 16) | (s->dig.nx - 1); 310 case 0x07c: /* DISPC_SIZE_LCD */ 311 return ((s->lcd.ny - 1) << 16) | (s->lcd.nx - 1); 312 313 case 0x080: /* DISPC_GFX_BA0 */ 314 return s->dispc.l[0].addr[0]; 315 case 0x084: /* DISPC_GFX_BA1 */ 316 return s->dispc.l[0].addr[1]; 317 case 0x088: /* DISPC_GFX_POSITION */ 318 return (s->dispc.l[0].posy << 16) | s->dispc.l[0].posx; 319 case 0x08c: /* DISPC_GFX_SIZE */ 320 return ((s->dispc.l[0].ny - 1) << 16) | (s->dispc.l[0].nx - 1); 321 case 0x0a0: /* DISPC_GFX_ATTRIBUTES */ 322 return s->dispc.l[0].attr; 323 case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */ 324 return s->dispc.l[0].tresh; 325 case 0x0a8: /* DISPC_GFX_FIFO_SIZE_STATUS */ 326 return 256; 327 case 0x0ac: /* DISPC_GFX_ROW_INC */ 328 return s->dispc.l[0].rowinc; 329 case 0x0b0: /* DISPC_GFX_PIXEL_INC */ 330 return s->dispc.l[0].colinc; 331 case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */ 332 return s->dispc.l[0].wininc; 333 case 0x0b8: /* DISPC_GFX_TABLE_BA */ 334 return s->dispc.l[0].addr[2]; 335 336 case 0x0bc: /* DISPC_VID1_BA0 */ 337 case 0x0c0: /* DISPC_VID1_BA1 */ 338 case 0x0c4: /* DISPC_VID1_POSITION */ 339 case 0x0c8: /* DISPC_VID1_SIZE */ 340 case 0x0cc: /* DISPC_VID1_ATTRIBUTES */ 341 case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */ 342 case 0x0d4: /* DISPC_VID1_FIFO_SIZE_STATUS */ 343 case 0x0d8: /* DISPC_VID1_ROW_INC */ 344 case 0x0dc: /* DISPC_VID1_PIXEL_INC */ 345 case 0x0e0: /* DISPC_VID1_FIR */ 346 case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */ 347 case 0x0e8: /* DISPC_VID1_ACCU0 */ 348 case 0x0ec: /* DISPC_VID1_ACCU1 */ 349 case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */ 350 case 0x14c: /* DISPC_VID2_BA0 */ 351 case 0x150: /* DISPC_VID2_BA1 */ 352 case 0x154: /* DISPC_VID2_POSITION */ 353 case 0x158: /* DISPC_VID2_SIZE */ 354 case 0x15c: /* DISPC_VID2_ATTRIBUTES */ 355 case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */ 356 case 0x164: /* DISPC_VID2_FIFO_SIZE_STATUS */ 357 case 0x168: /* DISPC_VID2_ROW_INC */ 358 case 0x16c: /* DISPC_VID2_PIXEL_INC */ 359 case 0x170: /* DISPC_VID2_FIR */ 360 case 0x174: /* DISPC_VID2_PICTURE_SIZE */ 361 case 0x178: /* DISPC_VID2_ACCU0 */ 362 case 0x17c: /* DISPC_VID2_ACCU1 */ 363 case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */ 364 case 0x1d4: /* DISPC_DATA_CYCLE1 */ 365 case 0x1d8: /* DISPC_DATA_CYCLE2 */ 366 case 0x1dc: /* DISPC_DATA_CYCLE3 */ 367 return 0; 368 369 default: 370 break; 371 } 372 OMAP_BAD_REG(addr); 373 return 0; 374 } 375 376 static void omap_disc_write(void *opaque, hwaddr addr, 377 uint64_t value, unsigned size) 378 { 379 struct omap_dss_s *s = (struct omap_dss_s *) opaque; 380 381 if (size != 4) { 382 omap_badwidth_write32(opaque, addr, value); 383 return; 384 } 385 386 switch (addr) { 387 case 0x010: /* DISPC_SYSCONFIG */ 388 if (value & 2) /* SOFTRESET */ 389 omap_dss_reset(s); 390 s->dispc.idlemode = value & 0x301b; 391 break; 392 393 case 0x018: /* DISPC_IRQSTATUS */ 394 s->dispc.irqst &= ~value; 395 omap_dispc_interrupt_update(s); 396 break; 397 398 case 0x01c: /* DISPC_IRQENABLE */ 399 s->dispc.irqen = value & 0xffff; 400 omap_dispc_interrupt_update(s); 401 break; 402 403 case 0x040: /* DISPC_CONTROL */ 404 s->dispc.control = value & 0x07ff9fff; 405 s->dig.enable = (value >> 1) & 1; 406 s->lcd.enable = (value >> 0) & 1; 407 if (value & (1 << 12)) /* OVERLAY_OPTIMIZATION */ 408 if (!((s->dispc.l[1].attr | s->dispc.l[2].attr) & 1)) { 409 fprintf(stderr, "%s: Overlay Optimization when no overlay " 410 "region effectively exists leads to " 411 "unpredictable behaviour!\n", __func__); 412 } 413 if (value & (1 << 6)) { /* GODIGITAL */ 414 /* XXX: Shadowed fields are: 415 * s->dispc.config 416 * s->dispc.capable 417 * s->dispc.bg[0] 418 * s->dispc.bg[1] 419 * s->dispc.trans[0] 420 * s->dispc.trans[1] 421 * s->dispc.line 422 * s->dispc.timing[0] 423 * s->dispc.timing[1] 424 * s->dispc.timing[2] 425 * s->dispc.timing[3] 426 * s->lcd.nx 427 * s->lcd.ny 428 * s->dig.nx 429 * s->dig.ny 430 * s->dispc.l[0].addr[0] 431 * s->dispc.l[0].addr[1] 432 * s->dispc.l[0].addr[2] 433 * s->dispc.l[0].posx 434 * s->dispc.l[0].posy 435 * s->dispc.l[0].nx 436 * s->dispc.l[0].ny 437 * s->dispc.l[0].tresh 438 * s->dispc.l[0].rowinc 439 * s->dispc.l[0].colinc 440 * s->dispc.l[0].wininc 441 * All they need to be loaded here from their shadow registers. 442 */ 443 } 444 if (value & (1 << 5)) { /* GOLCD */ 445 /* XXX: Likewise for LCD here. */ 446 } 447 s->dispc.invalidate = 1; 448 break; 449 450 case 0x044: /* DISPC_CONFIG */ 451 s->dispc.config = value & 0x3fff; 452 /* XXX: 453 * bits 2:1 (LOADMODE) reset to 0 after set to 1 and palette loaded 454 * bits 2:1 (LOADMODE) reset to 2 after set to 3 and palette loaded 455 */ 456 s->dispc.invalidate = 1; 457 break; 458 459 case 0x048: /* DISPC_CAPABLE */ 460 s->dispc.capable = value & 0x3ff; 461 break; 462 463 case 0x04c: /* DISPC_DEFAULT_COLOR0 */ 464 s->dispc.bg[0] = value & 0xffffff; 465 s->dispc.invalidate = 1; 466 break; 467 case 0x050: /* DISPC_DEFAULT_COLOR1 */ 468 s->dispc.bg[1] = value & 0xffffff; 469 s->dispc.invalidate = 1; 470 break; 471 case 0x054: /* DISPC_TRANS_COLOR0 */ 472 s->dispc.trans[0] = value & 0xffffff; 473 s->dispc.invalidate = 1; 474 break; 475 case 0x058: /* DISPC_TRANS_COLOR1 */ 476 s->dispc.trans[1] = value & 0xffffff; 477 s->dispc.invalidate = 1; 478 break; 479 480 case 0x060: /* DISPC_LINE_NUMBER */ 481 s->dispc.line = value & 0x7ff; 482 break; 483 484 case 0x064: /* DISPC_TIMING_H */ 485 s->dispc.timing[0] = value & 0x0ff0ff3f; 486 break; 487 case 0x068: /* DISPC_TIMING_V */ 488 s->dispc.timing[1] = value & 0x0ff0ff3f; 489 break; 490 case 0x06c: /* DISPC_POL_FREQ */ 491 s->dispc.timing[2] = value & 0x0003ffff; 492 break; 493 case 0x070: /* DISPC_DIVISOR */ 494 s->dispc.timing[3] = value & 0x00ff00ff; 495 break; 496 497 case 0x078: /* DISPC_SIZE_DIG */ 498 s->dig.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */ 499 s->dig.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */ 500 s->dispc.invalidate = 1; 501 break; 502 case 0x07c: /* DISPC_SIZE_LCD */ 503 s->lcd.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */ 504 s->lcd.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */ 505 s->dispc.invalidate = 1; 506 break; 507 case 0x080: /* DISPC_GFX_BA0 */ 508 s->dispc.l[0].addr[0] = (hwaddr) value; 509 s->dispc.invalidate = 1; 510 break; 511 case 0x084: /* DISPC_GFX_BA1 */ 512 s->dispc.l[0].addr[1] = (hwaddr) value; 513 s->dispc.invalidate = 1; 514 break; 515 case 0x088: /* DISPC_GFX_POSITION */ 516 s->dispc.l[0].posx = ((value >> 0) & 0x7ff); /* GFXPOSX */ 517 s->dispc.l[0].posy = ((value >> 16) & 0x7ff); /* GFXPOSY */ 518 s->dispc.invalidate = 1; 519 break; 520 case 0x08c: /* DISPC_GFX_SIZE */ 521 s->dispc.l[0].nx = ((value >> 0) & 0x7ff) + 1; /* GFXSIZEX */ 522 s->dispc.l[0].ny = ((value >> 16) & 0x7ff) + 1; /* GFXSIZEY */ 523 s->dispc.invalidate = 1; 524 break; 525 case 0x0a0: /* DISPC_GFX_ATTRIBUTES */ 526 s->dispc.l[0].attr = value & 0x7ff; 527 if (value & (3 << 9)) 528 fprintf(stderr, "%s: Big-endian pixel format not supported\n", 529 __func__); 530 s->dispc.l[0].enable = value & 1; 531 s->dispc.l[0].bpp = (value >> 1) & 0xf; 532 s->dispc.invalidate = 1; 533 break; 534 case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */ 535 s->dispc.l[0].tresh = value & 0x01ff01ff; 536 break; 537 case 0x0ac: /* DISPC_GFX_ROW_INC */ 538 s->dispc.l[0].rowinc = value; 539 s->dispc.invalidate = 1; 540 break; 541 case 0x0b0: /* DISPC_GFX_PIXEL_INC */ 542 s->dispc.l[0].colinc = value; 543 s->dispc.invalidate = 1; 544 break; 545 case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */ 546 s->dispc.l[0].wininc = value; 547 break; 548 case 0x0b8: /* DISPC_GFX_TABLE_BA */ 549 s->dispc.l[0].addr[2] = (hwaddr) value; 550 s->dispc.invalidate = 1; 551 break; 552 553 case 0x0bc: /* DISPC_VID1_BA0 */ 554 case 0x0c0: /* DISPC_VID1_BA1 */ 555 case 0x0c4: /* DISPC_VID1_POSITION */ 556 case 0x0c8: /* DISPC_VID1_SIZE */ 557 case 0x0cc: /* DISPC_VID1_ATTRIBUTES */ 558 case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */ 559 case 0x0d8: /* DISPC_VID1_ROW_INC */ 560 case 0x0dc: /* DISPC_VID1_PIXEL_INC */ 561 case 0x0e0: /* DISPC_VID1_FIR */ 562 case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */ 563 case 0x0e8: /* DISPC_VID1_ACCU0 */ 564 case 0x0ec: /* DISPC_VID1_ACCU1 */ 565 case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */ 566 case 0x14c: /* DISPC_VID2_BA0 */ 567 case 0x150: /* DISPC_VID2_BA1 */ 568 case 0x154: /* DISPC_VID2_POSITION */ 569 case 0x158: /* DISPC_VID2_SIZE */ 570 case 0x15c: /* DISPC_VID2_ATTRIBUTES */ 571 case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */ 572 case 0x168: /* DISPC_VID2_ROW_INC */ 573 case 0x16c: /* DISPC_VID2_PIXEL_INC */ 574 case 0x170: /* DISPC_VID2_FIR */ 575 case 0x174: /* DISPC_VID2_PICTURE_SIZE */ 576 case 0x178: /* DISPC_VID2_ACCU0 */ 577 case 0x17c: /* DISPC_VID2_ACCU1 */ 578 case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */ 579 case 0x1d4: /* DISPC_DATA_CYCLE1 */ 580 case 0x1d8: /* DISPC_DATA_CYCLE2 */ 581 case 0x1dc: /* DISPC_DATA_CYCLE3 */ 582 break; 583 584 default: 585 OMAP_BAD_REG(addr); 586 } 587 } 588 589 static const MemoryRegionOps omap_disc_ops = { 590 .read = omap_disc_read, 591 .write = omap_disc_write, 592 .endianness = DEVICE_NATIVE_ENDIAN, 593 }; 594 595 static void omap_rfbi_transfer_stop(struct omap_dss_s *s) 596 { 597 if (!s->rfbi.busy) 598 return; 599 600 /* TODO: in non-Bypass mode we probably need to just deassert the DRQ. */ 601 602 s->rfbi.busy = 0; 603 } 604 605 static void omap_rfbi_transfer_start(struct omap_dss_s *s) 606 { 607 void *data; 608 hwaddr len; 609 hwaddr data_addr; 610 int pitch; 611 static void *bounce_buffer; 612 static hwaddr bounce_len; 613 614 if (!s->rfbi.enable || s->rfbi.busy) 615 return; 616 617 if (s->rfbi.control & (1 << 1)) { /* BYPASS */ 618 /* TODO: in non-Bypass mode we probably need to just assert the 619 * DRQ and wait for DMA to write the pixels. */ 620 fprintf(stderr, "%s: Bypass mode unimplemented\n", __func__); 621 return; 622 } 623 624 if (!(s->dispc.control & (1 << 11))) /* RFBIMODE */ 625 return; 626 /* TODO: check that LCD output is enabled in DISPC. */ 627 628 s->rfbi.busy = 1; 629 630 len = s->rfbi.pixels * 2; 631 632 data_addr = s->dispc.l[0].addr[0]; 633 data = cpu_physical_memory_map(data_addr, &len, 0); 634 if (data && len != s->rfbi.pixels * 2) { 635 cpu_physical_memory_unmap(data, len, 0, 0); 636 data = NULL; 637 len = s->rfbi.pixels * 2; 638 } 639 if (!data) { 640 if (len > bounce_len) { 641 bounce_buffer = g_realloc(bounce_buffer, len); 642 } 643 data = bounce_buffer; 644 cpu_physical_memory_read(data_addr, data, len); 645 } 646 647 /* TODO bpp */ 648 s->rfbi.pixels = 0; 649 650 /* TODO: negative values */ 651 pitch = s->dispc.l[0].nx + (s->dispc.l[0].rowinc - 1) / 2; 652 653 if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) 654 s->rfbi.chip[0]->block(s->rfbi.chip[0]->opaque, 1, data, len, pitch); 655 if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) 656 s->rfbi.chip[1]->block(s->rfbi.chip[1]->opaque, 1, data, len, pitch); 657 658 if (data != bounce_buffer) { 659 cpu_physical_memory_unmap(data, len, 0, len); 660 } 661 662 omap_rfbi_transfer_stop(s); 663 664 /* TODO */ 665 s->dispc.irqst |= 1; /* FRAMEDONE */ 666 omap_dispc_interrupt_update(s); 667 } 668 669 static uint64_t omap_rfbi_read(void *opaque, hwaddr addr, 670 unsigned size) 671 { 672 struct omap_dss_s *s = (struct omap_dss_s *) opaque; 673 674 if (size != 4) { 675 return omap_badwidth_read32(opaque, addr); 676 } 677 678 switch (addr) { 679 case 0x00: /* RFBI_REVISION */ 680 return 0x10; 681 682 case 0x10: /* RFBI_SYSCONFIG */ 683 return s->rfbi.idlemode; 684 685 case 0x14: /* RFBI_SYSSTATUS */ 686 return 1 | (s->rfbi.busy << 8); /* RESETDONE */ 687 688 case 0x40: /* RFBI_CONTROL */ 689 return s->rfbi.control; 690 691 case 0x44: /* RFBI_PIXELCNT */ 692 return s->rfbi.pixels; 693 694 case 0x48: /* RFBI_LINE_NUMBER */ 695 return s->rfbi.skiplines; 696 697 case 0x58: /* RFBI_READ */ 698 case 0x5c: /* RFBI_STATUS */ 699 return s->rfbi.rxbuf; 700 701 case 0x60: /* RFBI_CONFIG0 */ 702 return s->rfbi.config[0]; 703 case 0x64: /* RFBI_ONOFF_TIME0 */ 704 return s->rfbi.time[0]; 705 case 0x68: /* RFBI_CYCLE_TIME0 */ 706 return s->rfbi.time[1]; 707 case 0x6c: /* RFBI_DATA_CYCLE1_0 */ 708 return s->rfbi.data[0]; 709 case 0x70: /* RFBI_DATA_CYCLE2_0 */ 710 return s->rfbi.data[1]; 711 case 0x74: /* RFBI_DATA_CYCLE3_0 */ 712 return s->rfbi.data[2]; 713 714 case 0x78: /* RFBI_CONFIG1 */ 715 return s->rfbi.config[1]; 716 case 0x7c: /* RFBI_ONOFF_TIME1 */ 717 return s->rfbi.time[2]; 718 case 0x80: /* RFBI_CYCLE_TIME1 */ 719 return s->rfbi.time[3]; 720 case 0x84: /* RFBI_DATA_CYCLE1_1 */ 721 return s->rfbi.data[3]; 722 case 0x88: /* RFBI_DATA_CYCLE2_1 */ 723 return s->rfbi.data[4]; 724 case 0x8c: /* RFBI_DATA_CYCLE3_1 */ 725 return s->rfbi.data[5]; 726 727 case 0x90: /* RFBI_VSYNC_WIDTH */ 728 return s->rfbi.vsync; 729 case 0x94: /* RFBI_HSYNC_WIDTH */ 730 return s->rfbi.hsync; 731 } 732 OMAP_BAD_REG(addr); 733 return 0; 734 } 735 736 static void omap_rfbi_write(void *opaque, hwaddr addr, 737 uint64_t value, unsigned size) 738 { 739 struct omap_dss_s *s = (struct omap_dss_s *) opaque; 740 741 if (size != 4) { 742 omap_badwidth_write32(opaque, addr, value); 743 return; 744 } 745 746 switch (addr) { 747 case 0x10: /* RFBI_SYSCONFIG */ 748 if (value & 2) /* SOFTRESET */ 749 omap_rfbi_reset(s); 750 s->rfbi.idlemode = value & 0x19; 751 break; 752 753 case 0x40: /* RFBI_CONTROL */ 754 s->rfbi.control = value & 0xf; 755 s->rfbi.enable = value & 1; 756 if (value & (1 << 4) && /* ITE */ 757 !(s->rfbi.config[0] & s->rfbi.config[1] & 0xc)) 758 omap_rfbi_transfer_start(s); 759 break; 760 761 case 0x44: /* RFBI_PIXELCNT */ 762 s->rfbi.pixels = value; 763 break; 764 765 case 0x48: /* RFBI_LINE_NUMBER */ 766 s->rfbi.skiplines = value & 0x7ff; 767 break; 768 769 case 0x4c: /* RFBI_CMD */ 770 if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) 771 s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 0, value & 0xffff); 772 if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) 773 s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 0, value & 0xffff); 774 break; 775 case 0x50: /* RFBI_PARAM */ 776 if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) 777 s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff); 778 if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) 779 s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff); 780 break; 781 case 0x54: /* RFBI_DATA */ 782 /* TODO: take into account the format set up in s->rfbi.config[?] and 783 * s->rfbi.data[?], but special-case the most usual scenario so that 784 * speed doesn't suffer. */ 785 if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) { 786 s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff); 787 s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value >> 16); 788 } 789 if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) { 790 s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff); 791 s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value >> 16); 792 } 793 if (!-- s->rfbi.pixels) 794 omap_rfbi_transfer_stop(s); 795 break; 796 case 0x58: /* RFBI_READ */ 797 if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) 798 s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1); 799 else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) 800 s->rfbi.rxbuf = s->rfbi.chip[1]->read(s->rfbi.chip[1]->opaque, 1); 801 if (!-- s->rfbi.pixels) 802 omap_rfbi_transfer_stop(s); 803 break; 804 805 case 0x5c: /* RFBI_STATUS */ 806 if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) 807 s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0); 808 else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) 809 s->rfbi.rxbuf = s->rfbi.chip[1]->read(s->rfbi.chip[1]->opaque, 0); 810 if (!-- s->rfbi.pixels) 811 omap_rfbi_transfer_stop(s); 812 break; 813 814 case 0x60: /* RFBI_CONFIG0 */ 815 s->rfbi.config[0] = value & 0x003f1fff; 816 break; 817 818 case 0x64: /* RFBI_ONOFF_TIME0 */ 819 s->rfbi.time[0] = value & 0x3fffffff; 820 break; 821 case 0x68: /* RFBI_CYCLE_TIME0 */ 822 s->rfbi.time[1] = value & 0x0fffffff; 823 break; 824 case 0x6c: /* RFBI_DATA_CYCLE1_0 */ 825 s->rfbi.data[0] = value & 0x0f1f0f1f; 826 break; 827 case 0x70: /* RFBI_DATA_CYCLE2_0 */ 828 s->rfbi.data[1] = value & 0x0f1f0f1f; 829 break; 830 case 0x74: /* RFBI_DATA_CYCLE3_0 */ 831 s->rfbi.data[2] = value & 0x0f1f0f1f; 832 break; 833 case 0x78: /* RFBI_CONFIG1 */ 834 s->rfbi.config[1] = value & 0x003f1fff; 835 break; 836 837 case 0x7c: /* RFBI_ONOFF_TIME1 */ 838 s->rfbi.time[2] = value & 0x3fffffff; 839 break; 840 case 0x80: /* RFBI_CYCLE_TIME1 */ 841 s->rfbi.time[3] = value & 0x0fffffff; 842 break; 843 case 0x84: /* RFBI_DATA_CYCLE1_1 */ 844 s->rfbi.data[3] = value & 0x0f1f0f1f; 845 break; 846 case 0x88: /* RFBI_DATA_CYCLE2_1 */ 847 s->rfbi.data[4] = value & 0x0f1f0f1f; 848 break; 849 case 0x8c: /* RFBI_DATA_CYCLE3_1 */ 850 s->rfbi.data[5] = value & 0x0f1f0f1f; 851 break; 852 853 case 0x90: /* RFBI_VSYNC_WIDTH */ 854 s->rfbi.vsync = value & 0xffff; 855 break; 856 case 0x94: /* RFBI_HSYNC_WIDTH */ 857 s->rfbi.hsync = value & 0xffff; 858 break; 859 860 default: 861 OMAP_BAD_REG(addr); 862 } 863 } 864 865 static const MemoryRegionOps omap_rfbi_ops = { 866 .read = omap_rfbi_read, 867 .write = omap_rfbi_write, 868 .endianness = DEVICE_NATIVE_ENDIAN, 869 }; 870 871 static uint64_t omap_venc_read(void *opaque, hwaddr addr, 872 unsigned size) 873 { 874 if (size != 4) { 875 return omap_badwidth_read32(opaque, addr); 876 } 877 878 switch (addr) { 879 case 0x00: /* REV_ID */ 880 case 0x04: /* STATUS */ 881 case 0x08: /* F_CONTROL */ 882 case 0x10: /* VIDOUT_CTRL */ 883 case 0x14: /* SYNC_CTRL */ 884 case 0x1c: /* LLEN */ 885 case 0x20: /* FLENS */ 886 case 0x24: /* HFLTR_CTRL */ 887 case 0x28: /* CC_CARR_WSS_CARR */ 888 case 0x2c: /* C_PHASE */ 889 case 0x30: /* GAIN_U */ 890 case 0x34: /* GAIN_V */ 891 case 0x38: /* GAIN_Y */ 892 case 0x3c: /* BLACK_LEVEL */ 893 case 0x40: /* BLANK_LEVEL */ 894 case 0x44: /* X_COLOR */ 895 case 0x48: /* M_CONTROL */ 896 case 0x4c: /* BSTAMP_WSS_DATA */ 897 case 0x50: /* S_CARR */ 898 case 0x54: /* LINE21 */ 899 case 0x58: /* LN_SEL */ 900 case 0x5c: /* L21__WC_CTL */ 901 case 0x60: /* HTRIGGER_VTRIGGER */ 902 case 0x64: /* SAVID__EAVID */ 903 case 0x68: /* FLEN__FAL */ 904 case 0x6c: /* LAL__PHASE_RESET */ 905 case 0x70: /* HS_INT_START_STOP_X */ 906 case 0x74: /* HS_EXT_START_STOP_X */ 907 case 0x78: /* VS_INT_START_X */ 908 case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */ 909 case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */ 910 case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */ 911 case 0x88: /* VS_EXT_STOP_Y */ 912 case 0x90: /* AVID_START_STOP_X */ 913 case 0x94: /* AVID_START_STOP_Y */ 914 case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */ 915 case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */ 916 case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */ 917 case 0xb0: /* TVDETGP_INT_START_STOP_X */ 918 case 0xb4: /* TVDETGP_INT_START_STOP_Y */ 919 case 0xb8: /* GEN_CTRL */ 920 case 0xc4: /* DAC_TST__DAC_A */ 921 case 0xc8: /* DAC_B__DAC_C */ 922 return 0; 923 924 default: 925 break; 926 } 927 OMAP_BAD_REG(addr); 928 return 0; 929 } 930 931 static void omap_venc_write(void *opaque, hwaddr addr, 932 uint64_t value, unsigned size) 933 { 934 if (size != 4) { 935 omap_badwidth_write32(opaque, addr, size); 936 return; 937 } 938 939 switch (addr) { 940 case 0x08: /* F_CONTROL */ 941 case 0x10: /* VIDOUT_CTRL */ 942 case 0x14: /* SYNC_CTRL */ 943 case 0x1c: /* LLEN */ 944 case 0x20: /* FLENS */ 945 case 0x24: /* HFLTR_CTRL */ 946 case 0x28: /* CC_CARR_WSS_CARR */ 947 case 0x2c: /* C_PHASE */ 948 case 0x30: /* GAIN_U */ 949 case 0x34: /* GAIN_V */ 950 case 0x38: /* GAIN_Y */ 951 case 0x3c: /* BLACK_LEVEL */ 952 case 0x40: /* BLANK_LEVEL */ 953 case 0x44: /* X_COLOR */ 954 case 0x48: /* M_CONTROL */ 955 case 0x4c: /* BSTAMP_WSS_DATA */ 956 case 0x50: /* S_CARR */ 957 case 0x54: /* LINE21 */ 958 case 0x58: /* LN_SEL */ 959 case 0x5c: /* L21__WC_CTL */ 960 case 0x60: /* HTRIGGER_VTRIGGER */ 961 case 0x64: /* SAVID__EAVID */ 962 case 0x68: /* FLEN__FAL */ 963 case 0x6c: /* LAL__PHASE_RESET */ 964 case 0x70: /* HS_INT_START_STOP_X */ 965 case 0x74: /* HS_EXT_START_STOP_X */ 966 case 0x78: /* VS_INT_START_X */ 967 case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */ 968 case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */ 969 case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */ 970 case 0x88: /* VS_EXT_STOP_Y */ 971 case 0x90: /* AVID_START_STOP_X */ 972 case 0x94: /* AVID_START_STOP_Y */ 973 case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */ 974 case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */ 975 case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */ 976 case 0xb0: /* TVDETGP_INT_START_STOP_X */ 977 case 0xb4: /* TVDETGP_INT_START_STOP_Y */ 978 case 0xb8: /* GEN_CTRL */ 979 case 0xc4: /* DAC_TST__DAC_A */ 980 case 0xc8: /* DAC_B__DAC_C */ 981 break; 982 983 default: 984 OMAP_BAD_REG(addr); 985 } 986 } 987 988 static const MemoryRegionOps omap_venc_ops = { 989 .read = omap_venc_read, 990 .write = omap_venc_write, 991 .endianness = DEVICE_NATIVE_ENDIAN, 992 }; 993 994 static uint64_t omap_im3_read(void *opaque, hwaddr addr, 995 unsigned size) 996 { 997 if (size != 4) { 998 return omap_badwidth_read32(opaque, addr); 999 } 1000 1001 switch (addr) { 1002 case 0x0a8: /* SBIMERRLOGA */ 1003 case 0x0b0: /* SBIMERRLOG */ 1004 case 0x190: /* SBIMSTATE */ 1005 case 0x198: /* SBTMSTATE_L */ 1006 case 0x19c: /* SBTMSTATE_H */ 1007 case 0x1a8: /* SBIMCONFIG_L */ 1008 case 0x1ac: /* SBIMCONFIG_H */ 1009 case 0x1f8: /* SBID_L */ 1010 case 0x1fc: /* SBID_H */ 1011 return 0; 1012 1013 default: 1014 break; 1015 } 1016 OMAP_BAD_REG(addr); 1017 return 0; 1018 } 1019 1020 static void omap_im3_write(void *opaque, hwaddr addr, 1021 uint64_t value, unsigned size) 1022 { 1023 if (size != 4) { 1024 omap_badwidth_write32(opaque, addr, value); 1025 return; 1026 } 1027 1028 switch (addr) { 1029 case 0x0b0: /* SBIMERRLOG */ 1030 case 0x190: /* SBIMSTATE */ 1031 case 0x198: /* SBTMSTATE_L */ 1032 case 0x19c: /* SBTMSTATE_H */ 1033 case 0x1a8: /* SBIMCONFIG_L */ 1034 case 0x1ac: /* SBIMCONFIG_H */ 1035 break; 1036 1037 default: 1038 OMAP_BAD_REG(addr); 1039 } 1040 } 1041 1042 static const MemoryRegionOps omap_im3_ops = { 1043 .read = omap_im3_read, 1044 .write = omap_im3_write, 1045 .endianness = DEVICE_NATIVE_ENDIAN, 1046 }; 1047 1048 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, 1049 MemoryRegion *sysmem, 1050 hwaddr l3_base, 1051 qemu_irq irq, qemu_irq drq, 1052 omap_clk fck1, omap_clk fck2, omap_clk ck54m, 1053 omap_clk ick1, omap_clk ick2) 1054 { 1055 struct omap_dss_s *s = g_new0(struct omap_dss_s, 1); 1056 1057 s->irq = irq; 1058 s->drq = drq; 1059 omap_dss_reset(s); 1060 1061 memory_region_init_io(&s->iomem_diss1, NULL, &omap_diss_ops, s, "omap.diss1", 1062 omap_l4_region_size(ta, 0)); 1063 memory_region_init_io(&s->iomem_disc1, NULL, &omap_disc_ops, s, "omap.disc1", 1064 omap_l4_region_size(ta, 1)); 1065 memory_region_init_io(&s->iomem_rfbi1, NULL, &omap_rfbi_ops, s, "omap.rfbi1", 1066 omap_l4_region_size(ta, 2)); 1067 memory_region_init_io(&s->iomem_venc1, NULL, &omap_venc_ops, s, "omap.venc1", 1068 omap_l4_region_size(ta, 3)); 1069 memory_region_init_io(&s->iomem_im3, NULL, &omap_im3_ops, s, 1070 "omap.im3", 0x1000); 1071 1072 omap_l4_attach(ta, 0, &s->iomem_diss1); 1073 omap_l4_attach(ta, 1, &s->iomem_disc1); 1074 omap_l4_attach(ta, 2, &s->iomem_rfbi1); 1075 omap_l4_attach(ta, 3, &s->iomem_venc1); 1076 memory_region_add_subregion(sysmem, l3_base, &s->iomem_im3); 1077 1078 #if 0 1079 s->state = graphic_console_init(omap_update_display, 1080 omap_invalidate_display, omap_screen_dump, s); 1081 #endif 1082 1083 return s; 1084 } 1085 1086 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip) 1087 { 1088 if (cs < 0 || cs > 1) 1089 hw_error("%s: wrong CS %i\n", __func__, cs); 1090 s->rfbi.chip[cs] = chip; 1091 } 1092