1 /* 2 * QEMU G364 framebuffer Emulator. 3 * 4 * Copyright (c) 2007-2011 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "hw/hw.h" 21 #include "ui/console.h" 22 #include "ui/pixel_ops.h" 23 #include "trace.h" 24 #include "hw/sysbus.h" 25 26 typedef struct G364State { 27 /* hardware */ 28 uint8_t *vram; 29 uint32_t vram_size; 30 qemu_irq irq; 31 MemoryRegion mem_vram; 32 MemoryRegion mem_ctrl; 33 /* registers */ 34 uint8_t color_palette[256][3]; 35 uint8_t cursor_palette[3][3]; 36 uint16_t cursor[512]; 37 uint32_t cursor_position; 38 uint32_t ctla; 39 uint32_t top_of_screen; 40 uint32_t width, height; /* in pixels */ 41 /* display refresh support */ 42 QemuConsole *con; 43 int depth; 44 int blanked; 45 } G364State; 46 47 #define REG_BOOT 0x000000 48 #define REG_DISPLAY 0x000118 49 #define REG_VDISPLAY 0x000150 50 #define REG_CTLA 0x000300 51 #define REG_TOP 0x000400 52 #define REG_CURS_PAL 0x000508 53 #define REG_CURS_POS 0x000638 54 #define REG_CLR_PAL 0x000800 55 #define REG_CURS_PAT 0x001000 56 #define REG_RESET 0x100000 57 58 #define CTLA_FORCE_BLANK 0x00000400 59 #define CTLA_NO_CURSOR 0x00800000 60 61 #define G364_PAGE_SIZE 4096 62 63 static inline int check_dirty(G364State *s, ram_addr_t page) 64 { 65 return memory_region_get_dirty(&s->mem_vram, page, G364_PAGE_SIZE, 66 DIRTY_MEMORY_VGA); 67 } 68 69 static inline void reset_dirty(G364State *s, 70 ram_addr_t page_min, ram_addr_t page_max) 71 { 72 memory_region_reset_dirty(&s->mem_vram, 73 page_min, 74 page_max + G364_PAGE_SIZE - page_min - 1, 75 DIRTY_MEMORY_VGA); 76 } 77 78 static void g364fb_draw_graphic8(G364State *s) 79 { 80 DisplaySurface *surface = qemu_console_surface(s->con); 81 int i, w; 82 uint8_t *vram; 83 uint8_t *data_display, *dd; 84 ram_addr_t page, page_min, page_max; 85 int x, y; 86 int xmin, xmax; 87 int ymin, ymax; 88 int xcursor, ycursor; 89 unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b); 90 91 switch (surface_bits_per_pixel(surface)) { 92 case 8: 93 rgb_to_pixel = rgb_to_pixel8; 94 w = 1; 95 break; 96 case 15: 97 rgb_to_pixel = rgb_to_pixel15; 98 w = 2; 99 break; 100 case 16: 101 rgb_to_pixel = rgb_to_pixel16; 102 w = 2; 103 break; 104 case 32: 105 rgb_to_pixel = rgb_to_pixel32; 106 w = 4; 107 break; 108 default: 109 hw_error("g364: unknown host depth %d", 110 surface_bits_per_pixel(surface)); 111 return; 112 } 113 114 page = 0; 115 page_min = (ram_addr_t)-1; 116 page_max = 0; 117 118 x = y = 0; 119 xmin = s->width; 120 xmax = 0; 121 ymin = s->height; 122 ymax = 0; 123 124 if (!(s->ctla & CTLA_NO_CURSOR)) { 125 xcursor = s->cursor_position >> 12; 126 ycursor = s->cursor_position & 0xfff; 127 } else { 128 xcursor = ycursor = -65; 129 } 130 131 vram = s->vram + s->top_of_screen; 132 /* XXX: out of range in vram? */ 133 data_display = dd = surface_data(surface); 134 while (y < s->height) { 135 if (check_dirty(s, page)) { 136 if (y < ymin) 137 ymin = ymax = y; 138 if (page_min == (ram_addr_t)-1) 139 page_min = page; 140 page_max = page; 141 if (x < xmin) 142 xmin = x; 143 for (i = 0; i < G364_PAGE_SIZE; i++) { 144 uint8_t index; 145 unsigned int color; 146 if (unlikely((y >= ycursor && y < ycursor + 64) && 147 (x >= xcursor && x < xcursor + 64))) { 148 /* pointer area */ 149 int xdiff = x - xcursor; 150 uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8]; 151 int op = (curs >> ((xdiff & 7) * 2)) & 3; 152 if (likely(op == 0)) { 153 /* transparent */ 154 index = *vram; 155 color = (*rgb_to_pixel)( 156 s->color_palette[index][0], 157 s->color_palette[index][1], 158 s->color_palette[index][2]); 159 } else { 160 /* get cursor color */ 161 index = op - 1; 162 color = (*rgb_to_pixel)( 163 s->cursor_palette[index][0], 164 s->cursor_palette[index][1], 165 s->cursor_palette[index][2]); 166 } 167 } else { 168 /* normal area */ 169 index = *vram; 170 color = (*rgb_to_pixel)( 171 s->color_palette[index][0], 172 s->color_palette[index][1], 173 s->color_palette[index][2]); 174 } 175 memcpy(dd, &color, w); 176 dd += w; 177 x++; 178 vram++; 179 if (x == s->width) { 180 xmax = s->width - 1; 181 y++; 182 if (y == s->height) { 183 ymax = s->height - 1; 184 goto done; 185 } 186 data_display = dd = data_display + surface_stride(surface); 187 xmin = 0; 188 x = 0; 189 } 190 } 191 if (x > xmax) 192 xmax = x; 193 if (y > ymax) 194 ymax = y; 195 } else { 196 int dy; 197 if (page_min != (ram_addr_t)-1) { 198 reset_dirty(s, page_min, page_max); 199 page_min = (ram_addr_t)-1; 200 page_max = 0; 201 dpy_gfx_update(s->con, xmin, ymin, 202 xmax - xmin + 1, ymax - ymin + 1); 203 xmin = s->width; 204 xmax = 0; 205 ymin = s->height; 206 ymax = 0; 207 } 208 x += G364_PAGE_SIZE; 209 dy = x / s->width; 210 x = x % s->width; 211 y += dy; 212 vram += G364_PAGE_SIZE; 213 data_display += dy * surface_stride(surface); 214 dd = data_display + x * w; 215 } 216 page += G364_PAGE_SIZE; 217 } 218 219 done: 220 if (page_min != (ram_addr_t)-1) { 221 dpy_gfx_update(s->con, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); 222 reset_dirty(s, page_min, page_max); 223 } 224 } 225 226 static void g364fb_draw_blank(G364State *s) 227 { 228 DisplaySurface *surface = qemu_console_surface(s->con); 229 int i, w; 230 uint8_t *d; 231 232 if (s->blanked) { 233 /* Screen is already blank. No need to redraw it */ 234 return; 235 } 236 237 w = s->width * surface_bytes_per_pixel(surface); 238 d = surface_data(surface); 239 for (i = 0; i < s->height; i++) { 240 memset(d, 0, w); 241 d += surface_stride(surface); 242 } 243 244 dpy_gfx_update(s->con, 0, 0, s->width, s->height); 245 s->blanked = 1; 246 } 247 248 static void g364fb_update_display(void *opaque) 249 { 250 G364State *s = opaque; 251 DisplaySurface *surface = qemu_console_surface(s->con); 252 253 qemu_flush_coalesced_mmio_buffer(); 254 255 if (s->width == 0 || s->height == 0) 256 return; 257 258 if (s->width != surface_width(surface) || 259 s->height != surface_height(surface)) { 260 qemu_console_resize(s->con, s->width, s->height); 261 } 262 263 memory_region_sync_dirty_bitmap(&s->mem_vram); 264 if (s->ctla & CTLA_FORCE_BLANK) { 265 g364fb_draw_blank(s); 266 } else if (s->depth == 8) { 267 g364fb_draw_graphic8(s); 268 } else { 269 error_report("g364: unknown guest depth %d", s->depth); 270 } 271 272 qemu_irq_raise(s->irq); 273 } 274 275 static inline void g364fb_invalidate_display(void *opaque) 276 { 277 G364State *s = opaque; 278 279 s->blanked = 0; 280 memory_region_set_dirty(&s->mem_vram, 0, s->vram_size); 281 } 282 283 static void g364fb_reset(G364State *s) 284 { 285 qemu_irq_lower(s->irq); 286 287 memset(s->color_palette, 0, sizeof(s->color_palette)); 288 memset(s->cursor_palette, 0, sizeof(s->cursor_palette)); 289 memset(s->cursor, 0, sizeof(s->cursor)); 290 s->cursor_position = 0; 291 s->ctla = 0; 292 s->top_of_screen = 0; 293 s->width = s->height = 0; 294 memset(s->vram, 0, s->vram_size); 295 g364fb_invalidate_display(s); 296 } 297 298 /* called for accesses to io ports */ 299 static uint64_t g364fb_ctrl_read(void *opaque, 300 hwaddr addr, 301 unsigned int size) 302 { 303 G364State *s = opaque; 304 uint32_t val; 305 306 if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { 307 /* cursor pattern */ 308 int idx = (addr - REG_CURS_PAT) >> 3; 309 val = s->cursor[idx]; 310 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { 311 /* cursor palette */ 312 int idx = (addr - REG_CURS_PAL) >> 3; 313 val = ((uint32_t)s->cursor_palette[idx][0] << 16); 314 val |= ((uint32_t)s->cursor_palette[idx][1] << 8); 315 val |= ((uint32_t)s->cursor_palette[idx][2] << 0); 316 } else { 317 switch (addr) { 318 case REG_DISPLAY: 319 val = s->width / 4; 320 break; 321 case REG_VDISPLAY: 322 val = s->height * 2; 323 break; 324 case REG_CTLA: 325 val = s->ctla; 326 break; 327 default: 328 { 329 error_report("g364: invalid read at [" TARGET_FMT_plx "]", 330 addr); 331 val = 0; 332 break; 333 } 334 } 335 } 336 337 trace_g364fb_read(addr, val); 338 339 return val; 340 } 341 342 static void g364fb_update_depth(G364State *s) 343 { 344 static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 }; 345 s->depth = depths[(s->ctla & 0x00700000) >> 20]; 346 } 347 348 static void g364_invalidate_cursor_position(G364State *s) 349 { 350 DisplaySurface *surface = qemu_console_surface(s->con); 351 int ymin, ymax, start, end; 352 353 /* invalidate only near the cursor */ 354 ymin = s->cursor_position & 0xfff; 355 ymax = MIN(s->height, ymin + 64); 356 start = ymin * surface_stride(surface); 357 end = (ymax + 1) * surface_stride(surface); 358 359 memory_region_set_dirty(&s->mem_vram, start, end - start); 360 } 361 362 static void g364fb_ctrl_write(void *opaque, 363 hwaddr addr, 364 uint64_t val, 365 unsigned int size) 366 { 367 G364State *s = opaque; 368 369 trace_g364fb_write(addr, val); 370 371 if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) { 372 /* color palette */ 373 int idx = (addr - REG_CLR_PAL) >> 3; 374 s->color_palette[idx][0] = (val >> 16) & 0xff; 375 s->color_palette[idx][1] = (val >> 8) & 0xff; 376 s->color_palette[idx][2] = val & 0xff; 377 g364fb_invalidate_display(s); 378 } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { 379 /* cursor pattern */ 380 int idx = (addr - REG_CURS_PAT) >> 3; 381 s->cursor[idx] = val; 382 g364fb_invalidate_display(s); 383 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { 384 /* cursor palette */ 385 int idx = (addr - REG_CURS_PAL) >> 3; 386 s->cursor_palette[idx][0] = (val >> 16) & 0xff; 387 s->cursor_palette[idx][1] = (val >> 8) & 0xff; 388 s->cursor_palette[idx][2] = val & 0xff; 389 g364fb_invalidate_display(s); 390 } else { 391 switch (addr) { 392 case REG_BOOT: /* Boot timing */ 393 case 0x00108: /* Line timing: half sync */ 394 case 0x00110: /* Line timing: back porch */ 395 case 0x00120: /* Line timing: short display */ 396 case 0x00128: /* Frame timing: broad pulse */ 397 case 0x00130: /* Frame timing: v sync */ 398 case 0x00138: /* Frame timing: v preequalise */ 399 case 0x00140: /* Frame timing: v postequalise */ 400 case 0x00148: /* Frame timing: v blank */ 401 case 0x00158: /* Line timing: line time */ 402 case 0x00160: /* Frame store: line start */ 403 case 0x00168: /* vram cycle: mem init */ 404 case 0x00170: /* vram cycle: transfer delay */ 405 case 0x00200: /* vram cycle: mask register */ 406 /* ignore */ 407 break; 408 case REG_TOP: 409 s->top_of_screen = val; 410 g364fb_invalidate_display(s); 411 break; 412 case REG_DISPLAY: 413 s->width = val * 4; 414 break; 415 case REG_VDISPLAY: 416 s->height = val / 2; 417 break; 418 case REG_CTLA: 419 s->ctla = val; 420 g364fb_update_depth(s); 421 g364fb_invalidate_display(s); 422 break; 423 case REG_CURS_POS: 424 g364_invalidate_cursor_position(s); 425 s->cursor_position = val; 426 g364_invalidate_cursor_position(s); 427 break; 428 case REG_RESET: 429 g364fb_reset(s); 430 break; 431 default: 432 error_report("g364: invalid write of 0x%" PRIx64 433 " at [" TARGET_FMT_plx "]", val, addr); 434 break; 435 } 436 } 437 qemu_irq_lower(s->irq); 438 } 439 440 static const MemoryRegionOps g364fb_ctrl_ops = { 441 .read = g364fb_ctrl_read, 442 .write = g364fb_ctrl_write, 443 .endianness = DEVICE_LITTLE_ENDIAN, 444 .impl.min_access_size = 4, 445 .impl.max_access_size = 4, 446 }; 447 448 static int g364fb_post_load(void *opaque, int version_id) 449 { 450 G364State *s = opaque; 451 452 /* force refresh */ 453 g364fb_update_depth(s); 454 g364fb_invalidate_display(s); 455 456 return 0; 457 } 458 459 static const VMStateDescription vmstate_g364fb = { 460 .name = "g364fb", 461 .version_id = 1, 462 .minimum_version_id = 1, 463 .post_load = g364fb_post_load, 464 .fields = (VMStateField[]) { 465 VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, 0, vram_size), 466 VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3), 467 VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9), 468 VMSTATE_UINT16_ARRAY(cursor, G364State, 512), 469 VMSTATE_UINT32(cursor_position, G364State), 470 VMSTATE_UINT32(ctla, G364State), 471 VMSTATE_UINT32(top_of_screen, G364State), 472 VMSTATE_UINT32(width, G364State), 473 VMSTATE_UINT32(height, G364State), 474 VMSTATE_END_OF_LIST() 475 } 476 }; 477 478 static const GraphicHwOps g364fb_ops = { 479 .invalidate = g364fb_invalidate_display, 480 .gfx_update = g364fb_update_display, 481 }; 482 483 static void g364fb_init(DeviceState *dev, G364State *s) 484 { 485 s->vram = g_malloc0(s->vram_size); 486 487 s->con = graphic_console_init(dev, 0, &g364fb_ops, s); 488 489 memory_region_init_io(&s->mem_ctrl, NULL, &g364fb_ctrl_ops, s, "ctrl", 0x180000); 490 memory_region_init_ram_ptr(&s->mem_vram, NULL, "vram", 491 s->vram_size, s->vram); 492 vmstate_register_ram(&s->mem_vram, dev); 493 memory_region_set_log(&s->mem_vram, true, DIRTY_MEMORY_VGA); 494 } 495 496 #define TYPE_G364 "sysbus-g364" 497 #define G364(obj) OBJECT_CHECK(G364SysBusState, (obj), TYPE_G364) 498 499 typedef struct { 500 SysBusDevice parent_obj; 501 502 G364State g364; 503 } G364SysBusState; 504 505 static int g364fb_sysbus_init(SysBusDevice *sbd) 506 { 507 DeviceState *dev = DEVICE(sbd); 508 G364SysBusState *sbs = G364(dev); 509 G364State *s = &sbs->g364; 510 511 g364fb_init(dev, s); 512 sysbus_init_irq(sbd, &s->irq); 513 sysbus_init_mmio(sbd, &s->mem_ctrl); 514 sysbus_init_mmio(sbd, &s->mem_vram); 515 516 return 0; 517 } 518 519 static void g364fb_sysbus_reset(DeviceState *d) 520 { 521 G364SysBusState *s = G364(d); 522 523 g364fb_reset(&s->g364); 524 } 525 526 static Property g364fb_sysbus_properties[] = { 527 DEFINE_PROP_UINT32("vram_size", G364SysBusState, g364.vram_size, 528 8 * 1024 * 1024), 529 DEFINE_PROP_END_OF_LIST(), 530 }; 531 532 static void g364fb_sysbus_class_init(ObjectClass *klass, void *data) 533 { 534 DeviceClass *dc = DEVICE_CLASS(klass); 535 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 536 537 k->init = g364fb_sysbus_init; 538 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 539 dc->desc = "G364 framebuffer"; 540 dc->reset = g364fb_sysbus_reset; 541 dc->vmsd = &vmstate_g364fb; 542 dc->props = g364fb_sysbus_properties; 543 } 544 545 static const TypeInfo g364fb_sysbus_info = { 546 .name = TYPE_G364, 547 .parent = TYPE_SYS_BUS_DEVICE, 548 .instance_size = sizeof(G364SysBusState), 549 .class_init = g364fb_sysbus_class_init, 550 }; 551 552 static void g364fb_register_types(void) 553 { 554 type_register_static(&g364fb_sysbus_info); 555 } 556 557 type_init(g364fb_register_types) 558