1 /* 2 * QEMU G364 framebuffer Emulator. 3 * 4 * Copyright (c) 2007-2011 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/hw.h" 22 #include "qemu/error-report.h" 23 #include "ui/console.h" 24 #include "ui/pixel_ops.h" 25 #include "trace.h" 26 #include "hw/sysbus.h" 27 28 typedef struct G364State { 29 /* hardware */ 30 uint8_t *vram; 31 uint32_t vram_size; 32 qemu_irq irq; 33 MemoryRegion mem_vram; 34 MemoryRegion mem_ctrl; 35 /* registers */ 36 uint8_t color_palette[256][3]; 37 uint8_t cursor_palette[3][3]; 38 uint16_t cursor[512]; 39 uint32_t cursor_position; 40 uint32_t ctla; 41 uint32_t top_of_screen; 42 uint32_t width, height; /* in pixels */ 43 /* display refresh support */ 44 QemuConsole *con; 45 int depth; 46 int blanked; 47 } G364State; 48 49 #define REG_BOOT 0x000000 50 #define REG_DISPLAY 0x000118 51 #define REG_VDISPLAY 0x000150 52 #define REG_CTLA 0x000300 53 #define REG_TOP 0x000400 54 #define REG_CURS_PAL 0x000508 55 #define REG_CURS_POS 0x000638 56 #define REG_CLR_PAL 0x000800 57 #define REG_CURS_PAT 0x001000 58 #define REG_RESET 0x100000 59 60 #define CTLA_FORCE_BLANK 0x00000400 61 #define CTLA_NO_CURSOR 0x00800000 62 63 #define G364_PAGE_SIZE 4096 64 65 static inline int check_dirty(G364State *s, DirtyBitmapSnapshot *snap, ram_addr_t page) 66 { 67 return memory_region_snapshot_get_dirty(&s->mem_vram, snap, page, G364_PAGE_SIZE); 68 } 69 70 static void g364fb_draw_graphic8(G364State *s) 71 { 72 DisplaySurface *surface = qemu_console_surface(s->con); 73 DirtyBitmapSnapshot *snap; 74 int i, w; 75 uint8_t *vram; 76 uint8_t *data_display, *dd; 77 ram_addr_t page; 78 int x, y; 79 int xmin, xmax; 80 int ymin, ymax; 81 int xcursor, ycursor; 82 unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b); 83 84 switch (surface_bits_per_pixel(surface)) { 85 case 8: 86 rgb_to_pixel = rgb_to_pixel8; 87 w = 1; 88 break; 89 case 15: 90 rgb_to_pixel = rgb_to_pixel15; 91 w = 2; 92 break; 93 case 16: 94 rgb_to_pixel = rgb_to_pixel16; 95 w = 2; 96 break; 97 case 32: 98 rgb_to_pixel = rgb_to_pixel32; 99 w = 4; 100 break; 101 default: 102 hw_error("g364: unknown host depth %d", 103 surface_bits_per_pixel(surface)); 104 return; 105 } 106 107 page = 0; 108 109 x = y = 0; 110 xmin = s->width; 111 xmax = 0; 112 ymin = s->height; 113 ymax = 0; 114 115 if (!(s->ctla & CTLA_NO_CURSOR)) { 116 xcursor = s->cursor_position >> 12; 117 ycursor = s->cursor_position & 0xfff; 118 } else { 119 xcursor = ycursor = -65; 120 } 121 122 vram = s->vram + s->top_of_screen; 123 /* XXX: out of range in vram? */ 124 data_display = dd = surface_data(surface); 125 snap = memory_region_snapshot_and_clear_dirty(&s->mem_vram, 0, s->vram_size, 126 DIRTY_MEMORY_VGA); 127 while (y < s->height) { 128 if (check_dirty(s, snap, page)) { 129 if (y < ymin) 130 ymin = ymax = y; 131 if (x < xmin) 132 xmin = x; 133 for (i = 0; i < G364_PAGE_SIZE; i++) { 134 uint8_t index; 135 unsigned int color; 136 if (unlikely((y >= ycursor && y < ycursor + 64) && 137 (x >= xcursor && x < xcursor + 64))) { 138 /* pointer area */ 139 int xdiff = x - xcursor; 140 uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8]; 141 int op = (curs >> ((xdiff & 7) * 2)) & 3; 142 if (likely(op == 0)) { 143 /* transparent */ 144 index = *vram; 145 color = (*rgb_to_pixel)( 146 s->color_palette[index][0], 147 s->color_palette[index][1], 148 s->color_palette[index][2]); 149 } else { 150 /* get cursor color */ 151 index = op - 1; 152 color = (*rgb_to_pixel)( 153 s->cursor_palette[index][0], 154 s->cursor_palette[index][1], 155 s->cursor_palette[index][2]); 156 } 157 } else { 158 /* normal area */ 159 index = *vram; 160 color = (*rgb_to_pixel)( 161 s->color_palette[index][0], 162 s->color_palette[index][1], 163 s->color_palette[index][2]); 164 } 165 memcpy(dd, &color, w); 166 dd += w; 167 x++; 168 vram++; 169 if (x == s->width) { 170 xmax = s->width - 1; 171 y++; 172 if (y == s->height) { 173 ymax = s->height - 1; 174 goto done; 175 } 176 data_display = dd = data_display + surface_stride(surface); 177 xmin = 0; 178 x = 0; 179 } 180 } 181 if (x > xmax) 182 xmax = x; 183 if (y > ymax) 184 ymax = y; 185 } else { 186 int dy; 187 if (xmax || ymax) { 188 dpy_gfx_update(s->con, xmin, ymin, 189 xmax - xmin + 1, ymax - ymin + 1); 190 xmin = s->width; 191 xmax = 0; 192 ymin = s->height; 193 ymax = 0; 194 } 195 x += G364_PAGE_SIZE; 196 dy = x / s->width; 197 x = x % s->width; 198 y += dy; 199 vram += G364_PAGE_SIZE; 200 data_display += dy * surface_stride(surface); 201 dd = data_display + x * w; 202 } 203 page += G364_PAGE_SIZE; 204 } 205 206 done: 207 if (xmax || ymax) { 208 dpy_gfx_update(s->con, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); 209 } 210 } 211 212 static void g364fb_draw_blank(G364State *s) 213 { 214 DisplaySurface *surface = qemu_console_surface(s->con); 215 int i, w; 216 uint8_t *d; 217 218 if (s->blanked) { 219 /* Screen is already blank. No need to redraw it */ 220 return; 221 } 222 223 w = s->width * surface_bytes_per_pixel(surface); 224 d = surface_data(surface); 225 for (i = 0; i < s->height; i++) { 226 memset(d, 0, w); 227 d += surface_stride(surface); 228 } 229 230 dpy_gfx_update(s->con, 0, 0, s->width, s->height); 231 s->blanked = 1; 232 } 233 234 static void g364fb_update_display(void *opaque) 235 { 236 G364State *s = opaque; 237 DisplaySurface *surface = qemu_console_surface(s->con); 238 239 qemu_flush_coalesced_mmio_buffer(); 240 241 if (s->width == 0 || s->height == 0) 242 return; 243 244 if (s->width != surface_width(surface) || 245 s->height != surface_height(surface)) { 246 qemu_console_resize(s->con, s->width, s->height); 247 } 248 249 if (s->ctla & CTLA_FORCE_BLANK) { 250 g364fb_draw_blank(s); 251 } else if (s->depth == 8) { 252 g364fb_draw_graphic8(s); 253 } else { 254 error_report("g364: unknown guest depth %d", s->depth); 255 } 256 257 qemu_irq_raise(s->irq); 258 } 259 260 static inline void g364fb_invalidate_display(void *opaque) 261 { 262 G364State *s = opaque; 263 264 s->blanked = 0; 265 memory_region_set_dirty(&s->mem_vram, 0, s->vram_size); 266 } 267 268 static void g364fb_reset(G364State *s) 269 { 270 qemu_irq_lower(s->irq); 271 272 memset(s->color_palette, 0, sizeof(s->color_palette)); 273 memset(s->cursor_palette, 0, sizeof(s->cursor_palette)); 274 memset(s->cursor, 0, sizeof(s->cursor)); 275 s->cursor_position = 0; 276 s->ctla = 0; 277 s->top_of_screen = 0; 278 s->width = s->height = 0; 279 memset(s->vram, 0, s->vram_size); 280 g364fb_invalidate_display(s); 281 } 282 283 /* called for accesses to io ports */ 284 static uint64_t g364fb_ctrl_read(void *opaque, 285 hwaddr addr, 286 unsigned int size) 287 { 288 G364State *s = opaque; 289 uint32_t val; 290 291 if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { 292 /* cursor pattern */ 293 int idx = (addr - REG_CURS_PAT) >> 3; 294 val = s->cursor[idx]; 295 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { 296 /* cursor palette */ 297 int idx = (addr - REG_CURS_PAL) >> 3; 298 val = ((uint32_t)s->cursor_palette[idx][0] << 16); 299 val |= ((uint32_t)s->cursor_palette[idx][1] << 8); 300 val |= ((uint32_t)s->cursor_palette[idx][2] << 0); 301 } else { 302 switch (addr) { 303 case REG_DISPLAY: 304 val = s->width / 4; 305 break; 306 case REG_VDISPLAY: 307 val = s->height * 2; 308 break; 309 case REG_CTLA: 310 val = s->ctla; 311 break; 312 default: 313 { 314 error_report("g364: invalid read at [" TARGET_FMT_plx "]", 315 addr); 316 val = 0; 317 break; 318 } 319 } 320 } 321 322 trace_g364fb_read(addr, val); 323 324 return val; 325 } 326 327 static void g364fb_update_depth(G364State *s) 328 { 329 static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 }; 330 s->depth = depths[(s->ctla & 0x00700000) >> 20]; 331 } 332 333 static void g364_invalidate_cursor_position(G364State *s) 334 { 335 DisplaySurface *surface = qemu_console_surface(s->con); 336 int ymin, ymax, start, end; 337 338 /* invalidate only near the cursor */ 339 ymin = s->cursor_position & 0xfff; 340 ymax = MIN(s->height, ymin + 64); 341 start = ymin * surface_stride(surface); 342 end = (ymax + 1) * surface_stride(surface); 343 344 memory_region_set_dirty(&s->mem_vram, start, end - start); 345 } 346 347 static void g364fb_ctrl_write(void *opaque, 348 hwaddr addr, 349 uint64_t val, 350 unsigned int size) 351 { 352 G364State *s = opaque; 353 354 trace_g364fb_write(addr, val); 355 356 if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) { 357 /* color palette */ 358 int idx = (addr - REG_CLR_PAL) >> 3; 359 s->color_palette[idx][0] = (val >> 16) & 0xff; 360 s->color_palette[idx][1] = (val >> 8) & 0xff; 361 s->color_palette[idx][2] = val & 0xff; 362 g364fb_invalidate_display(s); 363 } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { 364 /* cursor pattern */ 365 int idx = (addr - REG_CURS_PAT) >> 3; 366 s->cursor[idx] = val; 367 g364fb_invalidate_display(s); 368 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { 369 /* cursor palette */ 370 int idx = (addr - REG_CURS_PAL) >> 3; 371 s->cursor_palette[idx][0] = (val >> 16) & 0xff; 372 s->cursor_palette[idx][1] = (val >> 8) & 0xff; 373 s->cursor_palette[idx][2] = val & 0xff; 374 g364fb_invalidate_display(s); 375 } else { 376 switch (addr) { 377 case REG_BOOT: /* Boot timing */ 378 case 0x00108: /* Line timing: half sync */ 379 case 0x00110: /* Line timing: back porch */ 380 case 0x00120: /* Line timing: short display */ 381 case 0x00128: /* Frame timing: broad pulse */ 382 case 0x00130: /* Frame timing: v sync */ 383 case 0x00138: /* Frame timing: v preequalise */ 384 case 0x00140: /* Frame timing: v postequalise */ 385 case 0x00148: /* Frame timing: v blank */ 386 case 0x00158: /* Line timing: line time */ 387 case 0x00160: /* Frame store: line start */ 388 case 0x00168: /* vram cycle: mem init */ 389 case 0x00170: /* vram cycle: transfer delay */ 390 case 0x00200: /* vram cycle: mask register */ 391 /* ignore */ 392 break; 393 case REG_TOP: 394 s->top_of_screen = val; 395 g364fb_invalidate_display(s); 396 break; 397 case REG_DISPLAY: 398 s->width = val * 4; 399 break; 400 case REG_VDISPLAY: 401 s->height = val / 2; 402 break; 403 case REG_CTLA: 404 s->ctla = val; 405 g364fb_update_depth(s); 406 g364fb_invalidate_display(s); 407 break; 408 case REG_CURS_POS: 409 g364_invalidate_cursor_position(s); 410 s->cursor_position = val; 411 g364_invalidate_cursor_position(s); 412 break; 413 case REG_RESET: 414 g364fb_reset(s); 415 break; 416 default: 417 error_report("g364: invalid write of 0x%" PRIx64 418 " at [" TARGET_FMT_plx "]", val, addr); 419 break; 420 } 421 } 422 qemu_irq_lower(s->irq); 423 } 424 425 static const MemoryRegionOps g364fb_ctrl_ops = { 426 .read = g364fb_ctrl_read, 427 .write = g364fb_ctrl_write, 428 .endianness = DEVICE_LITTLE_ENDIAN, 429 .impl.min_access_size = 4, 430 .impl.max_access_size = 4, 431 }; 432 433 static int g364fb_post_load(void *opaque, int version_id) 434 { 435 G364State *s = opaque; 436 437 /* force refresh */ 438 g364fb_update_depth(s); 439 g364fb_invalidate_display(s); 440 441 return 0; 442 } 443 444 static const VMStateDescription vmstate_g364fb = { 445 .name = "g364fb", 446 .version_id = 1, 447 .minimum_version_id = 1, 448 .post_load = g364fb_post_load, 449 .fields = (VMStateField[]) { 450 VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, vram_size), 451 VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3), 452 VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9), 453 VMSTATE_UINT16_ARRAY(cursor, G364State, 512), 454 VMSTATE_UINT32(cursor_position, G364State), 455 VMSTATE_UINT32(ctla, G364State), 456 VMSTATE_UINT32(top_of_screen, G364State), 457 VMSTATE_UINT32(width, G364State), 458 VMSTATE_UINT32(height, G364State), 459 VMSTATE_END_OF_LIST() 460 } 461 }; 462 463 static const GraphicHwOps g364fb_ops = { 464 .invalidate = g364fb_invalidate_display, 465 .gfx_update = g364fb_update_display, 466 }; 467 468 static void g364fb_init(DeviceState *dev, G364State *s) 469 { 470 s->vram = g_malloc0(s->vram_size); 471 472 s->con = graphic_console_init(dev, 0, &g364fb_ops, s); 473 474 memory_region_init_io(&s->mem_ctrl, NULL, &g364fb_ctrl_ops, s, "ctrl", 0x180000); 475 memory_region_init_ram_ptr(&s->mem_vram, NULL, "vram", 476 s->vram_size, s->vram); 477 vmstate_register_ram(&s->mem_vram, dev); 478 memory_region_set_log(&s->mem_vram, true, DIRTY_MEMORY_VGA); 479 } 480 481 #define TYPE_G364 "sysbus-g364" 482 #define G364(obj) OBJECT_CHECK(G364SysBusState, (obj), TYPE_G364) 483 484 typedef struct { 485 SysBusDevice parent_obj; 486 487 G364State g364; 488 } G364SysBusState; 489 490 static int g364fb_sysbus_init(SysBusDevice *sbd) 491 { 492 DeviceState *dev = DEVICE(sbd); 493 G364SysBusState *sbs = G364(dev); 494 G364State *s = &sbs->g364; 495 496 g364fb_init(dev, s); 497 sysbus_init_irq(sbd, &s->irq); 498 sysbus_init_mmio(sbd, &s->mem_ctrl); 499 sysbus_init_mmio(sbd, &s->mem_vram); 500 501 return 0; 502 } 503 504 static void g364fb_sysbus_reset(DeviceState *d) 505 { 506 G364SysBusState *s = G364(d); 507 508 g364fb_reset(&s->g364); 509 } 510 511 static Property g364fb_sysbus_properties[] = { 512 DEFINE_PROP_UINT32("vram_size", G364SysBusState, g364.vram_size, 513 8 * 1024 * 1024), 514 DEFINE_PROP_END_OF_LIST(), 515 }; 516 517 static void g364fb_sysbus_class_init(ObjectClass *klass, void *data) 518 { 519 DeviceClass *dc = DEVICE_CLASS(klass); 520 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 521 522 k->init = g364fb_sysbus_init; 523 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 524 dc->desc = "G364 framebuffer"; 525 dc->reset = g364fb_sysbus_reset; 526 dc->vmsd = &vmstate_g364fb; 527 dc->props = g364fb_sysbus_properties; 528 } 529 530 static const TypeInfo g364fb_sysbus_info = { 531 .name = TYPE_G364, 532 .parent = TYPE_SYS_BUS_DEVICE, 533 .instance_size = sizeof(G364SysBusState), 534 .class_init = g364fb_sysbus_class_init, 535 }; 536 537 static void g364fb_register_types(void) 538 { 539 type_register_static(&g364fb_sysbus_info); 540 } 541 542 type_init(g364fb_register_types) 543