1 /* 2 * Samsung exynos4210 Display Controller (FIMD) 3 * 4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. 5 * All rights reserved. 6 * Based on LCD controller for Samsung S5PC1xx-based board emulation 7 * by Kirill Batuzov <batuzovk@ispras.ru> 8 * 9 * Contributed by Mitsyanko Igor <i.mitsyanko@samsung.com> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/irq.h" 28 #include "hw/sysbus.h" 29 #include "migration/vmstate.h" 30 #include "ui/console.h" 31 #include "ui/pixel_ops.h" 32 #include "qemu/bswap.h" 33 #include "qemu/module.h" 34 #include "qemu/log.h" 35 #include "qom/object.h" 36 37 /* Debug messages configuration */ 38 #define EXYNOS4210_FIMD_DEBUG 0 39 #define EXYNOS4210_FIMD_MODE_TRACE 0 40 41 #if EXYNOS4210_FIMD_DEBUG == 0 42 #define DPRINT_L1(fmt, args...) do { } while (0) 43 #define DPRINT_L2(fmt, args...) do { } while (0) 44 #elif EXYNOS4210_FIMD_DEBUG == 1 45 #define DPRINT_L1(fmt, args...) \ 46 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0) 47 #define DPRINT_L2(fmt, args...) do { } while (0) 48 #else 49 #define DPRINT_L1(fmt, args...) \ 50 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0) 51 #define DPRINT_L2(fmt, args...) \ 52 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0) 53 #endif 54 55 #if EXYNOS4210_FIMD_MODE_TRACE == 0 56 #define DPRINT_TRACE(fmt, args...) do { } while (0) 57 #else 58 #define DPRINT_TRACE(fmt, args...) \ 59 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0) 60 #endif 61 62 #define NUM_OF_WINDOWS 5 63 #define FIMD_REGS_SIZE 0x4114 64 65 /* Video main control registers */ 66 #define FIMD_VIDCON0 0x0000 67 #define FIMD_VIDCON1 0x0004 68 #define FIMD_VIDCON2 0x0008 69 #define FIMD_VIDCON3 0x000C 70 #define FIMD_VIDCON0_ENVID_F (1 << 0) 71 #define FIMD_VIDCON0_ENVID (1 << 1) 72 #define FIMD_VIDCON0_ENVID_MASK ((1 << 0) | (1 << 1)) 73 #define FIMD_VIDCON1_ROMASK 0x07FFE000 74 75 /* Video time control registers */ 76 #define FIMD_VIDTCON_START 0x10 77 #define FIMD_VIDTCON_END 0x1C 78 #define FIMD_VIDTCON2_SIZE_MASK 0x07FF 79 #define FIMD_VIDTCON2_HOR_SHIFT 0 80 #define FIMD_VIDTCON2_VER_SHIFT 11 81 82 /* Window control registers */ 83 #define FIMD_WINCON_START 0x0020 84 #define FIMD_WINCON_END 0x0030 85 #define FIMD_WINCON_ROMASK 0x82200000 86 #define FIMD_WINCON_ENWIN (1 << 0) 87 #define FIMD_WINCON_BLD_PIX (1 << 6) 88 #define FIMD_WINCON_ALPHA_MUL (1 << 7) 89 #define FIMD_WINCON_ALPHA_SEL (1 << 1) 90 #define FIMD_WINCON_SWAP 0x078000 91 #define FIMD_WINCON_SWAP_SHIFT 15 92 #define FIMD_WINCON_SWAP_WORD 0x1 93 #define FIMD_WINCON_SWAP_HWORD 0x2 94 #define FIMD_WINCON_SWAP_BYTE 0x4 95 #define FIMD_WINCON_SWAP_BITS 0x8 96 #define FIMD_WINCON_BUFSTAT_L (1 << 21) 97 #define FIMD_WINCON_BUFSTAT_H (1 << 31) 98 #define FIMD_WINCON_BUFSTATUS ((1 << 21) | (1 << 31)) 99 #define FIMD_WINCON_BUF0_STAT ((0 << 21) | (0 << 31)) 100 #define FIMD_WINCON_BUF1_STAT ((1 << 21) | (0 << 31)) 101 #define FIMD_WINCON_BUF2_STAT ((0 << 21) | (1U << 31)) 102 #define FIMD_WINCON_BUFSELECT ((1 << 20) | (1 << 30)) 103 #define FIMD_WINCON_BUF0_SEL ((0 << 20) | (0 << 30)) 104 #define FIMD_WINCON_BUF1_SEL ((1 << 20) | (0 << 30)) 105 #define FIMD_WINCON_BUF2_SEL ((0 << 20) | (1 << 30)) 106 #define FIMD_WINCON_BUFMODE (1 << 14) 107 #define IS_PALETTIZED_MODE(w) (w->wincon & 0xC) 108 #define PAL_MODE_WITH_ALPHA(x) ((x) == 7) 109 #define WIN_BPP_MODE(w) ((w->wincon >> 2) & 0xF) 110 #define WIN_BPP_MODE_WITH_ALPHA(w) \ 111 (WIN_BPP_MODE(w) == 0xD || WIN_BPP_MODE(w) == 0xE) 112 113 /* Shadow control register */ 114 #define FIMD_SHADOWCON 0x0034 115 #define FIMD_WINDOW_PROTECTED(s, w) ((s) & (1 << (10 + (w)))) 116 /* Channel mapping control register */ 117 #define FIMD_WINCHMAP 0x003C 118 119 /* Window position control registers */ 120 #define FIMD_VIDOSD_START 0x0040 121 #define FIMD_VIDOSD_END 0x0088 122 #define FIMD_VIDOSD_COORD_MASK 0x07FF 123 #define FIMD_VIDOSD_HOR_SHIFT 11 124 #define FIMD_VIDOSD_VER_SHIFT 0 125 #define FIMD_VIDOSD_ALPHA_AEN0 0xFFF000 126 #define FIMD_VIDOSD_AEN0_SHIFT 12 127 #define FIMD_VIDOSD_ALPHA_AEN1 0x000FFF 128 129 /* Frame buffer address registers */ 130 #define FIMD_VIDWADD0_START 0x00A0 131 #define FIMD_VIDWADD0_END 0x00C4 132 #define FIMD_VIDWADD0_END 0x00C4 133 #define FIMD_VIDWADD1_START 0x00D0 134 #define FIMD_VIDWADD1_END 0x00F4 135 #define FIMD_VIDWADD2_START 0x0100 136 #define FIMD_VIDWADD2_END 0x0110 137 #define FIMD_VIDWADD2_PAGEWIDTH 0x1FFF 138 #define FIMD_VIDWADD2_OFFSIZE 0x1FFF 139 #define FIMD_VIDWADD2_OFFSIZE_SHIFT 13 140 #define FIMD_VIDW0ADD0_B2 0x20A0 141 #define FIMD_VIDW4ADD0_B2 0x20C0 142 143 /* Video interrupt control registers */ 144 #define FIMD_VIDINTCON0 0x130 145 #define FIMD_VIDINTCON1 0x134 146 147 /* Window color key registers */ 148 #define FIMD_WKEYCON_START 0x140 149 #define FIMD_WKEYCON_END 0x15C 150 #define FIMD_WKEYCON0_COMPKEY 0x00FFFFFF 151 #define FIMD_WKEYCON0_CTL_SHIFT 24 152 #define FIMD_WKEYCON0_DIRCON (1 << 24) 153 #define FIMD_WKEYCON0_KEYEN (1 << 25) 154 #define FIMD_WKEYCON0_KEYBLEN (1 << 26) 155 /* Window color key alpha control register */ 156 #define FIMD_WKEYALPHA_START 0x160 157 #define FIMD_WKEYALPHA_END 0x16C 158 159 /* Dithering control register */ 160 #define FIMD_DITHMODE 0x170 161 162 /* Window alpha control registers */ 163 #define FIMD_VIDALPHA_ALPHA_LOWER 0x000F0F0F 164 #define FIMD_VIDALPHA_ALPHA_UPPER 0x00F0F0F0 165 #define FIMD_VIDWALPHA_START 0x21C 166 #define FIMD_VIDWALPHA_END 0x240 167 168 /* Window color map registers */ 169 #define FIMD_WINMAP_START 0x180 170 #define FIMD_WINMAP_END 0x190 171 #define FIMD_WINMAP_EN (1 << 24) 172 #define FIMD_WINMAP_COLOR_MASK 0x00FFFFFF 173 174 /* Window palette control registers */ 175 #define FIMD_WPALCON_HIGH 0x019C 176 #define FIMD_WPALCON_LOW 0x01A0 177 #define FIMD_WPALCON_UPDATEEN (1 << 9) 178 #define FIMD_WPAL_W0PAL_L 0x07 179 #define FIMD_WPAL_W0PAL_L_SHT 0 180 #define FIMD_WPAL_W1PAL_L 0x07 181 #define FIMD_WPAL_W1PAL_L_SHT 3 182 #define FIMD_WPAL_W2PAL_L 0x01 183 #define FIMD_WPAL_W2PAL_L_SHT 6 184 #define FIMD_WPAL_W2PAL_H 0x06 185 #define FIMD_WPAL_W2PAL_H_SHT 8 186 #define FIMD_WPAL_W3PAL_L 0x01 187 #define FIMD_WPAL_W3PAL_L_SHT 7 188 #define FIMD_WPAL_W3PAL_H 0x06 189 #define FIMD_WPAL_W3PAL_H_SHT 12 190 #define FIMD_WPAL_W4PAL_L 0x01 191 #define FIMD_WPAL_W4PAL_L_SHT 8 192 #define FIMD_WPAL_W4PAL_H 0x06 193 #define FIMD_WPAL_W4PAL_H_SHT 16 194 195 /* Trigger control registers */ 196 #define FIMD_TRIGCON 0x01A4 197 #define FIMD_TRIGCON_ROMASK 0x00000004 198 199 /* LCD I80 Interface Control */ 200 #define FIMD_I80IFCON_START 0x01B0 201 #define FIMD_I80IFCON_END 0x01BC 202 /* Color gain control register */ 203 #define FIMD_COLORGAINCON 0x01C0 204 /* LCD i80 Interface Command Control */ 205 #define FIMD_LDI_CMDCON0 0x01D0 206 #define FIMD_LDI_CMDCON1 0x01D4 207 /* I80 System Interface Manual Command Control */ 208 #define FIMD_SIFCCON0 0x01E0 209 #define FIMD_SIFCCON2 0x01E8 210 211 /* Hue Control Registers */ 212 #define FIMD_HUECOEFCR_START 0x01EC 213 #define FIMD_HUECOEFCR_END 0x01F4 214 #define FIMD_HUECOEFCB_START 0x01FC 215 #define FIMD_HUECOEFCB_END 0x0208 216 #define FIMD_HUEOFFSET 0x020C 217 218 /* Video interrupt control registers */ 219 #define FIMD_VIDINT_INTFIFOPEND (1 << 0) 220 #define FIMD_VIDINT_INTFRMPEND (1 << 1) 221 #define FIMD_VIDINT_INTI80PEND (1 << 2) 222 #define FIMD_VIDINT_INTEN (1 << 0) 223 #define FIMD_VIDINT_INTFIFOEN (1 << 1) 224 #define FIMD_VIDINT_INTFRMEN (1 << 12) 225 #define FIMD_VIDINT_I80IFDONE (1 << 17) 226 227 /* Window blend equation control registers */ 228 #define FIMD_BLENDEQ_START 0x0244 229 #define FIMD_BLENDEQ_END 0x0250 230 #define FIMD_BLENDCON 0x0260 231 #define FIMD_ALPHA_8BIT (1 << 0) 232 #define FIMD_BLENDEQ_COEF_MASK 0xF 233 234 /* Window RTQOS Control Registers */ 235 #define FIMD_WRTQOSCON_START 0x0264 236 #define FIMD_WRTQOSCON_END 0x0274 237 238 /* LCD I80 Interface Command */ 239 #define FIMD_I80IFCMD_START 0x0280 240 #define FIMD_I80IFCMD_END 0x02AC 241 242 /* Shadow windows control registers */ 243 #define FIMD_SHD_ADD0_START 0x40A0 244 #define FIMD_SHD_ADD0_END 0x40C0 245 #define FIMD_SHD_ADD1_START 0x40D0 246 #define FIMD_SHD_ADD1_END 0x40F0 247 #define FIMD_SHD_ADD2_START 0x4100 248 #define FIMD_SHD_ADD2_END 0x4110 249 250 /* Palette memory */ 251 #define FIMD_PAL_MEM_START 0x2400 252 #define FIMD_PAL_MEM_END 0x37FC 253 /* Palette memory aliases for windows 0 and 1 */ 254 #define FIMD_PALMEM_AL_START 0x0400 255 #define FIMD_PALMEM_AL_END 0x0BFC 256 257 typedef struct { 258 uint8_t r, g, b; 259 /* D[31..24]dummy, D[23..16]rAlpha, D[15..8]gAlpha, D[7..0]bAlpha */ 260 uint32_t a; 261 } rgba; 262 #define RGBA_SIZE 7 263 264 typedef void pixel_to_rgb_func(uint32_t pixel, rgba *p); 265 typedef struct Exynos4210fimdWindow Exynos4210fimdWindow; 266 267 struct Exynos4210fimdWindow { 268 uint32_t wincon; /* Window control register */ 269 uint32_t buf_start[3]; /* Start address for video frame buffer */ 270 uint32_t buf_end[3]; /* End address for video frame buffer */ 271 uint32_t keycon[2]; /* Window color key registers */ 272 uint32_t keyalpha; /* Color key alpha control register */ 273 uint32_t winmap; /* Window color map register */ 274 uint32_t blendeq; /* Window blending equation control register */ 275 uint32_t rtqoscon; /* Window RTQOS Control Registers */ 276 uint32_t palette[256]; /* Palette RAM */ 277 uint32_t shadow_buf_start; /* Start address of shadow frame buffer */ 278 uint32_t shadow_buf_end; /* End address of shadow frame buffer */ 279 uint32_t shadow_buf_size; /* Virtual shadow screen width */ 280 281 pixel_to_rgb_func *pixel_to_rgb; 282 void (*draw_line)(Exynos4210fimdWindow *w, uint8_t *src, uint8_t *dst, 283 bool blend); 284 uint32_t (*get_alpha)(Exynos4210fimdWindow *w, uint32_t pix_a); 285 uint16_t lefttop_x, lefttop_y; /* VIDOSD0 register */ 286 uint16_t rightbot_x, rightbot_y; /* VIDOSD1 register */ 287 uint32_t osdsize; /* VIDOSD2&3 register */ 288 uint32_t alpha_val[2]; /* VIDOSD2&3, VIDWALPHA registers */ 289 uint16_t virtpage_width; /* VIDWADD2 register */ 290 uint16_t virtpage_offsize; /* VIDWADD2 register */ 291 MemoryRegionSection mem_section; /* RAM fragment containing framebuffer */ 292 uint8_t *host_fb_addr; /* Host pointer to window's framebuffer */ 293 hwaddr fb_len; /* Framebuffer length */ 294 }; 295 296 #define TYPE_EXYNOS4210_FIMD "exynos4210.fimd" 297 typedef struct Exynos4210fimdState Exynos4210fimdState; 298 DECLARE_INSTANCE_CHECKER(Exynos4210fimdState, EXYNOS4210_FIMD, 299 TYPE_EXYNOS4210_FIMD) 300 301 struct Exynos4210fimdState { 302 SysBusDevice parent_obj; 303 304 MemoryRegion iomem; 305 QemuConsole *console; 306 qemu_irq irq[3]; 307 308 uint32_t vidcon[4]; /* Video main control registers 0-3 */ 309 uint32_t vidtcon[4]; /* Video time control registers 0-3 */ 310 uint32_t shadowcon; /* Window shadow control register */ 311 uint32_t winchmap; /* Channel mapping control register */ 312 uint32_t vidintcon[2]; /* Video interrupt control registers */ 313 uint32_t dithmode; /* Dithering control register */ 314 uint32_t wpalcon[2]; /* Window palette control registers */ 315 uint32_t trigcon; /* Trigger control register */ 316 uint32_t i80ifcon[4]; /* I80 interface control registers */ 317 uint32_t colorgaincon; /* Color gain control register */ 318 uint32_t ldi_cmdcon[2]; /* LCD I80 interface command control */ 319 uint32_t sifccon[3]; /* I80 System Interface Manual Command Control */ 320 uint32_t huecoef_cr[4]; /* Hue control registers */ 321 uint32_t huecoef_cb[4]; /* Hue control registers */ 322 uint32_t hueoffset; /* Hue offset control register */ 323 uint32_t blendcon; /* Blending control register */ 324 uint32_t i80ifcmd[12]; /* LCD I80 Interface Command */ 325 326 Exynos4210fimdWindow window[5]; /* Window-specific registers */ 327 uint8_t *ifb; /* Internal frame buffer */ 328 bool invalidate; /* Image needs to be redrawn */ 329 bool enabled; /* Display controller is enabled */ 330 }; 331 332 /* Perform byte/halfword/word swap of data according to WINCON */ 333 static inline void fimd_swap_data(unsigned int swap_ctl, uint64_t *data) 334 { 335 int i; 336 uint64_t res; 337 uint64_t x = *data; 338 339 if (swap_ctl & FIMD_WINCON_SWAP_BITS) { 340 res = 0; 341 for (i = 0; i < 64; i++) { 342 if (x & (1ULL << (63 - i))) { 343 res |= (1ULL << i); 344 } 345 } 346 x = res; 347 } 348 349 if (swap_ctl & FIMD_WINCON_SWAP_BYTE) { 350 x = bswap64(x); 351 } 352 353 if (swap_ctl & FIMD_WINCON_SWAP_HWORD) { 354 x = ((x & 0x000000000000FFFFULL) << 48) | 355 ((x & 0x00000000FFFF0000ULL) << 16) | 356 ((x & 0x0000FFFF00000000ULL) >> 16) | 357 ((x & 0xFFFF000000000000ULL) >> 48); 358 } 359 360 if (swap_ctl & FIMD_WINCON_SWAP_WORD) { 361 x = ((x & 0x00000000FFFFFFFFULL) << 32) | 362 ((x & 0xFFFFFFFF00000000ULL) >> 32); 363 } 364 365 *data = x; 366 } 367 368 /* Conversion routines of Pixel data from frame buffer area to internal RGBA 369 * pixel representation. 370 * Every color component internally represented as 8-bit value. If original 371 * data has less than 8 bit for component, data is extended to 8 bit. For 372 * example, if blue component has only two possible values 0 and 1 it will be 373 * extended to 0 and 0xFF */ 374 375 /* One bit for alpha representation */ 376 #define DEF_PIXEL_TO_RGB_A1(N, R, G, B) \ 377 static void N(uint32_t pixel, rgba *p) \ 378 { \ 379 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \ 380 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \ 381 pixel >>= (B); \ 382 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \ 383 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \ 384 pixel >>= (G); \ 385 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \ 386 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \ 387 pixel >>= (R); \ 388 p->a = (pixel & 0x1); \ 389 } 390 391 DEF_PIXEL_TO_RGB_A1(pixel_a444_to_rgb, 4, 4, 4) 392 DEF_PIXEL_TO_RGB_A1(pixel_a555_to_rgb, 5, 5, 5) 393 DEF_PIXEL_TO_RGB_A1(pixel_a666_to_rgb, 6, 6, 6) 394 DEF_PIXEL_TO_RGB_A1(pixel_a665_to_rgb, 6, 6, 5) 395 DEF_PIXEL_TO_RGB_A1(pixel_a888_to_rgb, 8, 8, 8) 396 DEF_PIXEL_TO_RGB_A1(pixel_a887_to_rgb, 8, 8, 7) 397 398 /* Alpha component is always zero */ 399 #define DEF_PIXEL_TO_RGB_A0(N, R, G, B) \ 400 static void N(uint32_t pixel, rgba *p) \ 401 { \ 402 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \ 403 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \ 404 pixel >>= (B); \ 405 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \ 406 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \ 407 pixel >>= (G); \ 408 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \ 409 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \ 410 p->a = 0x0; \ 411 } 412 413 DEF_PIXEL_TO_RGB_A0(pixel_565_to_rgb, 5, 6, 5) 414 DEF_PIXEL_TO_RGB_A0(pixel_555_to_rgb, 5, 5, 5) 415 DEF_PIXEL_TO_RGB_A0(pixel_666_to_rgb, 6, 6, 6) 416 DEF_PIXEL_TO_RGB_A0(pixel_888_to_rgb, 8, 8, 8) 417 418 /* Alpha component has some meaningful value */ 419 #define DEF_PIXEL_TO_RGB_A(N, R, G, B, A) \ 420 static void N(uint32_t pixel, rgba *p) \ 421 { \ 422 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \ 423 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \ 424 pixel >>= (B); \ 425 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \ 426 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \ 427 pixel >>= (G); \ 428 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \ 429 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \ 430 pixel >>= (R); \ 431 p->a = (pixel & ((1 << (A)) - 1)) << (8 - (A)) | \ 432 ((pixel >> (2 * (A) - 8)) & ((1 << (8 - (A))) - 1)); \ 433 p->a = p->a | (p->a << 8) | (p->a << 16); \ 434 } 435 436 DEF_PIXEL_TO_RGB_A(pixel_4444_to_rgb, 4, 4, 4, 4) 437 DEF_PIXEL_TO_RGB_A(pixel_8888_to_rgb, 8, 8, 8, 8) 438 439 /* Lookup table to extent 2-bit color component to 8 bit */ 440 static const uint8_t pixel_lutable_2b[4] = { 441 0x0, 0x55, 0xAA, 0xFF 442 }; 443 /* Lookup table to extent 3-bit color component to 8 bit */ 444 static const uint8_t pixel_lutable_3b[8] = { 445 0x0, 0x24, 0x49, 0x6D, 0x92, 0xB6, 0xDB, 0xFF 446 }; 447 /* Special case for a232 bpp mode */ 448 static void pixel_a232_to_rgb(uint32_t pixel, rgba *p) 449 { 450 p->b = pixel_lutable_2b[(pixel & 0x3)]; 451 pixel >>= 2; 452 p->g = pixel_lutable_3b[(pixel & 0x7)]; 453 pixel >>= 3; 454 p->r = pixel_lutable_2b[(pixel & 0x3)]; 455 pixel >>= 2; 456 p->a = (pixel & 0x1); 457 } 458 459 /* Special case for (5+1, 5+1, 5+1) mode. Data bit 15 is common LSB 460 * for all three color components */ 461 static void pixel_1555_to_rgb(uint32_t pixel, rgba *p) 462 { 463 uint8_t comm = (pixel >> 15) & 1; 464 p->b = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3); 465 pixel >>= 5; 466 p->g = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3); 467 pixel >>= 5; 468 p->r = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3); 469 p->a = 0x0; 470 } 471 472 /* Put/get pixel to/from internal LCD Controller framebuffer */ 473 474 static int put_pixel_ifb(const rgba p, uint8_t *d) 475 { 476 *(uint8_t *)d++ = p.r; 477 *(uint8_t *)d++ = p.g; 478 *(uint8_t *)d++ = p.b; 479 *(uint32_t *)d = p.a; 480 return RGBA_SIZE; 481 } 482 483 static int get_pixel_ifb(const uint8_t *s, rgba *p) 484 { 485 p->r = *(uint8_t *)s++; 486 p->g = *(uint8_t *)s++; 487 p->b = *(uint8_t *)s++; 488 p->a = (*(uint32_t *)s) & 0x00FFFFFF; 489 return RGBA_SIZE; 490 } 491 492 static pixel_to_rgb_func *palette_data_format[8] = { 493 [0] = pixel_565_to_rgb, 494 [1] = pixel_a555_to_rgb, 495 [2] = pixel_666_to_rgb, 496 [3] = pixel_a665_to_rgb, 497 [4] = pixel_a666_to_rgb, 498 [5] = pixel_888_to_rgb, 499 [6] = pixel_a888_to_rgb, 500 [7] = pixel_8888_to_rgb 501 }; 502 503 /* Returns Index in palette data formats table for given window number WINDOW */ 504 static uint32_t 505 exynos4210_fimd_palette_format(Exynos4210fimdState *s, int window) 506 { 507 uint32_t ret; 508 509 switch (window) { 510 case 0: 511 ret = (s->wpalcon[1] >> FIMD_WPAL_W0PAL_L_SHT) & FIMD_WPAL_W0PAL_L; 512 if (ret != 7) { 513 ret = 6 - ret; 514 } 515 break; 516 case 1: 517 ret = (s->wpalcon[1] >> FIMD_WPAL_W1PAL_L_SHT) & FIMD_WPAL_W1PAL_L; 518 if (ret != 7) { 519 ret = 6 - ret; 520 } 521 break; 522 case 2: 523 ret = ((s->wpalcon[0] >> FIMD_WPAL_W2PAL_H_SHT) & FIMD_WPAL_W2PAL_H) | 524 ((s->wpalcon[1] >> FIMD_WPAL_W2PAL_L_SHT) & FIMD_WPAL_W2PAL_L); 525 break; 526 case 3: 527 ret = ((s->wpalcon[0] >> FIMD_WPAL_W3PAL_H_SHT) & FIMD_WPAL_W3PAL_H) | 528 ((s->wpalcon[1] >> FIMD_WPAL_W3PAL_L_SHT) & FIMD_WPAL_W3PAL_L); 529 break; 530 case 4: 531 ret = ((s->wpalcon[0] >> FIMD_WPAL_W4PAL_H_SHT) & FIMD_WPAL_W4PAL_H) | 532 ((s->wpalcon[1] >> FIMD_WPAL_W4PAL_L_SHT) & FIMD_WPAL_W4PAL_L); 533 break; 534 default: 535 hw_error("exynos4210.fimd: incorrect window number %d\n", window); 536 ret = 0; 537 break; 538 } 539 return ret; 540 } 541 542 #define FIMD_1_MINUS_COLOR(x) \ 543 ((0xFF - ((x) & 0xFF)) | (0xFF00 - ((x) & 0xFF00)) | \ 544 (0xFF0000 - ((x) & 0xFF0000))) 545 #define EXTEND_LOWER_HALFBYTE(x) (((x) & 0xF0F0F) | (((x) << 4) & 0xF0F0F0)) 546 #define EXTEND_UPPER_HALFBYTE(x) (((x) & 0xF0F0F0) | (((x) >> 4) & 0xF0F0F)) 547 548 /* Multiply three lower bytes of two 32-bit words with each other. 549 * Each byte with values 0-255 is considered as a number with possible values 550 * in a range [0 - 1] */ 551 static inline uint32_t fimd_mult_each_byte(uint32_t a, uint32_t b) 552 { 553 uint32_t tmp; 554 uint32_t ret; 555 556 ret = ((tmp = (((a & 0xFF) * (b & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF : tmp; 557 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF)) / 0xFF)) > 0xFF) ? 558 0xFF00 : tmp << 8; 559 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF)) / 0xFF)) > 0xFF) ? 560 0xFF0000 : tmp << 16; 561 return ret; 562 } 563 564 /* For each corresponding bytes of two 32-bit words: (a*b + c*d) 565 * Byte values 0-255 are mapped to a range [0 .. 1] */ 566 static inline uint32_t 567 fimd_mult_and_sum_each_byte(uint32_t a, uint32_t b, uint32_t c, uint32_t d) 568 { 569 uint32_t tmp; 570 uint32_t ret; 571 572 ret = ((tmp = (((a & 0xFF) * (b & 0xFF) + (c & 0xFF) * (d & 0xFF)) / 0xFF)) 573 > 0xFF) ? 0xFF : tmp; 574 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF) + ((c >> 8) & 0xFF) * 575 ((d >> 8) & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF00 : tmp << 8; 576 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF) + 577 ((c >> 16) & 0xFF) * ((d >> 16) & 0xFF)) / 0xFF)) > 0xFF) ? 578 0xFF0000 : tmp << 16; 579 return ret; 580 } 581 582 /* These routines cover all possible sources of window's transparent factor 583 * used in blending equation. Choice of routine is affected by WPALCON 584 * registers, BLENDCON register and window's WINCON register */ 585 586 static uint32_t fimd_get_alpha_pix(Exynos4210fimdWindow *w, uint32_t pix_a) 587 { 588 return pix_a; 589 } 590 591 static uint32_t 592 fimd_get_alpha_pix_extlow(Exynos4210fimdWindow *w, uint32_t pix_a) 593 { 594 return EXTEND_LOWER_HALFBYTE(pix_a); 595 } 596 597 static uint32_t 598 fimd_get_alpha_pix_exthigh(Exynos4210fimdWindow *w, uint32_t pix_a) 599 { 600 return EXTEND_UPPER_HALFBYTE(pix_a); 601 } 602 603 static uint32_t fimd_get_alpha_mult(Exynos4210fimdWindow *w, uint32_t pix_a) 604 { 605 return fimd_mult_each_byte(pix_a, w->alpha_val[0]); 606 } 607 608 static uint32_t fimd_get_alpha_mult_ext(Exynos4210fimdWindow *w, uint32_t pix_a) 609 { 610 return fimd_mult_each_byte(EXTEND_LOWER_HALFBYTE(pix_a), 611 EXTEND_UPPER_HALFBYTE(w->alpha_val[0])); 612 } 613 614 static uint32_t fimd_get_alpha_aen(Exynos4210fimdWindow *w, uint32_t pix_a) 615 { 616 return w->alpha_val[pix_a]; 617 } 618 619 static uint32_t fimd_get_alpha_aen_ext(Exynos4210fimdWindow *w, uint32_t pix_a) 620 { 621 return EXTEND_UPPER_HALFBYTE(w->alpha_val[pix_a]); 622 } 623 624 static uint32_t fimd_get_alpha_sel(Exynos4210fimdWindow *w, uint32_t pix_a) 625 { 626 return w->alpha_val[(w->wincon & FIMD_WINCON_ALPHA_SEL) ? 1 : 0]; 627 } 628 629 static uint32_t fimd_get_alpha_sel_ext(Exynos4210fimdWindow *w, uint32_t pix_a) 630 { 631 return EXTEND_UPPER_HALFBYTE(w->alpha_val[(w->wincon & 632 FIMD_WINCON_ALPHA_SEL) ? 1 : 0]); 633 } 634 635 /* Updates currently active alpha value get function for specified window */ 636 static void fimd_update_get_alpha(Exynos4210fimdState *s, int win) 637 { 638 Exynos4210fimdWindow *w = &s->window[win]; 639 const bool alpha_is_8bit = s->blendcon & FIMD_ALPHA_8BIT; 640 641 if (w->wincon & FIMD_WINCON_BLD_PIX) { 642 if ((w->wincon & FIMD_WINCON_ALPHA_SEL) && WIN_BPP_MODE_WITH_ALPHA(w)) { 643 /* In this case, alpha component contains meaningful value */ 644 if (w->wincon & FIMD_WINCON_ALPHA_MUL) { 645 w->get_alpha = alpha_is_8bit ? 646 fimd_get_alpha_mult : fimd_get_alpha_mult_ext; 647 } else { 648 w->get_alpha = alpha_is_8bit ? 649 fimd_get_alpha_pix : fimd_get_alpha_pix_extlow; 650 } 651 } else { 652 if (IS_PALETTIZED_MODE(w) && 653 PAL_MODE_WITH_ALPHA(exynos4210_fimd_palette_format(s, win))) { 654 /* Alpha component has 8-bit numeric value */ 655 w->get_alpha = alpha_is_8bit ? 656 fimd_get_alpha_pix : fimd_get_alpha_pix_exthigh; 657 } else { 658 /* Alpha has only two possible values (AEN) */ 659 w->get_alpha = alpha_is_8bit ? 660 fimd_get_alpha_aen : fimd_get_alpha_aen_ext; 661 } 662 } 663 } else { 664 w->get_alpha = alpha_is_8bit ? fimd_get_alpha_sel : 665 fimd_get_alpha_sel_ext; 666 } 667 } 668 669 /* Blends current window's (w) pixel (foreground pixel *ret) with background 670 * window (w_blend) pixel p_bg according to formula: 671 * NEW_COLOR = a_coef x FG_PIXEL_COLOR + b_coef x BG_PIXEL_COLOR 672 * NEW_ALPHA = p_coef x FG_ALPHA + q_coef x BG_ALPHA 673 */ 674 static void 675 exynos4210_fimd_blend_pixel(Exynos4210fimdWindow *w, rgba p_bg, rgba *ret) 676 { 677 rgba p_fg = *ret; 678 uint32_t bg_color = ((p_bg.r & 0xFF) << 16) | ((p_bg.g & 0xFF) << 8) | 679 (p_bg.b & 0xFF); 680 uint32_t fg_color = ((p_fg.r & 0xFF) << 16) | ((p_fg.g & 0xFF) << 8) | 681 (p_fg.b & 0xFF); 682 uint32_t alpha_fg = p_fg.a; 683 int i; 684 /* It is possible that blending equation parameters a and b do not 685 * depend on window BLENEQ register. Account for this with first_coef */ 686 enum { A_COEF = 0, B_COEF = 1, P_COEF = 2, Q_COEF = 3, COEF_NUM = 4}; 687 uint32_t first_coef = A_COEF; 688 uint32_t blend_param[COEF_NUM]; 689 690 if (w->keycon[0] & FIMD_WKEYCON0_KEYEN) { 691 uint32_t colorkey = (w->keycon[1] & 692 ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) & FIMD_WKEYCON0_COMPKEY; 693 694 if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) && 695 (bg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) { 696 /* Foreground pixel is displayed */ 697 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) { 698 alpha_fg = w->keyalpha; 699 blend_param[A_COEF] = alpha_fg; 700 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg); 701 } else { 702 alpha_fg = 0; 703 blend_param[A_COEF] = 0xFFFFFF; 704 blend_param[B_COEF] = 0x0; 705 } 706 first_coef = P_COEF; 707 } else if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) == 0 && 708 (fg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) { 709 /* Background pixel is displayed */ 710 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) { 711 alpha_fg = w->keyalpha; 712 blend_param[A_COEF] = alpha_fg; 713 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg); 714 } else { 715 alpha_fg = 0; 716 blend_param[A_COEF] = 0x0; 717 blend_param[B_COEF] = 0xFFFFFF; 718 } 719 first_coef = P_COEF; 720 } 721 } 722 723 for (i = first_coef; i < COEF_NUM; i++) { 724 switch ((w->blendeq >> i * 6) & FIMD_BLENDEQ_COEF_MASK) { 725 case 0: 726 blend_param[i] = 0; 727 break; 728 case 1: 729 blend_param[i] = 0xFFFFFF; 730 break; 731 case 2: 732 blend_param[i] = alpha_fg; 733 break; 734 case 3: 735 blend_param[i] = FIMD_1_MINUS_COLOR(alpha_fg); 736 break; 737 case 4: 738 blend_param[i] = p_bg.a; 739 break; 740 case 5: 741 blend_param[i] = FIMD_1_MINUS_COLOR(p_bg.a); 742 break; 743 case 6: 744 blend_param[i] = w->alpha_val[0]; 745 break; 746 case 10: 747 blend_param[i] = fg_color; 748 break; 749 case 11: 750 blend_param[i] = FIMD_1_MINUS_COLOR(fg_color); 751 break; 752 case 12: 753 blend_param[i] = bg_color; 754 break; 755 case 13: 756 blend_param[i] = FIMD_1_MINUS_COLOR(bg_color); 757 break; 758 default: 759 hw_error("exynos4210.fimd: blend equation coef illegal value\n"); 760 break; 761 } 762 } 763 764 fg_color = fimd_mult_and_sum_each_byte(bg_color, blend_param[B_COEF], 765 fg_color, blend_param[A_COEF]); 766 ret->b = fg_color & 0xFF; 767 fg_color >>= 8; 768 ret->g = fg_color & 0xFF; 769 fg_color >>= 8; 770 ret->r = fg_color & 0xFF; 771 ret->a = fimd_mult_and_sum_each_byte(alpha_fg, blend_param[P_COEF], 772 p_bg.a, blend_param[Q_COEF]); 773 } 774 775 /* These routines read data from video frame buffer in system RAM, convert 776 * this data to display controller internal representation, if necessary, 777 * perform pixel blending with data, currently presented in internal buffer. 778 * Result is stored in display controller internal frame buffer. */ 779 780 /* Draw line with index in palette table in RAM frame buffer data */ 781 #define DEF_DRAW_LINE_PALETTE(N) \ 782 static void glue(draw_line_palette_, N)(Exynos4210fimdWindow *w, uint8_t *src, \ 783 uint8_t *dst, bool blend) \ 784 { \ 785 int width = w->rightbot_x - w->lefttop_x + 1; \ 786 uint8_t *ifb = dst; \ 787 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \ 788 uint64_t data; \ 789 rgba p, p_old; \ 790 int i; \ 791 do { \ 792 memcpy(&data, src, sizeof(data)); \ 793 src += 8; \ 794 fimd_swap_data(swap, &data); \ 795 for (i = (64 / (N) - 1); i >= 0; i--) { \ 796 w->pixel_to_rgb(w->palette[(data >> ((N) * i)) & \ 797 ((1ULL << (N)) - 1)], &p); \ 798 p.a = w->get_alpha(w, p.a); \ 799 if (blend) { \ 800 ifb += get_pixel_ifb(ifb, &p_old); \ 801 exynos4210_fimd_blend_pixel(w, p_old, &p); \ 802 } \ 803 dst += put_pixel_ifb(p, dst); \ 804 } \ 805 width -= (64 / (N)); \ 806 } while (width > 0); \ 807 } 808 809 /* Draw line with direct color value in RAM frame buffer data */ 810 #define DEF_DRAW_LINE_NOPALETTE(N) \ 811 static void glue(draw_line_, N)(Exynos4210fimdWindow *w, uint8_t *src, \ 812 uint8_t *dst, bool blend) \ 813 { \ 814 int width = w->rightbot_x - w->lefttop_x + 1; \ 815 uint8_t *ifb = dst; \ 816 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \ 817 uint64_t data; \ 818 rgba p, p_old; \ 819 int i; \ 820 do { \ 821 memcpy(&data, src, sizeof(data)); \ 822 src += 8; \ 823 fimd_swap_data(swap, &data); \ 824 for (i = (64 / (N) - 1); i >= 0; i--) { \ 825 w->pixel_to_rgb((data >> ((N) * i)) & ((1ULL << (N)) - 1), &p); \ 826 p.a = w->get_alpha(w, p.a); \ 827 if (blend) { \ 828 ifb += get_pixel_ifb(ifb, &p_old); \ 829 exynos4210_fimd_blend_pixel(w, p_old, &p); \ 830 } \ 831 dst += put_pixel_ifb(p, dst); \ 832 } \ 833 width -= (64 / (N)); \ 834 } while (width > 0); \ 835 } 836 837 DEF_DRAW_LINE_PALETTE(1) 838 DEF_DRAW_LINE_PALETTE(2) 839 DEF_DRAW_LINE_PALETTE(4) 840 DEF_DRAW_LINE_PALETTE(8) 841 DEF_DRAW_LINE_NOPALETTE(8) /* 8bpp mode has palette and non-palette versions */ 842 DEF_DRAW_LINE_NOPALETTE(16) 843 DEF_DRAW_LINE_NOPALETTE(32) 844 845 /* Special draw line routine for window color map case */ 846 static void draw_line_mapcolor(Exynos4210fimdWindow *w, uint8_t *src, 847 uint8_t *dst, bool blend) 848 { 849 rgba p, p_old; 850 uint8_t *ifb = dst; 851 int width = w->rightbot_x - w->lefttop_x + 1; 852 uint32_t map_color = w->winmap & FIMD_WINMAP_COLOR_MASK; 853 854 do { 855 pixel_888_to_rgb(map_color, &p); 856 p.a = w->get_alpha(w, p.a); 857 if (blend) { 858 ifb += get_pixel_ifb(ifb, &p_old); 859 exynos4210_fimd_blend_pixel(w, p_old, &p); 860 } 861 dst += put_pixel_ifb(p, dst); 862 } while (--width); 863 } 864 865 /* Write RGB to QEMU's GraphicConsole framebuffer */ 866 867 static int put_to_qemufb_pixel8(const rgba p, uint8_t *d) 868 { 869 uint32_t pixel = rgb_to_pixel8(p.r, p.g, p.b); 870 *(uint8_t *)d = pixel; 871 return 1; 872 } 873 874 static int put_to_qemufb_pixel15(const rgba p, uint8_t *d) 875 { 876 uint32_t pixel = rgb_to_pixel15(p.r, p.g, p.b); 877 *(uint16_t *)d = pixel; 878 return 2; 879 } 880 881 static int put_to_qemufb_pixel16(const rgba p, uint8_t *d) 882 { 883 uint32_t pixel = rgb_to_pixel16(p.r, p.g, p.b); 884 *(uint16_t *)d = pixel; 885 return 2; 886 } 887 888 static int put_to_qemufb_pixel24(const rgba p, uint8_t *d) 889 { 890 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b); 891 *(uint8_t *)d++ = (pixel >> 0) & 0xFF; 892 *(uint8_t *)d++ = (pixel >> 8) & 0xFF; 893 *(uint8_t *)d++ = (pixel >> 16) & 0xFF; 894 return 3; 895 } 896 897 static int put_to_qemufb_pixel32(const rgba p, uint8_t *d) 898 { 899 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b); 900 *(uint32_t *)d = pixel; 901 return 4; 902 } 903 904 /* Routine to copy pixel from internal buffer to QEMU buffer */ 905 static int (*put_pixel_toqemu)(const rgba p, uint8_t *pixel); 906 static inline void fimd_update_putpix_qemu(int bpp) 907 { 908 switch (bpp) { 909 case 8: 910 put_pixel_toqemu = put_to_qemufb_pixel8; 911 break; 912 case 15: 913 put_pixel_toqemu = put_to_qemufb_pixel15; 914 break; 915 case 16: 916 put_pixel_toqemu = put_to_qemufb_pixel16; 917 break; 918 case 24: 919 put_pixel_toqemu = put_to_qemufb_pixel24; 920 break; 921 case 32: 922 put_pixel_toqemu = put_to_qemufb_pixel32; 923 break; 924 default: 925 hw_error("exynos4210.fimd: unsupported BPP (%d)", bpp); 926 break; 927 } 928 } 929 930 /* Routine to copy a line from internal frame buffer to QEMU display */ 931 static void fimd_copy_line_toqemu(int width, uint8_t *src, uint8_t *dst) 932 { 933 rgba p; 934 935 do { 936 src += get_pixel_ifb(src, &p); 937 dst += put_pixel_toqemu(p, dst); 938 } while (--width); 939 } 940 941 /* Parse BPPMODE_F = WINCON1[5:2] bits */ 942 static void exynos4210_fimd_update_win_bppmode(Exynos4210fimdState *s, int win) 943 { 944 Exynos4210fimdWindow *w = &s->window[win]; 945 946 if (w->winmap & FIMD_WINMAP_EN) { 947 w->draw_line = draw_line_mapcolor; 948 return; 949 } 950 951 switch (WIN_BPP_MODE(w)) { 952 case 0: 953 w->draw_line = draw_line_palette_1; 954 w->pixel_to_rgb = 955 palette_data_format[exynos4210_fimd_palette_format(s, win)]; 956 break; 957 case 1: 958 w->draw_line = draw_line_palette_2; 959 w->pixel_to_rgb = 960 palette_data_format[exynos4210_fimd_palette_format(s, win)]; 961 break; 962 case 2: 963 w->draw_line = draw_line_palette_4; 964 w->pixel_to_rgb = 965 palette_data_format[exynos4210_fimd_palette_format(s, win)]; 966 break; 967 case 3: 968 w->draw_line = draw_line_palette_8; 969 w->pixel_to_rgb = 970 palette_data_format[exynos4210_fimd_palette_format(s, win)]; 971 break; 972 case 4: 973 w->draw_line = draw_line_8; 974 w->pixel_to_rgb = pixel_a232_to_rgb; 975 break; 976 case 5: 977 w->draw_line = draw_line_16; 978 w->pixel_to_rgb = pixel_565_to_rgb; 979 break; 980 case 6: 981 w->draw_line = draw_line_16; 982 w->pixel_to_rgb = pixel_a555_to_rgb; 983 break; 984 case 7: 985 w->draw_line = draw_line_16; 986 w->pixel_to_rgb = pixel_1555_to_rgb; 987 break; 988 case 8: 989 w->draw_line = draw_line_32; 990 w->pixel_to_rgb = pixel_666_to_rgb; 991 break; 992 case 9: 993 w->draw_line = draw_line_32; 994 w->pixel_to_rgb = pixel_a665_to_rgb; 995 break; 996 case 10: 997 w->draw_line = draw_line_32; 998 w->pixel_to_rgb = pixel_a666_to_rgb; 999 break; 1000 case 11: 1001 w->draw_line = draw_line_32; 1002 w->pixel_to_rgb = pixel_888_to_rgb; 1003 break; 1004 case 12: 1005 w->draw_line = draw_line_32; 1006 w->pixel_to_rgb = pixel_a887_to_rgb; 1007 break; 1008 case 13: 1009 w->draw_line = draw_line_32; 1010 if ((w->wincon & FIMD_WINCON_BLD_PIX) && (w->wincon & 1011 FIMD_WINCON_ALPHA_SEL)) { 1012 w->pixel_to_rgb = pixel_8888_to_rgb; 1013 } else { 1014 w->pixel_to_rgb = pixel_a888_to_rgb; 1015 } 1016 break; 1017 case 14: 1018 w->draw_line = draw_line_16; 1019 if ((w->wincon & FIMD_WINCON_BLD_PIX) && (w->wincon & 1020 FIMD_WINCON_ALPHA_SEL)) { 1021 w->pixel_to_rgb = pixel_4444_to_rgb; 1022 } else { 1023 w->pixel_to_rgb = pixel_a444_to_rgb; 1024 } 1025 break; 1026 case 15: 1027 w->draw_line = draw_line_16; 1028 w->pixel_to_rgb = pixel_555_to_rgb; 1029 break; 1030 } 1031 } 1032 1033 #if EXYNOS4210_FIMD_MODE_TRACE > 0 1034 static const char *exynos4210_fimd_get_bppmode(int mode_code) 1035 { 1036 switch (mode_code) { 1037 case 0: 1038 return "1 bpp"; 1039 case 1: 1040 return "2 bpp"; 1041 case 2: 1042 return "4 bpp"; 1043 case 3: 1044 return "8 bpp (palettized)"; 1045 case 4: 1046 return "8 bpp (non-palettized, A: 1-R:2-G:3-B:2)"; 1047 case 5: 1048 return "16 bpp (non-palettized, R:5-G:6-B:5)"; 1049 case 6: 1050 return "16 bpp (non-palettized, A:1-R:5-G:5-B:5)"; 1051 case 7: 1052 return "16 bpp (non-palettized, I :1-R:5-G:5-B:5)"; 1053 case 8: 1054 return "Unpacked 18 bpp (non-palettized, R:6-G:6-B:6)"; 1055 case 9: 1056 return "Unpacked 18bpp (non-palettized,A:1-R:6-G:6-B:5)"; 1057 case 10: 1058 return "Unpacked 19bpp (non-palettized,A:1-R:6-G:6-B:6)"; 1059 case 11: 1060 return "Unpacked 24 bpp (non-palettized R:8-G:8-B:8)"; 1061 case 12: 1062 return "Unpacked 24 bpp (non-palettized A:1-R:8-G:8-B:7)"; 1063 case 13: 1064 return "Unpacked 25 bpp (non-palettized A:1-R:8-G:8-B:8)"; 1065 case 14: 1066 return "Unpacked 13 bpp (non-palettized A:1-R:4-G:4-B:4)"; 1067 case 15: 1068 return "Unpacked 15 bpp (non-palettized R:5-G:5-B:5)"; 1069 default: 1070 return "Non-existing bpp mode"; 1071 } 1072 } 1073 1074 static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s, 1075 int win_num, uint32_t val) 1076 { 1077 Exynos4210fimdWindow *w = &s->window[win_num]; 1078 1079 if (w->winmap & FIMD_WINMAP_EN) { 1080 printf("QEMU FIMD: Window %d is mapped with MAPCOLOR=0x%x\n", 1081 win_num, w->winmap & 0xFFFFFF); 1082 return; 1083 } 1084 1085 if ((val != 0xFFFFFFFF) && ((w->wincon >> 2) & 0xF) == ((val >> 2) & 0xF)) { 1086 return; 1087 } 1088 printf("QEMU FIMD: Window %d BPP mode set to %s\n", win_num, 1089 exynos4210_fimd_get_bppmode((val >> 2) & 0xF)); 1090 } 1091 #else 1092 static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s, 1093 int win_num, uint32_t val) 1094 { 1095 1096 } 1097 #endif 1098 1099 static inline int fimd_get_buffer_id(Exynos4210fimdWindow *w) 1100 { 1101 switch (w->wincon & FIMD_WINCON_BUFSTATUS) { 1102 case FIMD_WINCON_BUF0_STAT: 1103 return 0; 1104 case FIMD_WINCON_BUF1_STAT: 1105 return 1; 1106 case FIMD_WINCON_BUF2_STAT: 1107 return 2; 1108 default: 1109 qemu_log_mask(LOG_GUEST_ERROR, "FIMD: Non-existent buffer index\n"); 1110 return 0; 1111 } 1112 } 1113 1114 static void exynos4210_fimd_invalidate(void *opaque) 1115 { 1116 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; 1117 s->invalidate = true; 1118 } 1119 1120 /* Updates specified window's MemorySection based on values of WINCON, 1121 * VIDOSDA, VIDOSDB, VIDWADDx and SHADOWCON registers */ 1122 static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win) 1123 { 1124 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 1125 Exynos4210fimdWindow *w = &s->window[win]; 1126 hwaddr fb_start_addr, fb_mapped_len; 1127 1128 if (!s->enabled || !(w->wincon & FIMD_WINCON_ENWIN) || 1129 FIMD_WINDOW_PROTECTED(s->shadowcon, win)) { 1130 return; 1131 } 1132 1133 if (w->host_fb_addr) { 1134 cpu_physical_memory_unmap(w->host_fb_addr, w->fb_len, 0, 0); 1135 w->host_fb_addr = NULL; 1136 w->fb_len = 0; 1137 } 1138 1139 fb_start_addr = w->buf_start[fimd_get_buffer_id(w)]; 1140 /* Total number of bytes of virtual screen used by current window */ 1141 w->fb_len = fb_mapped_len = (w->virtpage_width + w->virtpage_offsize) * 1142 (w->rightbot_y - w->lefttop_y + 1); 1143 1144 /* TODO: add .exit and unref the region there. Not needed yet since sysbus 1145 * does not support hot-unplug. 1146 */ 1147 if (w->mem_section.mr) { 1148 memory_region_set_log(w->mem_section.mr, false, DIRTY_MEMORY_VGA); 1149 memory_region_unref(w->mem_section.mr); 1150 } 1151 1152 w->mem_section = memory_region_find(sysbus_address_space(sbd), 1153 fb_start_addr, w->fb_len); 1154 assert(w->mem_section.mr); 1155 assert(w->mem_section.offset_within_address_space == fb_start_addr); 1156 DPRINT_TRACE("Window %u framebuffer changed: address=0x%08x, len=0x%x\n", 1157 win, fb_start_addr, w->fb_len); 1158 1159 if (int128_get64(w->mem_section.size) != w->fb_len || 1160 !memory_region_is_ram(w->mem_section.mr)) { 1161 qemu_log_mask(LOG_GUEST_ERROR, 1162 "FIMD: Failed to find window %u framebuffer region\n", 1163 win); 1164 goto error_return; 1165 } 1166 1167 w->host_fb_addr = cpu_physical_memory_map(fb_start_addr, &fb_mapped_len, 1168 false); 1169 if (!w->host_fb_addr) { 1170 qemu_log_mask(LOG_GUEST_ERROR, 1171 "FIMD: Failed to map window %u framebuffer\n", win); 1172 goto error_return; 1173 } 1174 1175 if (fb_mapped_len != w->fb_len) { 1176 qemu_log_mask(LOG_GUEST_ERROR, 1177 "FIMD: Window %u mapped framebuffer length is less than " 1178 "expected\n", win); 1179 cpu_physical_memory_unmap(w->host_fb_addr, fb_mapped_len, 0, 0); 1180 goto error_return; 1181 } 1182 memory_region_set_log(w->mem_section.mr, true, DIRTY_MEMORY_VGA); 1183 exynos4210_fimd_invalidate(s); 1184 return; 1185 1186 error_return: 1187 memory_region_unref(w->mem_section.mr); 1188 w->mem_section.mr = NULL; 1189 w->mem_section.size = int128_zero(); 1190 w->host_fb_addr = NULL; 1191 w->fb_len = 0; 1192 } 1193 1194 static void exynos4210_fimd_enable(Exynos4210fimdState *s, bool enabled) 1195 { 1196 if (enabled && !s->enabled) { 1197 unsigned w; 1198 s->enabled = true; 1199 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1200 fimd_update_memory_section(s, w); 1201 } 1202 } 1203 s->enabled = enabled; 1204 DPRINT_TRACE("display controller %s\n", enabled ? "enabled" : "disabled"); 1205 } 1206 1207 static inline uint32_t unpack_upper_4(uint32_t x) 1208 { 1209 return ((x & 0xF00) << 12) | ((x & 0xF0) << 8) | ((x & 0xF) << 4); 1210 } 1211 1212 static inline uint32_t pack_upper_4(uint32_t x) 1213 { 1214 return (((x & 0xF00000) >> 12) | ((x & 0xF000) >> 8) | 1215 ((x & 0xF0) >> 4)) & 0xFFF; 1216 } 1217 1218 static void exynos4210_fimd_update_irq(Exynos4210fimdState *s) 1219 { 1220 if (!(s->vidintcon[0] & FIMD_VIDINT_INTEN)) { 1221 qemu_irq_lower(s->irq[0]); 1222 qemu_irq_lower(s->irq[1]); 1223 qemu_irq_lower(s->irq[2]); 1224 return; 1225 } 1226 if ((s->vidintcon[0] & FIMD_VIDINT_INTFIFOEN) && 1227 (s->vidintcon[1] & FIMD_VIDINT_INTFIFOPEND)) { 1228 qemu_irq_raise(s->irq[0]); 1229 } else { 1230 qemu_irq_lower(s->irq[0]); 1231 } 1232 if ((s->vidintcon[0] & FIMD_VIDINT_INTFRMEN) && 1233 (s->vidintcon[1] & FIMD_VIDINT_INTFRMPEND)) { 1234 qemu_irq_raise(s->irq[1]); 1235 } else { 1236 qemu_irq_lower(s->irq[1]); 1237 } 1238 if ((s->vidintcon[0] & FIMD_VIDINT_I80IFDONE) && 1239 (s->vidintcon[1] & FIMD_VIDINT_INTI80PEND)) { 1240 qemu_irq_raise(s->irq[2]); 1241 } else { 1242 qemu_irq_lower(s->irq[2]); 1243 } 1244 } 1245 1246 static void exynos4210_update_resolution(Exynos4210fimdState *s) 1247 { 1248 DisplaySurface *surface = qemu_console_surface(s->console); 1249 1250 /* LCD resolution is stored in VIDEO TIME CONTROL REGISTER 2 */ 1251 uint32_t width = ((s->vidtcon[2] >> FIMD_VIDTCON2_HOR_SHIFT) & 1252 FIMD_VIDTCON2_SIZE_MASK) + 1; 1253 uint32_t height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT) & 1254 FIMD_VIDTCON2_SIZE_MASK) + 1; 1255 1256 if (s->ifb == NULL || surface_width(surface) != width || 1257 surface_height(surface) != height) { 1258 DPRINT_L1("Resolution changed from %ux%u to %ux%u\n", 1259 surface_width(surface), surface_height(surface), width, height); 1260 qemu_console_resize(s->console, width, height); 1261 s->ifb = g_realloc(s->ifb, width * height * RGBA_SIZE + 1); 1262 memset(s->ifb, 0, width * height * RGBA_SIZE + 1); 1263 exynos4210_fimd_invalidate(s); 1264 } 1265 } 1266 1267 static void exynos4210_fimd_update(void *opaque) 1268 { 1269 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; 1270 DisplaySurface *surface; 1271 Exynos4210fimdWindow *w; 1272 DirtyBitmapSnapshot *snap; 1273 int i, line; 1274 hwaddr fb_line_addr, inc_size; 1275 int scrn_height; 1276 int first_line = -1, last_line = -1, scrn_width; 1277 bool blend = false; 1278 uint8_t *host_fb_addr; 1279 bool is_dirty = false; 1280 const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1; 1281 1282 if (!s || !s->console || !s->enabled || 1283 surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) { 1284 return; 1285 } 1286 exynos4210_update_resolution(s); 1287 surface = qemu_console_surface(s->console); 1288 1289 for (i = 0; i < NUM_OF_WINDOWS; i++) { 1290 w = &s->window[i]; 1291 if ((w->wincon & FIMD_WINCON_ENWIN) && w->host_fb_addr) { 1292 scrn_height = w->rightbot_y - w->lefttop_y + 1; 1293 scrn_width = w->virtpage_width; 1294 /* Total width of virtual screen page in bytes */ 1295 inc_size = scrn_width + w->virtpage_offsize; 1296 host_fb_addr = w->host_fb_addr; 1297 fb_line_addr = w->mem_section.offset_within_region; 1298 snap = memory_region_snapshot_and_clear_dirty(w->mem_section.mr, 1299 fb_line_addr, inc_size * scrn_height, DIRTY_MEMORY_VGA); 1300 1301 for (line = 0; line < scrn_height; line++) { 1302 is_dirty = memory_region_snapshot_get_dirty(w->mem_section.mr, 1303 snap, fb_line_addr, scrn_width); 1304 1305 if (s->invalidate || is_dirty) { 1306 if (first_line == -1) { 1307 first_line = line; 1308 } 1309 last_line = line; 1310 w->draw_line(w, host_fb_addr, s->ifb + 1311 w->lefttop_x * RGBA_SIZE + (w->lefttop_y + line) * 1312 global_width * RGBA_SIZE, blend); 1313 } 1314 host_fb_addr += inc_size; 1315 fb_line_addr += inc_size; 1316 } 1317 g_free(snap); 1318 blend = true; 1319 } 1320 } 1321 1322 /* Copy resulting image to QEMU_CONSOLE. */ 1323 if (first_line >= 0) { 1324 uint8_t *d; 1325 int bpp; 1326 1327 bpp = surface_bits_per_pixel(surface); 1328 fimd_update_putpix_qemu(bpp); 1329 bpp = (bpp + 1) >> 3; 1330 d = surface_data(surface); 1331 for (line = first_line; line <= last_line; line++) { 1332 fimd_copy_line_toqemu(global_width, s->ifb + global_width * line * 1333 RGBA_SIZE, d + global_width * line * bpp); 1334 } 1335 dpy_gfx_update_full(s->console); 1336 } 1337 s->invalidate = false; 1338 s->vidintcon[1] |= FIMD_VIDINT_INTFRMPEND; 1339 if ((s->vidcon[0] & FIMD_VIDCON0_ENVID_F) == 0) { 1340 exynos4210_fimd_enable(s, false); 1341 } 1342 exynos4210_fimd_update_irq(s); 1343 } 1344 1345 static void exynos4210_fimd_reset(DeviceState *d) 1346 { 1347 Exynos4210fimdState *s = EXYNOS4210_FIMD(d); 1348 unsigned w; 1349 1350 DPRINT_TRACE("Display controller reset\n"); 1351 /* Set all display controller registers to 0 */ 1352 memset(&s->vidcon, 0, (uint8_t *)&s->window - (uint8_t *)&s->vidcon); 1353 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1354 memset(&s->window[w], 0, sizeof(Exynos4210fimdWindow)); 1355 s->window[w].blendeq = 0xC2; 1356 exynos4210_fimd_update_win_bppmode(s, w); 1357 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF); 1358 fimd_update_get_alpha(s, w); 1359 } 1360 1361 g_free(s->ifb); 1362 s->ifb = NULL; 1363 1364 exynos4210_fimd_invalidate(s); 1365 exynos4210_fimd_enable(s, false); 1366 /* Some registers have non-zero initial values */ 1367 s->winchmap = 0x7D517D51; 1368 s->colorgaincon = 0x10040100; 1369 s->huecoef_cr[0] = s->huecoef_cr[3] = 0x01000100; 1370 s->huecoef_cb[0] = s->huecoef_cb[3] = 0x01000100; 1371 s->hueoffset = 0x01800080; 1372 } 1373 1374 static void exynos4210_fimd_write(void *opaque, hwaddr offset, 1375 uint64_t val, unsigned size) 1376 { 1377 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; 1378 unsigned w, i; 1379 uint32_t old_value; 1380 1381 DPRINT_L2("write offset 0x%08x, value=%llu(0x%08llx)\n", offset, 1382 (long long unsigned int)val, (long long unsigned int)val); 1383 1384 switch (offset) { 1385 case FIMD_VIDCON0: 1386 if ((val & FIMD_VIDCON0_ENVID_MASK) == FIMD_VIDCON0_ENVID_MASK) { 1387 exynos4210_fimd_enable(s, true); 1388 } else { 1389 if ((val & FIMD_VIDCON0_ENVID) == 0) { 1390 exynos4210_fimd_enable(s, false); 1391 } 1392 } 1393 s->vidcon[0] = val; 1394 break; 1395 case FIMD_VIDCON1: 1396 /* Leave read-only bits as is */ 1397 val = (val & (~FIMD_VIDCON1_ROMASK)) | 1398 (s->vidcon[1] & FIMD_VIDCON1_ROMASK); 1399 s->vidcon[1] = val; 1400 break; 1401 case FIMD_VIDCON2 ... FIMD_VIDCON3: 1402 s->vidcon[(offset) >> 2] = val; 1403 break; 1404 case FIMD_VIDTCON_START ... FIMD_VIDTCON_END: 1405 s->vidtcon[(offset - FIMD_VIDTCON_START) >> 2] = val; 1406 break; 1407 case FIMD_WINCON_START ... FIMD_WINCON_END: 1408 w = (offset - FIMD_WINCON_START) >> 2; 1409 /* Window's current buffer ID */ 1410 i = fimd_get_buffer_id(&s->window[w]); 1411 old_value = s->window[w].wincon; 1412 val = (val & ~FIMD_WINCON_ROMASK) | 1413 (s->window[w].wincon & FIMD_WINCON_ROMASK); 1414 if (w == 0) { 1415 /* Window 0 wincon ALPHA_MUL bit must always be 0 */ 1416 val &= ~FIMD_WINCON_ALPHA_MUL; 1417 } 1418 exynos4210_fimd_trace_bppmode(s, w, val); 1419 switch (val & FIMD_WINCON_BUFSELECT) { 1420 case FIMD_WINCON_BUF0_SEL: 1421 val &= ~FIMD_WINCON_BUFSTATUS; 1422 break; 1423 case FIMD_WINCON_BUF1_SEL: 1424 val = (val & ~FIMD_WINCON_BUFSTAT_H) | FIMD_WINCON_BUFSTAT_L; 1425 break; 1426 case FIMD_WINCON_BUF2_SEL: 1427 if (val & FIMD_WINCON_BUFMODE) { 1428 val = (val & ~FIMD_WINCON_BUFSTAT_L) | FIMD_WINCON_BUFSTAT_H; 1429 } 1430 break; 1431 default: 1432 break; 1433 } 1434 s->window[w].wincon = val; 1435 exynos4210_fimd_update_win_bppmode(s, w); 1436 fimd_update_get_alpha(s, w); 1437 if ((i != fimd_get_buffer_id(&s->window[w])) || 1438 (!(old_value & FIMD_WINCON_ENWIN) && (s->window[w].wincon & 1439 FIMD_WINCON_ENWIN))) { 1440 fimd_update_memory_section(s, w); 1441 } 1442 break; 1443 case FIMD_SHADOWCON: 1444 old_value = s->shadowcon; 1445 s->shadowcon = val; 1446 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1447 if (FIMD_WINDOW_PROTECTED(old_value, w) && 1448 !FIMD_WINDOW_PROTECTED(s->shadowcon, w)) { 1449 fimd_update_memory_section(s, w); 1450 } 1451 } 1452 break; 1453 case FIMD_WINCHMAP: 1454 s->winchmap = val; 1455 break; 1456 case FIMD_VIDOSD_START ... FIMD_VIDOSD_END: 1457 w = (offset - FIMD_VIDOSD_START) >> 4; 1458 i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2; 1459 switch (i) { 1460 case 0: 1461 old_value = s->window[w].lefttop_y; 1462 s->window[w].lefttop_x = (val >> FIMD_VIDOSD_HOR_SHIFT) & 1463 FIMD_VIDOSD_COORD_MASK; 1464 s->window[w].lefttop_y = (val >> FIMD_VIDOSD_VER_SHIFT) & 1465 FIMD_VIDOSD_COORD_MASK; 1466 if (s->window[w].lefttop_y != old_value) { 1467 fimd_update_memory_section(s, w); 1468 } 1469 break; 1470 case 1: 1471 old_value = s->window[w].rightbot_y; 1472 s->window[w].rightbot_x = (val >> FIMD_VIDOSD_HOR_SHIFT) & 1473 FIMD_VIDOSD_COORD_MASK; 1474 s->window[w].rightbot_y = (val >> FIMD_VIDOSD_VER_SHIFT) & 1475 FIMD_VIDOSD_COORD_MASK; 1476 if (s->window[w].rightbot_y != old_value) { 1477 fimd_update_memory_section(s, w); 1478 } 1479 break; 1480 case 2: 1481 if (w == 0) { 1482 s->window[w].osdsize = val; 1483 } else { 1484 s->window[w].alpha_val[0] = 1485 unpack_upper_4((val & FIMD_VIDOSD_ALPHA_AEN0) >> 1486 FIMD_VIDOSD_AEN0_SHIFT) | 1487 (s->window[w].alpha_val[0] & FIMD_VIDALPHA_ALPHA_LOWER); 1488 s->window[w].alpha_val[1] = 1489 unpack_upper_4(val & FIMD_VIDOSD_ALPHA_AEN1) | 1490 (s->window[w].alpha_val[1] & FIMD_VIDALPHA_ALPHA_LOWER); 1491 } 1492 break; 1493 case 3: 1494 if (w != 1 && w != 2) { 1495 qemu_log_mask(LOG_GUEST_ERROR, 1496 "FIMD: Bad write offset 0x%08"HWADDR_PRIx"\n", 1497 offset); 1498 return; 1499 } 1500 s->window[w].osdsize = val; 1501 break; 1502 } 1503 break; 1504 case FIMD_VIDWADD0_START ... FIMD_VIDWADD0_END: 1505 w = (offset - FIMD_VIDWADD0_START) >> 3; 1506 i = ((offset - FIMD_VIDWADD0_START) >> 2) & 1; 1507 if (i == fimd_get_buffer_id(&s->window[w]) && 1508 s->window[w].buf_start[i] != val) { 1509 s->window[w].buf_start[i] = val; 1510 fimd_update_memory_section(s, w); 1511 break; 1512 } 1513 s->window[w].buf_start[i] = val; 1514 break; 1515 case FIMD_VIDWADD1_START ... FIMD_VIDWADD1_END: 1516 w = (offset - FIMD_VIDWADD1_START) >> 3; 1517 i = ((offset - FIMD_VIDWADD1_START) >> 2) & 1; 1518 s->window[w].buf_end[i] = val; 1519 break; 1520 case FIMD_VIDWADD2_START ... FIMD_VIDWADD2_END: 1521 w = (offset - FIMD_VIDWADD2_START) >> 2; 1522 if (((val & FIMD_VIDWADD2_PAGEWIDTH) != s->window[w].virtpage_width) || 1523 (((val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE) != 1524 s->window[w].virtpage_offsize)) { 1525 s->window[w].virtpage_width = val & FIMD_VIDWADD2_PAGEWIDTH; 1526 s->window[w].virtpage_offsize = 1527 (val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE; 1528 fimd_update_memory_section(s, w); 1529 } 1530 break; 1531 case FIMD_VIDINTCON0: 1532 s->vidintcon[0] = val; 1533 break; 1534 case FIMD_VIDINTCON1: 1535 s->vidintcon[1] &= ~(val & 7); 1536 exynos4210_fimd_update_irq(s); 1537 break; 1538 case FIMD_WKEYCON_START ... FIMD_WKEYCON_END: 1539 w = ((offset - FIMD_WKEYCON_START) >> 3) + 1; 1540 i = ((offset - FIMD_WKEYCON_START) >> 2) & 1; 1541 s->window[w].keycon[i] = val; 1542 break; 1543 case FIMD_WKEYALPHA_START ... FIMD_WKEYALPHA_END: 1544 w = ((offset - FIMD_WKEYALPHA_START) >> 2) + 1; 1545 s->window[w].keyalpha = val; 1546 break; 1547 case FIMD_DITHMODE: 1548 s->dithmode = val; 1549 break; 1550 case FIMD_WINMAP_START ... FIMD_WINMAP_END: 1551 w = (offset - FIMD_WINMAP_START) >> 2; 1552 old_value = s->window[w].winmap; 1553 s->window[w].winmap = val; 1554 if ((val & FIMD_WINMAP_EN) ^ (old_value & FIMD_WINMAP_EN)) { 1555 exynos4210_fimd_invalidate(s); 1556 exynos4210_fimd_update_win_bppmode(s, w); 1557 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF); 1558 exynos4210_fimd_update(s); 1559 } 1560 break; 1561 case FIMD_WPALCON_HIGH ... FIMD_WPALCON_LOW: 1562 i = (offset - FIMD_WPALCON_HIGH) >> 2; 1563 s->wpalcon[i] = val; 1564 if (s->wpalcon[1] & FIMD_WPALCON_UPDATEEN) { 1565 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1566 exynos4210_fimd_update_win_bppmode(s, w); 1567 fimd_update_get_alpha(s, w); 1568 } 1569 } 1570 break; 1571 case FIMD_TRIGCON: 1572 val = (val & ~FIMD_TRIGCON_ROMASK) | (s->trigcon & FIMD_TRIGCON_ROMASK); 1573 s->trigcon = val; 1574 break; 1575 case FIMD_I80IFCON_START ... FIMD_I80IFCON_END: 1576 s->i80ifcon[(offset - FIMD_I80IFCON_START) >> 2] = val; 1577 break; 1578 case FIMD_COLORGAINCON: 1579 s->colorgaincon = val; 1580 break; 1581 case FIMD_LDI_CMDCON0 ... FIMD_LDI_CMDCON1: 1582 s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON0) >> 2] = val; 1583 break; 1584 case FIMD_SIFCCON0 ... FIMD_SIFCCON2: 1585 i = (offset - FIMD_SIFCCON0) >> 2; 1586 if (i != 2) { 1587 s->sifccon[i] = val; 1588 } 1589 break; 1590 case FIMD_HUECOEFCR_START ... FIMD_HUECOEFCR_END: 1591 i = (offset - FIMD_HUECOEFCR_START) >> 2; 1592 s->huecoef_cr[i] = val; 1593 break; 1594 case FIMD_HUECOEFCB_START ... FIMD_HUECOEFCB_END: 1595 i = (offset - FIMD_HUECOEFCB_START) >> 2; 1596 s->huecoef_cb[i] = val; 1597 break; 1598 case FIMD_HUEOFFSET: 1599 s->hueoffset = val; 1600 break; 1601 case FIMD_VIDWALPHA_START ... FIMD_VIDWALPHA_END: 1602 w = ((offset - FIMD_VIDWALPHA_START) >> 3); 1603 i = ((offset - FIMD_VIDWALPHA_START) >> 2) & 1; 1604 if (w == 0) { 1605 s->window[w].alpha_val[i] = val; 1606 } else { 1607 s->window[w].alpha_val[i] = (val & FIMD_VIDALPHA_ALPHA_LOWER) | 1608 (s->window[w].alpha_val[i] & FIMD_VIDALPHA_ALPHA_UPPER); 1609 } 1610 break; 1611 case FIMD_BLENDEQ_START ... FIMD_BLENDEQ_END: 1612 s->window[(offset - FIMD_BLENDEQ_START) >> 2].blendeq = val; 1613 break; 1614 case FIMD_BLENDCON: 1615 old_value = s->blendcon; 1616 s->blendcon = val; 1617 if ((s->blendcon & FIMD_ALPHA_8BIT) != (old_value & FIMD_ALPHA_8BIT)) { 1618 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1619 fimd_update_get_alpha(s, w); 1620 } 1621 } 1622 break; 1623 case FIMD_WRTQOSCON_START ... FIMD_WRTQOSCON_END: 1624 s->window[(offset - FIMD_WRTQOSCON_START) >> 2].rtqoscon = val; 1625 break; 1626 case FIMD_I80IFCMD_START ... FIMD_I80IFCMD_END: 1627 s->i80ifcmd[(offset - FIMD_I80IFCMD_START) >> 2] = val; 1628 break; 1629 case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2: 1630 if (offset & 0x0004) { 1631 qemu_log_mask(LOG_GUEST_ERROR, 1632 "FIMD: bad write offset 0x%08"HWADDR_PRIx"\n", 1633 offset); 1634 break; 1635 } 1636 w = (offset - FIMD_VIDW0ADD0_B2) >> 3; 1637 if (fimd_get_buffer_id(&s->window[w]) == 2 && 1638 s->window[w].buf_start[2] != val) { 1639 s->window[w].buf_start[2] = val; 1640 fimd_update_memory_section(s, w); 1641 break; 1642 } 1643 s->window[w].buf_start[2] = val; 1644 break; 1645 case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END: 1646 if (offset & 0x0004) { 1647 qemu_log_mask(LOG_GUEST_ERROR, 1648 "FIMD: bad write offset 0x%08"HWADDR_PRIx"\n", 1649 offset); 1650 break; 1651 } 1652 s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start = val; 1653 break; 1654 case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END: 1655 if (offset & 0x0004) { 1656 qemu_log_mask(LOG_GUEST_ERROR, 1657 "FIMD: bad write offset 0x%08"HWADDR_PRIx"\n", 1658 offset); 1659 break; 1660 } 1661 s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end = val; 1662 break; 1663 case FIMD_SHD_ADD2_START ... FIMD_SHD_ADD2_END: 1664 s->window[(offset - FIMD_SHD_ADD2_START) >> 2].shadow_buf_size = val; 1665 break; 1666 case FIMD_PAL_MEM_START ... FIMD_PAL_MEM_END: 1667 w = (offset - FIMD_PAL_MEM_START) >> 10; 1668 i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF; 1669 s->window[w].palette[i] = val; 1670 break; 1671 case FIMD_PALMEM_AL_START ... FIMD_PALMEM_AL_END: 1672 /* Palette memory aliases for windows 0 and 1 */ 1673 w = (offset - FIMD_PALMEM_AL_START) >> 10; 1674 i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF; 1675 s->window[w].palette[i] = val; 1676 break; 1677 default: 1678 qemu_log_mask(LOG_GUEST_ERROR, 1679 "FIMD: bad write offset 0x%08"HWADDR_PRIx"\n", offset); 1680 break; 1681 } 1682 } 1683 1684 static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset, 1685 unsigned size) 1686 { 1687 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; 1688 int w, i; 1689 uint32_t ret = 0; 1690 1691 DPRINT_L2("read offset 0x%08x\n", offset); 1692 1693 switch (offset) { 1694 case FIMD_VIDCON0 ... FIMD_VIDCON3: 1695 return s->vidcon[(offset - FIMD_VIDCON0) >> 2]; 1696 case FIMD_VIDTCON_START ... FIMD_VIDTCON_END: 1697 return s->vidtcon[(offset - FIMD_VIDTCON_START) >> 2]; 1698 case FIMD_WINCON_START ... FIMD_WINCON_END: 1699 return s->window[(offset - FIMD_WINCON_START) >> 2].wincon; 1700 case FIMD_SHADOWCON: 1701 return s->shadowcon; 1702 case FIMD_WINCHMAP: 1703 return s->winchmap; 1704 case FIMD_VIDOSD_START ... FIMD_VIDOSD_END: 1705 w = (offset - FIMD_VIDOSD_START) >> 4; 1706 i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2; 1707 switch (i) { 1708 case 0: 1709 ret = ((s->window[w].lefttop_x & FIMD_VIDOSD_COORD_MASK) << 1710 FIMD_VIDOSD_HOR_SHIFT) | 1711 (s->window[w].lefttop_y & FIMD_VIDOSD_COORD_MASK); 1712 break; 1713 case 1: 1714 ret = ((s->window[w].rightbot_x & FIMD_VIDOSD_COORD_MASK) << 1715 FIMD_VIDOSD_HOR_SHIFT) | 1716 (s->window[w].rightbot_y & FIMD_VIDOSD_COORD_MASK); 1717 break; 1718 case 2: 1719 if (w == 0) { 1720 ret = s->window[w].osdsize; 1721 } else { 1722 ret = (pack_upper_4(s->window[w].alpha_val[0]) << 1723 FIMD_VIDOSD_AEN0_SHIFT) | 1724 pack_upper_4(s->window[w].alpha_val[1]); 1725 } 1726 break; 1727 case 3: 1728 if (w != 1 && w != 2) { 1729 qemu_log_mask(LOG_GUEST_ERROR, 1730 "FIMD: bad read offset 0x%08"HWADDR_PRIx"\n", 1731 offset); 1732 return 0xBAADBAAD; 1733 } 1734 ret = s->window[w].osdsize; 1735 break; 1736 } 1737 return ret; 1738 case FIMD_VIDWADD0_START ... FIMD_VIDWADD0_END: 1739 w = (offset - FIMD_VIDWADD0_START) >> 3; 1740 i = ((offset - FIMD_VIDWADD0_START) >> 2) & 1; 1741 return s->window[w].buf_start[i]; 1742 case FIMD_VIDWADD1_START ... FIMD_VIDWADD1_END: 1743 w = (offset - FIMD_VIDWADD1_START) >> 3; 1744 i = ((offset - FIMD_VIDWADD1_START) >> 2) & 1; 1745 return s->window[w].buf_end[i]; 1746 case FIMD_VIDWADD2_START ... FIMD_VIDWADD2_END: 1747 w = (offset - FIMD_VIDWADD2_START) >> 2; 1748 return s->window[w].virtpage_width | (s->window[w].virtpage_offsize << 1749 FIMD_VIDWADD2_OFFSIZE_SHIFT); 1750 case FIMD_VIDINTCON0 ... FIMD_VIDINTCON1: 1751 return s->vidintcon[(offset - FIMD_VIDINTCON0) >> 2]; 1752 case FIMD_WKEYCON_START ... FIMD_WKEYCON_END: 1753 w = ((offset - FIMD_WKEYCON_START) >> 3) + 1; 1754 i = ((offset - FIMD_WKEYCON_START) >> 2) & 1; 1755 return s->window[w].keycon[i]; 1756 case FIMD_WKEYALPHA_START ... FIMD_WKEYALPHA_END: 1757 w = ((offset - FIMD_WKEYALPHA_START) >> 2) + 1; 1758 return s->window[w].keyalpha; 1759 case FIMD_DITHMODE: 1760 return s->dithmode; 1761 case FIMD_WINMAP_START ... FIMD_WINMAP_END: 1762 return s->window[(offset - FIMD_WINMAP_START) >> 2].winmap; 1763 case FIMD_WPALCON_HIGH ... FIMD_WPALCON_LOW: 1764 return s->wpalcon[(offset - FIMD_WPALCON_HIGH) >> 2]; 1765 case FIMD_TRIGCON: 1766 return s->trigcon; 1767 case FIMD_I80IFCON_START ... FIMD_I80IFCON_END: 1768 return s->i80ifcon[(offset - FIMD_I80IFCON_START) >> 2]; 1769 case FIMD_COLORGAINCON: 1770 return s->colorgaincon; 1771 case FIMD_LDI_CMDCON0 ... FIMD_LDI_CMDCON1: 1772 return s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON0) >> 2]; 1773 case FIMD_SIFCCON0 ... FIMD_SIFCCON2: 1774 i = (offset - FIMD_SIFCCON0) >> 2; 1775 return s->sifccon[i]; 1776 case FIMD_HUECOEFCR_START ... FIMD_HUECOEFCR_END: 1777 i = (offset - FIMD_HUECOEFCR_START) >> 2; 1778 return s->huecoef_cr[i]; 1779 case FIMD_HUECOEFCB_START ... FIMD_HUECOEFCB_END: 1780 i = (offset - FIMD_HUECOEFCB_START) >> 2; 1781 return s->huecoef_cb[i]; 1782 case FIMD_HUEOFFSET: 1783 return s->hueoffset; 1784 case FIMD_VIDWALPHA_START ... FIMD_VIDWALPHA_END: 1785 w = ((offset - FIMD_VIDWALPHA_START) >> 3); 1786 i = ((offset - FIMD_VIDWALPHA_START) >> 2) & 1; 1787 return s->window[w].alpha_val[i] & 1788 (w == 0 ? 0xFFFFFF : FIMD_VIDALPHA_ALPHA_LOWER); 1789 case FIMD_BLENDEQ_START ... FIMD_BLENDEQ_END: 1790 return s->window[(offset - FIMD_BLENDEQ_START) >> 2].blendeq; 1791 case FIMD_BLENDCON: 1792 return s->blendcon; 1793 case FIMD_WRTQOSCON_START ... FIMD_WRTQOSCON_END: 1794 return s->window[(offset - FIMD_WRTQOSCON_START) >> 2].rtqoscon; 1795 case FIMD_I80IFCMD_START ... FIMD_I80IFCMD_END: 1796 return s->i80ifcmd[(offset - FIMD_I80IFCMD_START) >> 2]; 1797 case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2: 1798 if (offset & 0x0004) { 1799 break; 1800 } 1801 return s->window[(offset - FIMD_VIDW0ADD0_B2) >> 3].buf_start[2]; 1802 case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END: 1803 if (offset & 0x0004) { 1804 break; 1805 } 1806 return s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start; 1807 case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END: 1808 if (offset & 0x0004) { 1809 break; 1810 } 1811 return s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end; 1812 case FIMD_SHD_ADD2_START ... FIMD_SHD_ADD2_END: 1813 return s->window[(offset - FIMD_SHD_ADD2_START) >> 2].shadow_buf_size; 1814 case FIMD_PAL_MEM_START ... FIMD_PAL_MEM_END: 1815 w = (offset - FIMD_PAL_MEM_START) >> 10; 1816 i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF; 1817 return s->window[w].palette[i]; 1818 case FIMD_PALMEM_AL_START ... FIMD_PALMEM_AL_END: 1819 /* Palette aliases for win 0,1 */ 1820 w = (offset - FIMD_PALMEM_AL_START) >> 10; 1821 i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF; 1822 return s->window[w].palette[i]; 1823 } 1824 1825 qemu_log_mask(LOG_GUEST_ERROR, 1826 "FIMD: bad read offset 0x%08"HWADDR_PRIx"\n", offset); 1827 return 0xBAADBAAD; 1828 } 1829 1830 static const MemoryRegionOps exynos4210_fimd_mmio_ops = { 1831 .read = exynos4210_fimd_read, 1832 .write = exynos4210_fimd_write, 1833 .valid = { 1834 .min_access_size = 4, 1835 .max_access_size = 4, 1836 .unaligned = false 1837 }, 1838 .endianness = DEVICE_NATIVE_ENDIAN, 1839 }; 1840 1841 static int exynos4210_fimd_load(void *opaque, int version_id) 1842 { 1843 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; 1844 int w; 1845 1846 if (version_id != 1) { 1847 return -EINVAL; 1848 } 1849 1850 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1851 exynos4210_fimd_update_win_bppmode(s, w); 1852 fimd_update_get_alpha(s, w); 1853 fimd_update_memory_section(s, w); 1854 } 1855 1856 /* Redraw the whole screen */ 1857 exynos4210_update_resolution(s); 1858 exynos4210_fimd_invalidate(s); 1859 exynos4210_fimd_enable(s, (s->vidcon[0] & FIMD_VIDCON0_ENVID_MASK) == 1860 FIMD_VIDCON0_ENVID_MASK); 1861 return 0; 1862 } 1863 1864 static const VMStateDescription exynos4210_fimd_window_vmstate = { 1865 .name = "exynos4210.fimd_window", 1866 .version_id = 1, 1867 .minimum_version_id = 1, 1868 .fields = (VMStateField[]) { 1869 VMSTATE_UINT32(wincon, Exynos4210fimdWindow), 1870 VMSTATE_UINT32_ARRAY(buf_start, Exynos4210fimdWindow, 3), 1871 VMSTATE_UINT32_ARRAY(buf_end, Exynos4210fimdWindow, 3), 1872 VMSTATE_UINT32_ARRAY(keycon, Exynos4210fimdWindow, 2), 1873 VMSTATE_UINT32(keyalpha, Exynos4210fimdWindow), 1874 VMSTATE_UINT32(winmap, Exynos4210fimdWindow), 1875 VMSTATE_UINT32(blendeq, Exynos4210fimdWindow), 1876 VMSTATE_UINT32(rtqoscon, Exynos4210fimdWindow), 1877 VMSTATE_UINT32_ARRAY(palette, Exynos4210fimdWindow, 256), 1878 VMSTATE_UINT32(shadow_buf_start, Exynos4210fimdWindow), 1879 VMSTATE_UINT32(shadow_buf_end, Exynos4210fimdWindow), 1880 VMSTATE_UINT32(shadow_buf_size, Exynos4210fimdWindow), 1881 VMSTATE_UINT16(lefttop_x, Exynos4210fimdWindow), 1882 VMSTATE_UINT16(lefttop_y, Exynos4210fimdWindow), 1883 VMSTATE_UINT16(rightbot_x, Exynos4210fimdWindow), 1884 VMSTATE_UINT16(rightbot_y, Exynos4210fimdWindow), 1885 VMSTATE_UINT32(osdsize, Exynos4210fimdWindow), 1886 VMSTATE_UINT32_ARRAY(alpha_val, Exynos4210fimdWindow, 2), 1887 VMSTATE_UINT16(virtpage_width, Exynos4210fimdWindow), 1888 VMSTATE_UINT16(virtpage_offsize, Exynos4210fimdWindow), 1889 VMSTATE_END_OF_LIST() 1890 } 1891 }; 1892 1893 static const VMStateDescription exynos4210_fimd_vmstate = { 1894 .name = "exynos4210.fimd", 1895 .version_id = 1, 1896 .minimum_version_id = 1, 1897 .post_load = exynos4210_fimd_load, 1898 .fields = (VMStateField[]) { 1899 VMSTATE_UINT32_ARRAY(vidcon, Exynos4210fimdState, 4), 1900 VMSTATE_UINT32_ARRAY(vidtcon, Exynos4210fimdState, 4), 1901 VMSTATE_UINT32(shadowcon, Exynos4210fimdState), 1902 VMSTATE_UINT32(winchmap, Exynos4210fimdState), 1903 VMSTATE_UINT32_ARRAY(vidintcon, Exynos4210fimdState, 2), 1904 VMSTATE_UINT32(dithmode, Exynos4210fimdState), 1905 VMSTATE_UINT32_ARRAY(wpalcon, Exynos4210fimdState, 2), 1906 VMSTATE_UINT32(trigcon, Exynos4210fimdState), 1907 VMSTATE_UINT32_ARRAY(i80ifcon, Exynos4210fimdState, 4), 1908 VMSTATE_UINT32(colorgaincon, Exynos4210fimdState), 1909 VMSTATE_UINT32_ARRAY(ldi_cmdcon, Exynos4210fimdState, 2), 1910 VMSTATE_UINT32_ARRAY(sifccon, Exynos4210fimdState, 3), 1911 VMSTATE_UINT32_ARRAY(huecoef_cr, Exynos4210fimdState, 4), 1912 VMSTATE_UINT32_ARRAY(huecoef_cb, Exynos4210fimdState, 4), 1913 VMSTATE_UINT32(hueoffset, Exynos4210fimdState), 1914 VMSTATE_UINT32_ARRAY(i80ifcmd, Exynos4210fimdState, 12), 1915 VMSTATE_UINT32(blendcon, Exynos4210fimdState), 1916 VMSTATE_STRUCT_ARRAY(window, Exynos4210fimdState, 5, 1, 1917 exynos4210_fimd_window_vmstate, Exynos4210fimdWindow), 1918 VMSTATE_END_OF_LIST() 1919 } 1920 }; 1921 1922 static const GraphicHwOps exynos4210_fimd_ops = { 1923 .invalidate = exynos4210_fimd_invalidate, 1924 .gfx_update = exynos4210_fimd_update, 1925 }; 1926 1927 static void exynos4210_fimd_init(Object *obj) 1928 { 1929 Exynos4210fimdState *s = EXYNOS4210_FIMD(obj); 1930 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 1931 1932 s->ifb = NULL; 1933 1934 sysbus_init_irq(dev, &s->irq[0]); 1935 sysbus_init_irq(dev, &s->irq[1]); 1936 sysbus_init_irq(dev, &s->irq[2]); 1937 1938 memory_region_init_io(&s->iomem, obj, &exynos4210_fimd_mmio_ops, s, 1939 "exynos4210.fimd", FIMD_REGS_SIZE); 1940 sysbus_init_mmio(dev, &s->iomem); 1941 } 1942 1943 static void exynos4210_fimd_realize(DeviceState *dev, Error **errp) 1944 { 1945 Exynos4210fimdState *s = EXYNOS4210_FIMD(dev); 1946 1947 s->console = graphic_console_init(dev, 0, &exynos4210_fimd_ops, s); 1948 } 1949 1950 static void exynos4210_fimd_class_init(ObjectClass *klass, void *data) 1951 { 1952 DeviceClass *dc = DEVICE_CLASS(klass); 1953 1954 dc->vmsd = &exynos4210_fimd_vmstate; 1955 dc->reset = exynos4210_fimd_reset; 1956 dc->realize = exynos4210_fimd_realize; 1957 } 1958 1959 static const TypeInfo exynos4210_fimd_info = { 1960 .name = TYPE_EXYNOS4210_FIMD, 1961 .parent = TYPE_SYS_BUS_DEVICE, 1962 .instance_size = sizeof(Exynos4210fimdState), 1963 .instance_init = exynos4210_fimd_init, 1964 .class_init = exynos4210_fimd_class_init, 1965 }; 1966 1967 static void exynos4210_fimd_register_types(void) 1968 { 1969 type_register_static(&exynos4210_fimd_info); 1970 } 1971 1972 type_init(exynos4210_fimd_register_types) 1973