xref: /openbmc/qemu/hw/display/cirrus_vga_internal.h (revision ff56877e911782dedc9a424233fd3f62369c258c)
1  /*
2   * QEMU Cirrus CLGD 54xx VGA Emulator, ISA bus support
3   *
4   * Copyright (c) 2004 Fabrice Bellard
5   * Copyright (c) 2004 Makoto Suzuki (suzu)
6   *
7   * Permission is hereby granted, free of charge, to any person obtaining a copy
8   * of this software and associated documentation files (the "Software"), to deal
9   * in the Software without restriction, including without limitation the rights
10   * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11   * copies of the Software, and to permit persons to whom the Software is
12   * furnished to do so, subject to the following conditions:
13   *
14   * The above copyright notice and this permission notice shall be included in
15   * all copies or substantial portions of the Software.
16   *
17   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21   * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22   * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23   * THE SOFTWARE.
24   */
25  
26  #ifndef CIRRUS_VGA_INTERNAL_H
27  #define CIRRUS_VGA_INTERNAL_H
28  
29  #include "vga_int.h"
30  
31  /* IDs */
32  #define CIRRUS_ID_CLGD5422  (0x23 << 2)
33  #define CIRRUS_ID_CLGD5426  (0x24 << 2)
34  #define CIRRUS_ID_CLGD5424  (0x25 << 2)
35  #define CIRRUS_ID_CLGD5428  (0x26 << 2)
36  #define CIRRUS_ID_CLGD5430  (0x28 << 2)
37  #define CIRRUS_ID_CLGD5434  (0x2A << 2)
38  #define CIRRUS_ID_CLGD5436  (0x2B << 2)
39  #define CIRRUS_ID_CLGD5446  (0x2E << 2)
40  
41  extern const VMStateDescription vmstate_cirrus_vga;
42  
43  struct CirrusVGAState;
44  typedef void (*cirrus_bitblt_rop_t)(struct CirrusVGAState *s,
45                                      uint32_t dstaddr, uint32_t srcaddr,
46                                      int dstpitch, int srcpitch,
47                                      int bltwidth, int bltheight);
48  
49  typedef struct CirrusVGAState {
50      VGACommonState vga;
51  
52      MemoryRegion cirrus_vga_io;
53      MemoryRegion cirrus_linear_io;
54      MemoryRegion cirrus_linear_bitblt_io;
55      MemoryRegion cirrus_mmio_io;
56      MemoryRegion pci_bar;
57      bool linear_vram;  /* vga.vram mapped over cirrus_linear_io */
58      MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
59      MemoryRegion low_mem;           /* always mapped, overridden by: */
60      MemoryRegion cirrus_bank[2];    /*   aliases at 0xa0000-0xb0000  */
61      uint32_t cirrus_addr_mask;
62      uint32_t linear_mmio_mask;
63      uint8_t cirrus_shadow_gr0;
64      uint8_t cirrus_shadow_gr1;
65      uint8_t cirrus_hidden_dac_lockindex;
66      uint8_t cirrus_hidden_dac_data;
67      uint32_t cirrus_bank_base[2];
68      uint32_t cirrus_bank_limit[2];
69      uint8_t cirrus_hidden_palette[48];
70      bool enable_blitter;
71      int cirrus_blt_pixelwidth;
72      int cirrus_blt_width;
73      int cirrus_blt_height;
74      int cirrus_blt_dstpitch;
75      int cirrus_blt_srcpitch;
76      uint32_t cirrus_blt_fgcol;
77      uint32_t cirrus_blt_bgcol;
78      uint32_t cirrus_blt_dstaddr;
79      uint32_t cirrus_blt_srcaddr;
80      uint8_t cirrus_blt_mode;
81      uint8_t cirrus_blt_modeext;
82      cirrus_bitblt_rop_t cirrus_rop;
83  #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
84      uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
85      uint8_t *cirrus_srcptr;
86      uint8_t *cirrus_srcptr_end;
87      uint32_t cirrus_srccounter;
88      /* hwcursor display state */
89      int last_hw_cursor_size;
90      int last_hw_cursor_x;
91      int last_hw_cursor_y;
92      int last_hw_cursor_y_start;
93      int last_hw_cursor_y_end;
94      int real_vram_size; /* XXX: suppress that */
95      int device_id;
96      int bustype;
97  } CirrusVGAState;
98  
99  void cirrus_init_common(CirrusVGAState *s, Object *owner,
100                          int device_id, int is_pci,
101                          MemoryRegion *system_memory, MemoryRegion *system_io);
102  
103  #endif
104