1 /* 2 * QEMU Cirrus CLGD 54xx VGA Emulator. 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * Copyright (c) 2004 Makoto Suzuki (suzu) 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 /* 26 * Reference: Finn Thogersons' VGADOC4b 27 * available at http://home.worldonline.dk/~finth/ 28 */ 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "trace.h" 32 #include "hw/hw.h" 33 #include "hw/pci/pci.h" 34 #include "ui/console.h" 35 #include "ui/pixel_ops.h" 36 #include "vga_int.h" 37 #include "hw/loader.h" 38 39 /* 40 * TODO: 41 * - destination write mask support not complete (bits 5..7) 42 * - optimize linear mappings 43 * - optimize bitblt functions 44 */ 45 46 //#define DEBUG_CIRRUS 47 //#define DEBUG_BITBLT 48 49 /*************************************** 50 * 51 * definitions 52 * 53 ***************************************/ 54 55 // ID 56 #define CIRRUS_ID_CLGD5422 (0x23<<2) 57 #define CIRRUS_ID_CLGD5426 (0x24<<2) 58 #define CIRRUS_ID_CLGD5424 (0x25<<2) 59 #define CIRRUS_ID_CLGD5428 (0x26<<2) 60 #define CIRRUS_ID_CLGD5430 (0x28<<2) 61 #define CIRRUS_ID_CLGD5434 (0x2A<<2) 62 #define CIRRUS_ID_CLGD5436 (0x2B<<2) 63 #define CIRRUS_ID_CLGD5446 (0x2E<<2) 64 65 // sequencer 0x07 66 #define CIRRUS_SR7_BPP_VGA 0x00 67 #define CIRRUS_SR7_BPP_SVGA 0x01 68 #define CIRRUS_SR7_BPP_MASK 0x0e 69 #define CIRRUS_SR7_BPP_8 0x00 70 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02 71 #define CIRRUS_SR7_BPP_24 0x04 72 #define CIRRUS_SR7_BPP_16 0x06 73 #define CIRRUS_SR7_BPP_32 0x08 74 #define CIRRUS_SR7_ISAADDR_MASK 0xe0 75 76 // sequencer 0x0f 77 #define CIRRUS_MEMSIZE_512k 0x08 78 #define CIRRUS_MEMSIZE_1M 0x10 79 #define CIRRUS_MEMSIZE_2M 0x18 80 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled. 81 82 // sequencer 0x12 83 #define CIRRUS_CURSOR_SHOW 0x01 84 #define CIRRUS_CURSOR_HIDDENPEL 0x02 85 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear 86 87 // sequencer 0x17 88 #define CIRRUS_BUSTYPE_VLBFAST 0x10 89 #define CIRRUS_BUSTYPE_PCI 0x20 90 #define CIRRUS_BUSTYPE_VLBSLOW 0x30 91 #define CIRRUS_BUSTYPE_ISA 0x38 92 #define CIRRUS_MMIO_ENABLE 0x04 93 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared. 94 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80 95 96 // control 0x0b 97 #define CIRRUS_BANKING_DUAL 0x01 98 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k 99 100 // control 0x30 101 #define CIRRUS_BLTMODE_BACKWARDS 0x01 102 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02 103 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04 104 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08 105 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40 106 #define CIRRUS_BLTMODE_COLOREXPAND 0x80 107 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30 108 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00 109 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10 110 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20 111 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30 112 113 // control 0x31 114 #define CIRRUS_BLT_BUSY 0x01 115 #define CIRRUS_BLT_START 0x02 116 #define CIRRUS_BLT_RESET 0x04 117 #define CIRRUS_BLT_FIFOUSED 0x10 118 #define CIRRUS_BLT_AUTOSTART 0x80 119 120 // control 0x32 121 #define CIRRUS_ROP_0 0x00 122 #define CIRRUS_ROP_SRC_AND_DST 0x05 123 #define CIRRUS_ROP_NOP 0x06 124 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09 125 #define CIRRUS_ROP_NOTDST 0x0b 126 #define CIRRUS_ROP_SRC 0x0d 127 #define CIRRUS_ROP_1 0x0e 128 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50 129 #define CIRRUS_ROP_SRC_XOR_DST 0x59 130 #define CIRRUS_ROP_SRC_OR_DST 0x6d 131 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90 132 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95 133 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad 134 #define CIRRUS_ROP_NOTSRC 0xd0 135 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6 136 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda 137 138 #define CIRRUS_ROP_NOP_INDEX 2 139 #define CIRRUS_ROP_SRC_INDEX 5 140 141 // control 0x33 142 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04 143 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02 144 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01 145 146 // memory-mapped IO 147 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword 148 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword 149 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word 150 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word 151 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word 152 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word 153 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword 154 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword 155 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte 156 #define CIRRUS_MMIO_BLTMODE 0x18 // byte 157 #define CIRRUS_MMIO_BLTROP 0x1a // byte 158 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte 159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word? 160 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word? 161 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word 162 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word 163 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word 164 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word 165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte 166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte 167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte 168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte 169 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word 170 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word 171 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word 172 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word 173 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte 174 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte 175 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte 176 177 #define CIRRUS_PNPMMIO_SIZE 0x1000 178 179 struct CirrusVGAState; 180 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s, 181 uint8_t * dst, const uint8_t * src, 182 int dstpitch, int srcpitch, 183 int bltwidth, int bltheight); 184 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s, 185 uint8_t *dst, int dst_pitch, int width, int height); 186 187 typedef struct CirrusVGAState { 188 VGACommonState vga; 189 190 MemoryRegion cirrus_vga_io; 191 MemoryRegion cirrus_linear_io; 192 MemoryRegion cirrus_linear_bitblt_io; 193 MemoryRegion cirrus_mmio_io; 194 MemoryRegion pci_bar; 195 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */ 196 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */ 197 MemoryRegion low_mem; /* always mapped, overridden by: */ 198 MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */ 199 uint32_t cirrus_addr_mask; 200 uint32_t linear_mmio_mask; 201 uint8_t cirrus_shadow_gr0; 202 uint8_t cirrus_shadow_gr1; 203 uint8_t cirrus_hidden_dac_lockindex; 204 uint8_t cirrus_hidden_dac_data; 205 uint32_t cirrus_bank_base[2]; 206 uint32_t cirrus_bank_limit[2]; 207 uint8_t cirrus_hidden_palette[48]; 208 int cirrus_blt_pixelwidth; 209 int cirrus_blt_width; 210 int cirrus_blt_height; 211 int cirrus_blt_dstpitch; 212 int cirrus_blt_srcpitch; 213 uint32_t cirrus_blt_fgcol; 214 uint32_t cirrus_blt_bgcol; 215 uint32_t cirrus_blt_dstaddr; 216 uint32_t cirrus_blt_srcaddr; 217 uint8_t cirrus_blt_mode; 218 uint8_t cirrus_blt_modeext; 219 cirrus_bitblt_rop_t cirrus_rop; 220 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */ 221 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE]; 222 uint8_t *cirrus_srcptr; 223 uint8_t *cirrus_srcptr_end; 224 uint32_t cirrus_srccounter; 225 /* hwcursor display state */ 226 int last_hw_cursor_size; 227 int last_hw_cursor_x; 228 int last_hw_cursor_y; 229 int last_hw_cursor_y_start; 230 int last_hw_cursor_y_end; 231 int real_vram_size; /* XXX: suppress that */ 232 int device_id; 233 int bustype; 234 } CirrusVGAState; 235 236 typedef struct PCICirrusVGAState { 237 PCIDevice dev; 238 CirrusVGAState cirrus_vga; 239 } PCICirrusVGAState; 240 241 #define TYPE_PCI_CIRRUS_VGA "cirrus-vga" 242 #define PCI_CIRRUS_VGA(obj) \ 243 OBJECT_CHECK(PCICirrusVGAState, (obj), TYPE_PCI_CIRRUS_VGA) 244 245 #define TYPE_ISA_CIRRUS_VGA "isa-cirrus-vga" 246 #define ISA_CIRRUS_VGA(obj) \ 247 OBJECT_CHECK(ISACirrusVGAState, (obj), TYPE_ISA_CIRRUS_VGA) 248 249 typedef struct ISACirrusVGAState { 250 ISADevice parent_obj; 251 252 CirrusVGAState cirrus_vga; 253 } ISACirrusVGAState; 254 255 static uint8_t rop_to_index[256]; 256 257 /*************************************** 258 * 259 * prototypes. 260 * 261 ***************************************/ 262 263 264 static void cirrus_bitblt_reset(CirrusVGAState *s); 265 static void cirrus_update_memory_access(CirrusVGAState *s); 266 267 /*************************************** 268 * 269 * raster operations 270 * 271 ***************************************/ 272 273 static bool blit_region_is_unsafe(struct CirrusVGAState *s, 274 int32_t pitch, int32_t addr) 275 { 276 if (!pitch) { 277 return true; 278 } 279 if (pitch < 0) { 280 int64_t min = addr 281 + ((int64_t)s->cirrus_blt_height - 1) * pitch 282 - s->cirrus_blt_width; 283 if (min < -1 || addr >= s->vga.vram_size) { 284 return true; 285 } 286 } else { 287 int64_t max = addr 288 + ((int64_t)s->cirrus_blt_height-1) * pitch 289 + s->cirrus_blt_width; 290 if (max > s->vga.vram_size) { 291 return true; 292 } 293 } 294 return false; 295 } 296 297 static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only) 298 { 299 /* should be the case, see cirrus_bitblt_start */ 300 assert(s->cirrus_blt_width > 0); 301 assert(s->cirrus_blt_height > 0); 302 303 if (s->cirrus_blt_width > CIRRUS_BLTBUFSIZE) { 304 return true; 305 } 306 307 if (blit_region_is_unsafe(s, s->cirrus_blt_dstpitch, 308 s->cirrus_blt_dstaddr)) { 309 return true; 310 } 311 if (dst_only) { 312 return false; 313 } 314 if (blit_region_is_unsafe(s, s->cirrus_blt_srcpitch, 315 s->cirrus_blt_srcaddr)) { 316 return true; 317 } 318 319 return false; 320 } 321 322 static void cirrus_bitblt_rop_nop(CirrusVGAState *s, 323 uint8_t *dst,const uint8_t *src, 324 int dstpitch,int srcpitch, 325 int bltwidth,int bltheight) 326 { 327 } 328 329 static void cirrus_bitblt_fill_nop(CirrusVGAState *s, 330 uint8_t *dst, 331 int dstpitch, int bltwidth,int bltheight) 332 { 333 } 334 335 #define ROP_NAME 0 336 #define ROP_FN(d, s) 0 337 #include "cirrus_vga_rop.h" 338 339 #define ROP_NAME src_and_dst 340 #define ROP_FN(d, s) (s) & (d) 341 #include "cirrus_vga_rop.h" 342 343 #define ROP_NAME src_and_notdst 344 #define ROP_FN(d, s) (s) & (~(d)) 345 #include "cirrus_vga_rop.h" 346 347 #define ROP_NAME notdst 348 #define ROP_FN(d, s) ~(d) 349 #include "cirrus_vga_rop.h" 350 351 #define ROP_NAME src 352 #define ROP_FN(d, s) s 353 #include "cirrus_vga_rop.h" 354 355 #define ROP_NAME 1 356 #define ROP_FN(d, s) ~0 357 #include "cirrus_vga_rop.h" 358 359 #define ROP_NAME notsrc_and_dst 360 #define ROP_FN(d, s) (~(s)) & (d) 361 #include "cirrus_vga_rop.h" 362 363 #define ROP_NAME src_xor_dst 364 #define ROP_FN(d, s) (s) ^ (d) 365 #include "cirrus_vga_rop.h" 366 367 #define ROP_NAME src_or_dst 368 #define ROP_FN(d, s) (s) | (d) 369 #include "cirrus_vga_rop.h" 370 371 #define ROP_NAME notsrc_or_notdst 372 #define ROP_FN(d, s) (~(s)) | (~(d)) 373 #include "cirrus_vga_rop.h" 374 375 #define ROP_NAME src_notxor_dst 376 #define ROP_FN(d, s) ~((s) ^ (d)) 377 #include "cirrus_vga_rop.h" 378 379 #define ROP_NAME src_or_notdst 380 #define ROP_FN(d, s) (s) | (~(d)) 381 #include "cirrus_vga_rop.h" 382 383 #define ROP_NAME notsrc 384 #define ROP_FN(d, s) (~(s)) 385 #include "cirrus_vga_rop.h" 386 387 #define ROP_NAME notsrc_or_dst 388 #define ROP_FN(d, s) (~(s)) | (d) 389 #include "cirrus_vga_rop.h" 390 391 #define ROP_NAME notsrc_and_notdst 392 #define ROP_FN(d, s) (~(s)) & (~(d)) 393 #include "cirrus_vga_rop.h" 394 395 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = { 396 cirrus_bitblt_rop_fwd_0, 397 cirrus_bitblt_rop_fwd_src_and_dst, 398 cirrus_bitblt_rop_nop, 399 cirrus_bitblt_rop_fwd_src_and_notdst, 400 cirrus_bitblt_rop_fwd_notdst, 401 cirrus_bitblt_rop_fwd_src, 402 cirrus_bitblt_rop_fwd_1, 403 cirrus_bitblt_rop_fwd_notsrc_and_dst, 404 cirrus_bitblt_rop_fwd_src_xor_dst, 405 cirrus_bitblt_rop_fwd_src_or_dst, 406 cirrus_bitblt_rop_fwd_notsrc_or_notdst, 407 cirrus_bitblt_rop_fwd_src_notxor_dst, 408 cirrus_bitblt_rop_fwd_src_or_notdst, 409 cirrus_bitblt_rop_fwd_notsrc, 410 cirrus_bitblt_rop_fwd_notsrc_or_dst, 411 cirrus_bitblt_rop_fwd_notsrc_and_notdst, 412 }; 413 414 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = { 415 cirrus_bitblt_rop_bkwd_0, 416 cirrus_bitblt_rop_bkwd_src_and_dst, 417 cirrus_bitblt_rop_nop, 418 cirrus_bitblt_rop_bkwd_src_and_notdst, 419 cirrus_bitblt_rop_bkwd_notdst, 420 cirrus_bitblt_rop_bkwd_src, 421 cirrus_bitblt_rop_bkwd_1, 422 cirrus_bitblt_rop_bkwd_notsrc_and_dst, 423 cirrus_bitblt_rop_bkwd_src_xor_dst, 424 cirrus_bitblt_rop_bkwd_src_or_dst, 425 cirrus_bitblt_rop_bkwd_notsrc_or_notdst, 426 cirrus_bitblt_rop_bkwd_src_notxor_dst, 427 cirrus_bitblt_rop_bkwd_src_or_notdst, 428 cirrus_bitblt_rop_bkwd_notsrc, 429 cirrus_bitblt_rop_bkwd_notsrc_or_dst, 430 cirrus_bitblt_rop_bkwd_notsrc_and_notdst, 431 }; 432 433 #define TRANSP_ROP(name) {\ 434 name ## _8,\ 435 name ## _16,\ 436 } 437 #define TRANSP_NOP(func) {\ 438 func,\ 439 func,\ 440 } 441 442 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = { 443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0), 444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst), 445 TRANSP_NOP(cirrus_bitblt_rop_nop), 446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst), 447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst), 448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src), 449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1), 450 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst), 451 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst), 452 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst), 453 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst), 454 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst), 455 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst), 456 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc), 457 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst), 458 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst), 459 }; 460 461 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = { 462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0), 463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst), 464 TRANSP_NOP(cirrus_bitblt_rop_nop), 465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst), 466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst), 467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src), 468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1), 469 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst), 470 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst), 471 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst), 472 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst), 473 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst), 474 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst), 475 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc), 476 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst), 477 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst), 478 }; 479 480 #define ROP2(name) {\ 481 name ## _8,\ 482 name ## _16,\ 483 name ## _24,\ 484 name ## _32,\ 485 } 486 487 #define ROP_NOP2(func) {\ 488 func,\ 489 func,\ 490 func,\ 491 func,\ 492 } 493 494 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = { 495 ROP2(cirrus_patternfill_0), 496 ROP2(cirrus_patternfill_src_and_dst), 497 ROP_NOP2(cirrus_bitblt_rop_nop), 498 ROP2(cirrus_patternfill_src_and_notdst), 499 ROP2(cirrus_patternfill_notdst), 500 ROP2(cirrus_patternfill_src), 501 ROP2(cirrus_patternfill_1), 502 ROP2(cirrus_patternfill_notsrc_and_dst), 503 ROP2(cirrus_patternfill_src_xor_dst), 504 ROP2(cirrus_patternfill_src_or_dst), 505 ROP2(cirrus_patternfill_notsrc_or_notdst), 506 ROP2(cirrus_patternfill_src_notxor_dst), 507 ROP2(cirrus_patternfill_src_or_notdst), 508 ROP2(cirrus_patternfill_notsrc), 509 ROP2(cirrus_patternfill_notsrc_or_dst), 510 ROP2(cirrus_patternfill_notsrc_and_notdst), 511 }; 512 513 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = { 514 ROP2(cirrus_colorexpand_transp_0), 515 ROP2(cirrus_colorexpand_transp_src_and_dst), 516 ROP_NOP2(cirrus_bitblt_rop_nop), 517 ROP2(cirrus_colorexpand_transp_src_and_notdst), 518 ROP2(cirrus_colorexpand_transp_notdst), 519 ROP2(cirrus_colorexpand_transp_src), 520 ROP2(cirrus_colorexpand_transp_1), 521 ROP2(cirrus_colorexpand_transp_notsrc_and_dst), 522 ROP2(cirrus_colorexpand_transp_src_xor_dst), 523 ROP2(cirrus_colorexpand_transp_src_or_dst), 524 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst), 525 ROP2(cirrus_colorexpand_transp_src_notxor_dst), 526 ROP2(cirrus_colorexpand_transp_src_or_notdst), 527 ROP2(cirrus_colorexpand_transp_notsrc), 528 ROP2(cirrus_colorexpand_transp_notsrc_or_dst), 529 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst), 530 }; 531 532 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = { 533 ROP2(cirrus_colorexpand_0), 534 ROP2(cirrus_colorexpand_src_and_dst), 535 ROP_NOP2(cirrus_bitblt_rop_nop), 536 ROP2(cirrus_colorexpand_src_and_notdst), 537 ROP2(cirrus_colorexpand_notdst), 538 ROP2(cirrus_colorexpand_src), 539 ROP2(cirrus_colorexpand_1), 540 ROP2(cirrus_colorexpand_notsrc_and_dst), 541 ROP2(cirrus_colorexpand_src_xor_dst), 542 ROP2(cirrus_colorexpand_src_or_dst), 543 ROP2(cirrus_colorexpand_notsrc_or_notdst), 544 ROP2(cirrus_colorexpand_src_notxor_dst), 545 ROP2(cirrus_colorexpand_src_or_notdst), 546 ROP2(cirrus_colorexpand_notsrc), 547 ROP2(cirrus_colorexpand_notsrc_or_dst), 548 ROP2(cirrus_colorexpand_notsrc_and_notdst), 549 }; 550 551 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = { 552 ROP2(cirrus_colorexpand_pattern_transp_0), 553 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst), 554 ROP_NOP2(cirrus_bitblt_rop_nop), 555 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst), 556 ROP2(cirrus_colorexpand_pattern_transp_notdst), 557 ROP2(cirrus_colorexpand_pattern_transp_src), 558 ROP2(cirrus_colorexpand_pattern_transp_1), 559 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst), 560 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst), 561 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst), 562 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst), 563 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst), 564 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst), 565 ROP2(cirrus_colorexpand_pattern_transp_notsrc), 566 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst), 567 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst), 568 }; 569 570 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = { 571 ROP2(cirrus_colorexpand_pattern_0), 572 ROP2(cirrus_colorexpand_pattern_src_and_dst), 573 ROP_NOP2(cirrus_bitblt_rop_nop), 574 ROP2(cirrus_colorexpand_pattern_src_and_notdst), 575 ROP2(cirrus_colorexpand_pattern_notdst), 576 ROP2(cirrus_colorexpand_pattern_src), 577 ROP2(cirrus_colorexpand_pattern_1), 578 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst), 579 ROP2(cirrus_colorexpand_pattern_src_xor_dst), 580 ROP2(cirrus_colorexpand_pattern_src_or_dst), 581 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst), 582 ROP2(cirrus_colorexpand_pattern_src_notxor_dst), 583 ROP2(cirrus_colorexpand_pattern_src_or_notdst), 584 ROP2(cirrus_colorexpand_pattern_notsrc), 585 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst), 586 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst), 587 }; 588 589 static const cirrus_fill_t cirrus_fill[16][4] = { 590 ROP2(cirrus_fill_0), 591 ROP2(cirrus_fill_src_and_dst), 592 ROP_NOP2(cirrus_bitblt_fill_nop), 593 ROP2(cirrus_fill_src_and_notdst), 594 ROP2(cirrus_fill_notdst), 595 ROP2(cirrus_fill_src), 596 ROP2(cirrus_fill_1), 597 ROP2(cirrus_fill_notsrc_and_dst), 598 ROP2(cirrus_fill_src_xor_dst), 599 ROP2(cirrus_fill_src_or_dst), 600 ROP2(cirrus_fill_notsrc_or_notdst), 601 ROP2(cirrus_fill_src_notxor_dst), 602 ROP2(cirrus_fill_src_or_notdst), 603 ROP2(cirrus_fill_notsrc), 604 ROP2(cirrus_fill_notsrc_or_dst), 605 ROP2(cirrus_fill_notsrc_and_notdst), 606 }; 607 608 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s) 609 { 610 unsigned int color; 611 switch (s->cirrus_blt_pixelwidth) { 612 case 1: 613 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1; 614 break; 615 case 2: 616 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8); 617 s->cirrus_blt_fgcol = le16_to_cpu(color); 618 break; 619 case 3: 620 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 | 621 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16); 622 break; 623 default: 624 case 4: 625 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) | 626 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24); 627 s->cirrus_blt_fgcol = le32_to_cpu(color); 628 break; 629 } 630 } 631 632 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s) 633 { 634 unsigned int color; 635 switch (s->cirrus_blt_pixelwidth) { 636 case 1: 637 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0; 638 break; 639 case 2: 640 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8); 641 s->cirrus_blt_bgcol = le16_to_cpu(color); 642 break; 643 case 3: 644 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 | 645 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16); 646 break; 647 default: 648 case 4: 649 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) | 650 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24); 651 s->cirrus_blt_bgcol = le32_to_cpu(color); 652 break; 653 } 654 } 655 656 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin, 657 int off_pitch, int bytesperline, 658 int lines) 659 { 660 int y; 661 int off_cur; 662 int off_cur_end; 663 664 if (off_pitch < 0) { 665 off_begin -= bytesperline - 1; 666 } 667 668 for (y = 0; y < lines; y++) { 669 off_cur = off_begin; 670 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask; 671 assert(off_cur_end >= off_cur); 672 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur); 673 off_begin += off_pitch; 674 } 675 } 676 677 static int cirrus_bitblt_common_patterncopy(CirrusVGAState *s, bool videosrc) 678 { 679 uint32_t patternsize; 680 uint8_t *dst; 681 uint8_t *src; 682 683 dst = s->vga.vram_ptr + s->cirrus_blt_dstaddr; 684 685 if (videosrc) { 686 switch (s->vga.get_bpp(&s->vga)) { 687 case 8: 688 patternsize = 64; 689 break; 690 case 15: 691 case 16: 692 patternsize = 128; 693 break; 694 case 24: 695 case 32: 696 default: 697 patternsize = 256; 698 break; 699 } 700 s->cirrus_blt_srcaddr &= ~(patternsize - 1); 701 if (s->cirrus_blt_srcaddr + patternsize > s->vga.vram_size) { 702 return 0; 703 } 704 src = s->vga.vram_ptr + s->cirrus_blt_srcaddr; 705 } else { 706 src = s->cirrus_bltbuf; 707 } 708 709 if (blit_is_unsafe(s, true)) { 710 return 0; 711 } 712 713 (*s->cirrus_rop) (s, dst, src, 714 s->cirrus_blt_dstpitch, 0, 715 s->cirrus_blt_width, s->cirrus_blt_height); 716 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 717 s->cirrus_blt_dstpitch, s->cirrus_blt_width, 718 s->cirrus_blt_height); 719 return 1; 720 } 721 722 /* fill */ 723 724 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop) 725 { 726 cirrus_fill_t rop_func; 727 728 if (blit_is_unsafe(s, true)) { 729 return 0; 730 } 731 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 732 rop_func(s, s->vga.vram_ptr + s->cirrus_blt_dstaddr, 733 s->cirrus_blt_dstpitch, 734 s->cirrus_blt_width, s->cirrus_blt_height); 735 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 736 s->cirrus_blt_dstpitch, s->cirrus_blt_width, 737 s->cirrus_blt_height); 738 cirrus_bitblt_reset(s); 739 return 1; 740 } 741 742 /*************************************** 743 * 744 * bitblt (video-to-video) 745 * 746 ***************************************/ 747 748 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s) 749 { 750 return cirrus_bitblt_common_patterncopy(s, true); 751 } 752 753 static int cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h) 754 { 755 int sx = 0, sy = 0; 756 int dx = 0, dy = 0; 757 int depth = 0; 758 int notify = 0; 759 760 /* make sure to only copy if it's a plain copy ROP */ 761 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src || 762 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) { 763 764 int width, height; 765 766 depth = s->vga.get_bpp(&s->vga) / 8; 767 if (!depth) { 768 return 0; 769 } 770 s->vga.get_resolution(&s->vga, &width, &height); 771 772 /* extra x, y */ 773 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth; 774 sy = (src / ABS(s->cirrus_blt_srcpitch)); 775 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth; 776 dy = (dst / ABS(s->cirrus_blt_dstpitch)); 777 778 /* normalize width */ 779 w /= depth; 780 781 /* if we're doing a backward copy, we have to adjust 782 our x/y to be the upper left corner (instead of the lower 783 right corner) */ 784 if (s->cirrus_blt_dstpitch < 0) { 785 sx -= (s->cirrus_blt_width / depth) - 1; 786 dx -= (s->cirrus_blt_width / depth) - 1; 787 sy -= s->cirrus_blt_height - 1; 788 dy -= s->cirrus_blt_height - 1; 789 } 790 791 /* are we in the visible portion of memory? */ 792 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 && 793 (sx + w) <= width && (sy + h) <= height && 794 (dx + w) <= width && (dy + h) <= height) { 795 notify = 1; 796 } 797 } 798 799 /* we have to flush all pending changes so that the copy 800 is generated at the appropriate moment in time */ 801 if (notify) 802 graphic_hw_update(s->vga.con); 803 804 (*s->cirrus_rop) (s, s->vga.vram_ptr + s->cirrus_blt_dstaddr, 805 s->vga.vram_ptr + s->cirrus_blt_srcaddr, 806 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch, 807 s->cirrus_blt_width, s->cirrus_blt_height); 808 809 if (notify) { 810 qemu_console_copy(s->vga.con, 811 sx, sy, dx, dy, 812 s->cirrus_blt_width / depth, 813 s->cirrus_blt_height); 814 } 815 816 /* we don't have to notify the display that this portion has 817 changed since qemu_console_copy implies this */ 818 819 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 820 s->cirrus_blt_dstpitch, s->cirrus_blt_width, 821 s->cirrus_blt_height); 822 823 return 1; 824 } 825 826 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s) 827 { 828 if (blit_is_unsafe(s, false)) 829 return 0; 830 831 return cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr, 832 s->cirrus_blt_srcaddr - s->vga.start_addr, 833 s->cirrus_blt_width, s->cirrus_blt_height); 834 } 835 836 /*************************************** 837 * 838 * bitblt (cpu-to-video) 839 * 840 ***************************************/ 841 842 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s) 843 { 844 int copy_count; 845 uint8_t *end_ptr; 846 847 if (s->cirrus_srccounter > 0) { 848 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { 849 cirrus_bitblt_common_patterncopy(s, false); 850 the_end: 851 s->cirrus_srccounter = 0; 852 cirrus_bitblt_reset(s); 853 } else { 854 /* at least one scan line */ 855 do { 856 (*s->cirrus_rop)(s, s->vga.vram_ptr + s->cirrus_blt_dstaddr, 857 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1); 858 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0, 859 s->cirrus_blt_width, 1); 860 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch; 861 s->cirrus_srccounter -= s->cirrus_blt_srcpitch; 862 if (s->cirrus_srccounter <= 0) 863 goto the_end; 864 /* more bytes than needed can be transferred because of 865 word alignment, so we keep them for the next line */ 866 /* XXX: keep alignment to speed up transfer */ 867 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; 868 copy_count = s->cirrus_srcptr_end - end_ptr; 869 memmove(s->cirrus_bltbuf, end_ptr, copy_count); 870 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count; 871 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; 872 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end); 873 } 874 } 875 } 876 877 /*************************************** 878 * 879 * bitblt wrapper 880 * 881 ***************************************/ 882 883 static void cirrus_bitblt_reset(CirrusVGAState * s) 884 { 885 int need_update; 886 887 s->vga.gr[0x31] &= 888 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED); 889 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0] 890 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0]; 891 s->cirrus_srcptr = &s->cirrus_bltbuf[0]; 892 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0]; 893 s->cirrus_srccounter = 0; 894 if (!need_update) 895 return; 896 cirrus_update_memory_access(s); 897 } 898 899 static int cirrus_bitblt_cputovideo(CirrusVGAState * s) 900 { 901 int w; 902 903 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC; 904 s->cirrus_srcptr = &s->cirrus_bltbuf[0]; 905 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0]; 906 907 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { 908 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) { 909 s->cirrus_blt_srcpitch = 8; 910 } else { 911 /* XXX: check for 24 bpp */ 912 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth; 913 } 914 s->cirrus_srccounter = s->cirrus_blt_srcpitch; 915 } else { 916 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) { 917 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth; 918 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY) 919 s->cirrus_blt_srcpitch = ((w + 31) >> 5); 920 else 921 s->cirrus_blt_srcpitch = ((w + 7) >> 3); 922 } else { 923 /* always align input size to 32 bits */ 924 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3; 925 } 926 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height; 927 } 928 s->cirrus_srcptr = s->cirrus_bltbuf; 929 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; 930 cirrus_update_memory_access(s); 931 return 1; 932 } 933 934 static int cirrus_bitblt_videotocpu(CirrusVGAState * s) 935 { 936 /* XXX */ 937 #ifdef DEBUG_BITBLT 938 printf("cirrus: bitblt (video to cpu) is not implemented yet\n"); 939 #endif 940 return 0; 941 } 942 943 static int cirrus_bitblt_videotovideo(CirrusVGAState * s) 944 { 945 int ret; 946 947 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { 948 ret = cirrus_bitblt_videotovideo_patterncopy(s); 949 } else { 950 ret = cirrus_bitblt_videotovideo_copy(s); 951 } 952 if (ret) 953 cirrus_bitblt_reset(s); 954 return ret; 955 } 956 957 static void cirrus_bitblt_start(CirrusVGAState * s) 958 { 959 uint8_t blt_rop; 960 961 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY; 962 963 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1; 964 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1; 965 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8)); 966 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8)); 967 s->cirrus_blt_dstaddr = 968 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16)); 969 s->cirrus_blt_srcaddr = 970 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16)); 971 s->cirrus_blt_mode = s->vga.gr[0x30]; 972 s->cirrus_blt_modeext = s->vga.gr[0x33]; 973 blt_rop = s->vga.gr[0x32]; 974 975 s->cirrus_blt_dstaddr &= s->cirrus_addr_mask; 976 s->cirrus_blt_srcaddr &= s->cirrus_addr_mask; 977 978 #ifdef DEBUG_BITBLT 979 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n", 980 blt_rop, 981 s->cirrus_blt_mode, 982 s->cirrus_blt_modeext, 983 s->cirrus_blt_width, 984 s->cirrus_blt_height, 985 s->cirrus_blt_dstpitch, 986 s->cirrus_blt_srcpitch, 987 s->cirrus_blt_dstaddr, 988 s->cirrus_blt_srcaddr, 989 s->vga.gr[0x2f]); 990 #endif 991 992 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) { 993 case CIRRUS_BLTMODE_PIXELWIDTH8: 994 s->cirrus_blt_pixelwidth = 1; 995 break; 996 case CIRRUS_BLTMODE_PIXELWIDTH16: 997 s->cirrus_blt_pixelwidth = 2; 998 break; 999 case CIRRUS_BLTMODE_PIXELWIDTH24: 1000 s->cirrus_blt_pixelwidth = 3; 1001 break; 1002 case CIRRUS_BLTMODE_PIXELWIDTH32: 1003 s->cirrus_blt_pixelwidth = 4; 1004 break; 1005 default: 1006 #ifdef DEBUG_BITBLT 1007 printf("cirrus: bitblt - pixel width is unknown\n"); 1008 #endif 1009 goto bitblt_ignore; 1010 } 1011 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK; 1012 1013 if ((s-> 1014 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC | 1015 CIRRUS_BLTMODE_MEMSYSDEST)) 1016 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) { 1017 #ifdef DEBUG_BITBLT 1018 printf("cirrus: bitblt - memory-to-memory copy is requested\n"); 1019 #endif 1020 goto bitblt_ignore; 1021 } 1022 1023 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) && 1024 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST | 1025 CIRRUS_BLTMODE_TRANSPARENTCOMP | 1026 CIRRUS_BLTMODE_PATTERNCOPY | 1027 CIRRUS_BLTMODE_COLOREXPAND)) == 1028 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) { 1029 cirrus_bitblt_fgcol(s); 1030 cirrus_bitblt_solidfill(s, blt_rop); 1031 } else { 1032 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND | 1033 CIRRUS_BLTMODE_PATTERNCOPY)) == 1034 CIRRUS_BLTMODE_COLOREXPAND) { 1035 1036 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) { 1037 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) 1038 cirrus_bitblt_bgcol(s); 1039 else 1040 cirrus_bitblt_fgcol(s); 1041 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 1042 } else { 1043 cirrus_bitblt_fgcol(s); 1044 cirrus_bitblt_bgcol(s); 1045 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 1046 } 1047 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { 1048 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) { 1049 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) { 1050 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) 1051 cirrus_bitblt_bgcol(s); 1052 else 1053 cirrus_bitblt_fgcol(s); 1054 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 1055 } else { 1056 cirrus_bitblt_fgcol(s); 1057 cirrus_bitblt_bgcol(s); 1058 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 1059 } 1060 } else { 1061 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 1062 } 1063 } else { 1064 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) { 1065 if (s->cirrus_blt_pixelwidth > 2) { 1066 printf("src transparent without colorexpand must be 8bpp or 16bpp\n"); 1067 goto bitblt_ignore; 1068 } 1069 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) { 1070 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; 1071 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; 1072 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 1073 } else { 1074 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 1075 } 1076 } else { 1077 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) { 1078 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; 1079 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; 1080 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]]; 1081 } else { 1082 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]]; 1083 } 1084 } 1085 } 1086 // setup bitblt engine. 1087 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) { 1088 if (!cirrus_bitblt_cputovideo(s)) 1089 goto bitblt_ignore; 1090 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) { 1091 if (!cirrus_bitblt_videotocpu(s)) 1092 goto bitblt_ignore; 1093 } else { 1094 if (!cirrus_bitblt_videotovideo(s)) 1095 goto bitblt_ignore; 1096 } 1097 } 1098 return; 1099 bitblt_ignore:; 1100 cirrus_bitblt_reset(s); 1101 } 1102 1103 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value) 1104 { 1105 unsigned old_value; 1106 1107 old_value = s->vga.gr[0x31]; 1108 s->vga.gr[0x31] = reg_value; 1109 1110 if (((old_value & CIRRUS_BLT_RESET) != 0) && 1111 ((reg_value & CIRRUS_BLT_RESET) == 0)) { 1112 cirrus_bitblt_reset(s); 1113 } else if (((old_value & CIRRUS_BLT_START) == 0) && 1114 ((reg_value & CIRRUS_BLT_START) != 0)) { 1115 cirrus_bitblt_start(s); 1116 } 1117 } 1118 1119 1120 /*************************************** 1121 * 1122 * basic parameters 1123 * 1124 ***************************************/ 1125 1126 static void cirrus_get_offsets(VGACommonState *s1, 1127 uint32_t *pline_offset, 1128 uint32_t *pstart_addr, 1129 uint32_t *pline_compare) 1130 { 1131 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga); 1132 uint32_t start_addr, line_offset, line_compare; 1133 1134 line_offset = s->vga.cr[0x13] 1135 | ((s->vga.cr[0x1b] & 0x10) << 4); 1136 line_offset <<= 3; 1137 *pline_offset = line_offset; 1138 1139 start_addr = (s->vga.cr[0x0c] << 8) 1140 | s->vga.cr[0x0d] 1141 | ((s->vga.cr[0x1b] & 0x01) << 16) 1142 | ((s->vga.cr[0x1b] & 0x0c) << 15) 1143 | ((s->vga.cr[0x1d] & 0x80) << 12); 1144 *pstart_addr = start_addr; 1145 1146 line_compare = s->vga.cr[0x18] | 1147 ((s->vga.cr[0x07] & 0x10) << 4) | 1148 ((s->vga.cr[0x09] & 0x40) << 3); 1149 *pline_compare = line_compare; 1150 } 1151 1152 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s) 1153 { 1154 uint32_t ret = 16; 1155 1156 switch (s->cirrus_hidden_dac_data & 0xf) { 1157 case 0: 1158 ret = 15; 1159 break; /* Sierra HiColor */ 1160 case 1: 1161 ret = 16; 1162 break; /* XGA HiColor */ 1163 default: 1164 #ifdef DEBUG_CIRRUS 1165 printf("cirrus: invalid DAC value %x in 16bpp\n", 1166 (s->cirrus_hidden_dac_data & 0xf)); 1167 #endif 1168 ret = 15; /* XXX */ 1169 break; 1170 } 1171 return ret; 1172 } 1173 1174 static int cirrus_get_bpp(VGACommonState *s1) 1175 { 1176 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga); 1177 uint32_t ret = 8; 1178 1179 if ((s->vga.sr[0x07] & 0x01) != 0) { 1180 /* Cirrus SVGA */ 1181 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) { 1182 case CIRRUS_SR7_BPP_8: 1183 ret = 8; 1184 break; 1185 case CIRRUS_SR7_BPP_16_DOUBLEVCLK: 1186 ret = cirrus_get_bpp16_depth(s); 1187 break; 1188 case CIRRUS_SR7_BPP_24: 1189 ret = 24; 1190 break; 1191 case CIRRUS_SR7_BPP_16: 1192 ret = cirrus_get_bpp16_depth(s); 1193 break; 1194 case CIRRUS_SR7_BPP_32: 1195 ret = 32; 1196 break; 1197 default: 1198 #ifdef DEBUG_CIRRUS 1199 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]); 1200 #endif 1201 ret = 8; 1202 break; 1203 } 1204 } else { 1205 /* VGA */ 1206 ret = 0; 1207 } 1208 1209 return ret; 1210 } 1211 1212 static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight) 1213 { 1214 int width, height; 1215 1216 width = (s->cr[0x01] + 1) * 8; 1217 height = s->cr[0x12] | 1218 ((s->cr[0x07] & 0x02) << 7) | 1219 ((s->cr[0x07] & 0x40) << 3); 1220 height = (height + 1); 1221 /* interlace support */ 1222 if (s->cr[0x1a] & 0x01) 1223 height = height * 2; 1224 *pwidth = width; 1225 *pheight = height; 1226 } 1227 1228 /*************************************** 1229 * 1230 * bank memory 1231 * 1232 ***************************************/ 1233 1234 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index) 1235 { 1236 unsigned offset; 1237 unsigned limit; 1238 1239 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */ 1240 offset = s->vga.gr[0x09 + bank_index]; 1241 else /* single bank */ 1242 offset = s->vga.gr[0x09]; 1243 1244 if ((s->vga.gr[0x0b] & 0x20) != 0) 1245 offset <<= 14; 1246 else 1247 offset <<= 12; 1248 1249 if (s->real_vram_size <= offset) 1250 limit = 0; 1251 else 1252 limit = s->real_vram_size - offset; 1253 1254 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) { 1255 if (limit > 0x8000) { 1256 offset += 0x8000; 1257 limit -= 0x8000; 1258 } else { 1259 limit = 0; 1260 } 1261 } 1262 1263 if (limit > 0) { 1264 s->cirrus_bank_base[bank_index] = offset; 1265 s->cirrus_bank_limit[bank_index] = limit; 1266 } else { 1267 s->cirrus_bank_base[bank_index] = 0; 1268 s->cirrus_bank_limit[bank_index] = 0; 1269 } 1270 } 1271 1272 /*************************************** 1273 * 1274 * I/O access between 0x3c4-0x3c5 1275 * 1276 ***************************************/ 1277 1278 static int cirrus_vga_read_sr(CirrusVGAState * s) 1279 { 1280 switch (s->vga.sr_index) { 1281 case 0x00: // Standard VGA 1282 case 0x01: // Standard VGA 1283 case 0x02: // Standard VGA 1284 case 0x03: // Standard VGA 1285 case 0x04: // Standard VGA 1286 return s->vga.sr[s->vga.sr_index]; 1287 case 0x06: // Unlock Cirrus extensions 1288 return s->vga.sr[s->vga.sr_index]; 1289 case 0x10: 1290 case 0x30: 1291 case 0x50: 1292 case 0x70: // Graphics Cursor X 1293 case 0x90: 1294 case 0xb0: 1295 case 0xd0: 1296 case 0xf0: // Graphics Cursor X 1297 return s->vga.sr[0x10]; 1298 case 0x11: 1299 case 0x31: 1300 case 0x51: 1301 case 0x71: // Graphics Cursor Y 1302 case 0x91: 1303 case 0xb1: 1304 case 0xd1: 1305 case 0xf1: // Graphics Cursor Y 1306 return s->vga.sr[0x11]; 1307 case 0x05: // ??? 1308 case 0x07: // Extended Sequencer Mode 1309 case 0x08: // EEPROM Control 1310 case 0x09: // Scratch Register 0 1311 case 0x0a: // Scratch Register 1 1312 case 0x0b: // VCLK 0 1313 case 0x0c: // VCLK 1 1314 case 0x0d: // VCLK 2 1315 case 0x0e: // VCLK 3 1316 case 0x0f: // DRAM Control 1317 case 0x12: // Graphics Cursor Attribute 1318 case 0x13: // Graphics Cursor Pattern Address 1319 case 0x14: // Scratch Register 2 1320 case 0x15: // Scratch Register 3 1321 case 0x16: // Performance Tuning Register 1322 case 0x17: // Configuration Readback and Extended Control 1323 case 0x18: // Signature Generator Control 1324 case 0x19: // Signal Generator Result 1325 case 0x1a: // Signal Generator Result 1326 case 0x1b: // VCLK 0 Denominator & Post 1327 case 0x1c: // VCLK 1 Denominator & Post 1328 case 0x1d: // VCLK 2 Denominator & Post 1329 case 0x1e: // VCLK 3 Denominator & Post 1330 case 0x1f: // BIOS Write Enable and MCLK select 1331 #ifdef DEBUG_CIRRUS 1332 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index); 1333 #endif 1334 return s->vga.sr[s->vga.sr_index]; 1335 default: 1336 #ifdef DEBUG_CIRRUS 1337 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index); 1338 #endif 1339 return 0xff; 1340 break; 1341 } 1342 } 1343 1344 static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val) 1345 { 1346 switch (s->vga.sr_index) { 1347 case 0x00: // Standard VGA 1348 case 0x01: // Standard VGA 1349 case 0x02: // Standard VGA 1350 case 0x03: // Standard VGA 1351 case 0x04: // Standard VGA 1352 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index]; 1353 if (s->vga.sr_index == 1) 1354 s->vga.update_retrace_info(&s->vga); 1355 break; 1356 case 0x06: // Unlock Cirrus extensions 1357 val &= 0x17; 1358 if (val == 0x12) { 1359 s->vga.sr[s->vga.sr_index] = 0x12; 1360 } else { 1361 s->vga.sr[s->vga.sr_index] = 0x0f; 1362 } 1363 break; 1364 case 0x10: 1365 case 0x30: 1366 case 0x50: 1367 case 0x70: // Graphics Cursor X 1368 case 0x90: 1369 case 0xb0: 1370 case 0xd0: 1371 case 0xf0: // Graphics Cursor X 1372 s->vga.sr[0x10] = val; 1373 s->vga.hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5); 1374 break; 1375 case 0x11: 1376 case 0x31: 1377 case 0x51: 1378 case 0x71: // Graphics Cursor Y 1379 case 0x91: 1380 case 0xb1: 1381 case 0xd1: 1382 case 0xf1: // Graphics Cursor Y 1383 s->vga.sr[0x11] = val; 1384 s->vga.hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5); 1385 break; 1386 case 0x07: // Extended Sequencer Mode 1387 cirrus_update_memory_access(s); 1388 case 0x08: // EEPROM Control 1389 case 0x09: // Scratch Register 0 1390 case 0x0a: // Scratch Register 1 1391 case 0x0b: // VCLK 0 1392 case 0x0c: // VCLK 1 1393 case 0x0d: // VCLK 2 1394 case 0x0e: // VCLK 3 1395 case 0x0f: // DRAM Control 1396 case 0x13: // Graphics Cursor Pattern Address 1397 case 0x14: // Scratch Register 2 1398 case 0x15: // Scratch Register 3 1399 case 0x16: // Performance Tuning Register 1400 case 0x18: // Signature Generator Control 1401 case 0x19: // Signature Generator Result 1402 case 0x1a: // Signature Generator Result 1403 case 0x1b: // VCLK 0 Denominator & Post 1404 case 0x1c: // VCLK 1 Denominator & Post 1405 case 0x1d: // VCLK 2 Denominator & Post 1406 case 0x1e: // VCLK 3 Denominator & Post 1407 case 0x1f: // BIOS Write Enable and MCLK select 1408 s->vga.sr[s->vga.sr_index] = val; 1409 #ifdef DEBUG_CIRRUS 1410 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n", 1411 s->vga.sr_index, val); 1412 #endif 1413 break; 1414 case 0x12: // Graphics Cursor Attribute 1415 s->vga.sr[0x12] = val; 1416 s->vga.force_shadow = !!(val & CIRRUS_CURSOR_SHOW); 1417 #ifdef DEBUG_CIRRUS 1418 printf("cirrus: cursor ctl SR12=%02x (force shadow: %d)\n", 1419 val, s->vga.force_shadow); 1420 #endif 1421 break; 1422 case 0x17: // Configuration Readback and Extended Control 1423 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38) 1424 | (val & 0xc7); 1425 cirrus_update_memory_access(s); 1426 break; 1427 default: 1428 #ifdef DEBUG_CIRRUS 1429 printf("cirrus: outport sr_index %02x, sr_value %02x\n", 1430 s->vga.sr_index, val); 1431 #endif 1432 break; 1433 } 1434 } 1435 1436 /*************************************** 1437 * 1438 * I/O access at 0x3c6 1439 * 1440 ***************************************/ 1441 1442 static int cirrus_read_hidden_dac(CirrusVGAState * s) 1443 { 1444 if (++s->cirrus_hidden_dac_lockindex == 5) { 1445 s->cirrus_hidden_dac_lockindex = 0; 1446 return s->cirrus_hidden_dac_data; 1447 } 1448 return 0xff; 1449 } 1450 1451 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value) 1452 { 1453 if (s->cirrus_hidden_dac_lockindex == 4) { 1454 s->cirrus_hidden_dac_data = reg_value; 1455 #if defined(DEBUG_CIRRUS) 1456 printf("cirrus: outport hidden DAC, value %02x\n", reg_value); 1457 #endif 1458 } 1459 s->cirrus_hidden_dac_lockindex = 0; 1460 } 1461 1462 /*************************************** 1463 * 1464 * I/O access at 0x3c9 1465 * 1466 ***************************************/ 1467 1468 static int cirrus_vga_read_palette(CirrusVGAState * s) 1469 { 1470 int val; 1471 1472 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { 1473 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 + 1474 s->vga.dac_sub_index]; 1475 } else { 1476 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index]; 1477 } 1478 if (++s->vga.dac_sub_index == 3) { 1479 s->vga.dac_sub_index = 0; 1480 s->vga.dac_read_index++; 1481 } 1482 return val; 1483 } 1484 1485 static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value) 1486 { 1487 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value; 1488 if (++s->vga.dac_sub_index == 3) { 1489 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { 1490 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3], 1491 s->vga.dac_cache, 3); 1492 } else { 1493 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3); 1494 } 1495 /* XXX update cursor */ 1496 s->vga.dac_sub_index = 0; 1497 s->vga.dac_write_index++; 1498 } 1499 } 1500 1501 /*************************************** 1502 * 1503 * I/O access between 0x3ce-0x3cf 1504 * 1505 ***************************************/ 1506 1507 static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index) 1508 { 1509 switch (reg_index) { 1510 case 0x00: // Standard VGA, BGCOLOR 0x000000ff 1511 return s->cirrus_shadow_gr0; 1512 case 0x01: // Standard VGA, FGCOLOR 0x000000ff 1513 return s->cirrus_shadow_gr1; 1514 case 0x02: // Standard VGA 1515 case 0x03: // Standard VGA 1516 case 0x04: // Standard VGA 1517 case 0x06: // Standard VGA 1518 case 0x07: // Standard VGA 1519 case 0x08: // Standard VGA 1520 return s->vga.gr[s->vga.gr_index]; 1521 case 0x05: // Standard VGA, Cirrus extended mode 1522 default: 1523 break; 1524 } 1525 1526 if (reg_index < 0x3a) { 1527 return s->vga.gr[reg_index]; 1528 } else { 1529 #ifdef DEBUG_CIRRUS 1530 printf("cirrus: inport gr_index %02x\n", reg_index); 1531 #endif 1532 return 0xff; 1533 } 1534 } 1535 1536 static void 1537 cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value) 1538 { 1539 #if defined(DEBUG_BITBLT) && 0 1540 printf("gr%02x: %02x\n", reg_index, reg_value); 1541 #endif 1542 switch (reg_index) { 1543 case 0x00: // Standard VGA, BGCOLOR 0x000000ff 1544 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; 1545 s->cirrus_shadow_gr0 = reg_value; 1546 break; 1547 case 0x01: // Standard VGA, FGCOLOR 0x000000ff 1548 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; 1549 s->cirrus_shadow_gr1 = reg_value; 1550 break; 1551 case 0x02: // Standard VGA 1552 case 0x03: // Standard VGA 1553 case 0x04: // Standard VGA 1554 case 0x06: // Standard VGA 1555 case 0x07: // Standard VGA 1556 case 0x08: // Standard VGA 1557 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; 1558 break; 1559 case 0x05: // Standard VGA, Cirrus extended mode 1560 s->vga.gr[reg_index] = reg_value & 0x7f; 1561 cirrus_update_memory_access(s); 1562 break; 1563 case 0x09: // bank offset #0 1564 case 0x0A: // bank offset #1 1565 s->vga.gr[reg_index] = reg_value; 1566 cirrus_update_bank_ptr(s, 0); 1567 cirrus_update_bank_ptr(s, 1); 1568 cirrus_update_memory_access(s); 1569 break; 1570 case 0x0B: 1571 s->vga.gr[reg_index] = reg_value; 1572 cirrus_update_bank_ptr(s, 0); 1573 cirrus_update_bank_ptr(s, 1); 1574 cirrus_update_memory_access(s); 1575 break; 1576 case 0x10: // BGCOLOR 0x0000ff00 1577 case 0x11: // FGCOLOR 0x0000ff00 1578 case 0x12: // BGCOLOR 0x00ff0000 1579 case 0x13: // FGCOLOR 0x00ff0000 1580 case 0x14: // BGCOLOR 0xff000000 1581 case 0x15: // FGCOLOR 0xff000000 1582 case 0x20: // BLT WIDTH 0x0000ff 1583 case 0x22: // BLT HEIGHT 0x0000ff 1584 case 0x24: // BLT DEST PITCH 0x0000ff 1585 case 0x26: // BLT SRC PITCH 0x0000ff 1586 case 0x28: // BLT DEST ADDR 0x0000ff 1587 case 0x29: // BLT DEST ADDR 0x00ff00 1588 case 0x2c: // BLT SRC ADDR 0x0000ff 1589 case 0x2d: // BLT SRC ADDR 0x00ff00 1590 case 0x2f: // BLT WRITEMASK 1591 case 0x30: // BLT MODE 1592 case 0x32: // RASTER OP 1593 case 0x33: // BLT MODEEXT 1594 case 0x34: // BLT TRANSPARENT COLOR 0x00ff 1595 case 0x35: // BLT TRANSPARENT COLOR 0xff00 1596 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff 1597 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00 1598 s->vga.gr[reg_index] = reg_value; 1599 break; 1600 case 0x21: // BLT WIDTH 0x001f00 1601 case 0x23: // BLT HEIGHT 0x001f00 1602 case 0x25: // BLT DEST PITCH 0x001f00 1603 case 0x27: // BLT SRC PITCH 0x001f00 1604 s->vga.gr[reg_index] = reg_value & 0x1f; 1605 break; 1606 case 0x2a: // BLT DEST ADDR 0x3f0000 1607 s->vga.gr[reg_index] = reg_value & 0x3f; 1608 /* if auto start mode, starts bit blt now */ 1609 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) { 1610 cirrus_bitblt_start(s); 1611 } 1612 break; 1613 case 0x2e: // BLT SRC ADDR 0x3f0000 1614 s->vga.gr[reg_index] = reg_value & 0x3f; 1615 break; 1616 case 0x31: // BLT STATUS/START 1617 cirrus_write_bitblt(s, reg_value); 1618 break; 1619 default: 1620 #ifdef DEBUG_CIRRUS 1621 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index, 1622 reg_value); 1623 #endif 1624 break; 1625 } 1626 } 1627 1628 /*************************************** 1629 * 1630 * I/O access between 0x3d4-0x3d5 1631 * 1632 ***************************************/ 1633 1634 static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index) 1635 { 1636 switch (reg_index) { 1637 case 0x00: // Standard VGA 1638 case 0x01: // Standard VGA 1639 case 0x02: // Standard VGA 1640 case 0x03: // Standard VGA 1641 case 0x04: // Standard VGA 1642 case 0x05: // Standard VGA 1643 case 0x06: // Standard VGA 1644 case 0x07: // Standard VGA 1645 case 0x08: // Standard VGA 1646 case 0x09: // Standard VGA 1647 case 0x0a: // Standard VGA 1648 case 0x0b: // Standard VGA 1649 case 0x0c: // Standard VGA 1650 case 0x0d: // Standard VGA 1651 case 0x0e: // Standard VGA 1652 case 0x0f: // Standard VGA 1653 case 0x10: // Standard VGA 1654 case 0x11: // Standard VGA 1655 case 0x12: // Standard VGA 1656 case 0x13: // Standard VGA 1657 case 0x14: // Standard VGA 1658 case 0x15: // Standard VGA 1659 case 0x16: // Standard VGA 1660 case 0x17: // Standard VGA 1661 case 0x18: // Standard VGA 1662 return s->vga.cr[s->vga.cr_index]; 1663 case 0x24: // Attribute Controller Toggle Readback (R) 1664 return (s->vga.ar_flip_flop << 7); 1665 case 0x19: // Interlace End 1666 case 0x1a: // Miscellaneous Control 1667 case 0x1b: // Extended Display Control 1668 case 0x1c: // Sync Adjust and Genlock 1669 case 0x1d: // Overlay Extended Control 1670 case 0x22: // Graphics Data Latches Readback (R) 1671 case 0x25: // Part Status 1672 case 0x27: // Part ID (R) 1673 return s->vga.cr[s->vga.cr_index]; 1674 case 0x26: // Attribute Controller Index Readback (R) 1675 return s->vga.ar_index & 0x3f; 1676 break; 1677 default: 1678 #ifdef DEBUG_CIRRUS 1679 printf("cirrus: inport cr_index %02x\n", reg_index); 1680 #endif 1681 return 0xff; 1682 } 1683 } 1684 1685 static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value) 1686 { 1687 switch (s->vga.cr_index) { 1688 case 0x00: // Standard VGA 1689 case 0x01: // Standard VGA 1690 case 0x02: // Standard VGA 1691 case 0x03: // Standard VGA 1692 case 0x04: // Standard VGA 1693 case 0x05: // Standard VGA 1694 case 0x06: // Standard VGA 1695 case 0x07: // Standard VGA 1696 case 0x08: // Standard VGA 1697 case 0x09: // Standard VGA 1698 case 0x0a: // Standard VGA 1699 case 0x0b: // Standard VGA 1700 case 0x0c: // Standard VGA 1701 case 0x0d: // Standard VGA 1702 case 0x0e: // Standard VGA 1703 case 0x0f: // Standard VGA 1704 case 0x10: // Standard VGA 1705 case 0x11: // Standard VGA 1706 case 0x12: // Standard VGA 1707 case 0x13: // Standard VGA 1708 case 0x14: // Standard VGA 1709 case 0x15: // Standard VGA 1710 case 0x16: // Standard VGA 1711 case 0x17: // Standard VGA 1712 case 0x18: // Standard VGA 1713 /* handle CR0-7 protection */ 1714 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) { 1715 /* can always write bit 4 of CR7 */ 1716 if (s->vga.cr_index == 7) 1717 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10); 1718 return; 1719 } 1720 s->vga.cr[s->vga.cr_index] = reg_value; 1721 switch(s->vga.cr_index) { 1722 case 0x00: 1723 case 0x04: 1724 case 0x05: 1725 case 0x06: 1726 case 0x07: 1727 case 0x11: 1728 case 0x17: 1729 s->vga.update_retrace_info(&s->vga); 1730 break; 1731 } 1732 break; 1733 case 0x19: // Interlace End 1734 case 0x1a: // Miscellaneous Control 1735 case 0x1b: // Extended Display Control 1736 case 0x1c: // Sync Adjust and Genlock 1737 case 0x1d: // Overlay Extended Control 1738 s->vga.cr[s->vga.cr_index] = reg_value; 1739 #ifdef DEBUG_CIRRUS 1740 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n", 1741 s->vga.cr_index, reg_value); 1742 #endif 1743 break; 1744 case 0x22: // Graphics Data Latches Readback (R) 1745 case 0x24: // Attribute Controller Toggle Readback (R) 1746 case 0x26: // Attribute Controller Index Readback (R) 1747 case 0x27: // Part ID (R) 1748 break; 1749 case 0x25: // Part Status 1750 default: 1751 #ifdef DEBUG_CIRRUS 1752 printf("cirrus: outport cr_index %02x, cr_value %02x\n", 1753 s->vga.cr_index, reg_value); 1754 #endif 1755 break; 1756 } 1757 } 1758 1759 /*************************************** 1760 * 1761 * memory-mapped I/O (bitblt) 1762 * 1763 ***************************************/ 1764 1765 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address) 1766 { 1767 int value = 0xff; 1768 1769 switch (address) { 1770 case (CIRRUS_MMIO_BLTBGCOLOR + 0): 1771 value = cirrus_vga_read_gr(s, 0x00); 1772 break; 1773 case (CIRRUS_MMIO_BLTBGCOLOR + 1): 1774 value = cirrus_vga_read_gr(s, 0x10); 1775 break; 1776 case (CIRRUS_MMIO_BLTBGCOLOR + 2): 1777 value = cirrus_vga_read_gr(s, 0x12); 1778 break; 1779 case (CIRRUS_MMIO_BLTBGCOLOR + 3): 1780 value = cirrus_vga_read_gr(s, 0x14); 1781 break; 1782 case (CIRRUS_MMIO_BLTFGCOLOR + 0): 1783 value = cirrus_vga_read_gr(s, 0x01); 1784 break; 1785 case (CIRRUS_MMIO_BLTFGCOLOR + 1): 1786 value = cirrus_vga_read_gr(s, 0x11); 1787 break; 1788 case (CIRRUS_MMIO_BLTFGCOLOR + 2): 1789 value = cirrus_vga_read_gr(s, 0x13); 1790 break; 1791 case (CIRRUS_MMIO_BLTFGCOLOR + 3): 1792 value = cirrus_vga_read_gr(s, 0x15); 1793 break; 1794 case (CIRRUS_MMIO_BLTWIDTH + 0): 1795 value = cirrus_vga_read_gr(s, 0x20); 1796 break; 1797 case (CIRRUS_MMIO_BLTWIDTH + 1): 1798 value = cirrus_vga_read_gr(s, 0x21); 1799 break; 1800 case (CIRRUS_MMIO_BLTHEIGHT + 0): 1801 value = cirrus_vga_read_gr(s, 0x22); 1802 break; 1803 case (CIRRUS_MMIO_BLTHEIGHT + 1): 1804 value = cirrus_vga_read_gr(s, 0x23); 1805 break; 1806 case (CIRRUS_MMIO_BLTDESTPITCH + 0): 1807 value = cirrus_vga_read_gr(s, 0x24); 1808 break; 1809 case (CIRRUS_MMIO_BLTDESTPITCH + 1): 1810 value = cirrus_vga_read_gr(s, 0x25); 1811 break; 1812 case (CIRRUS_MMIO_BLTSRCPITCH + 0): 1813 value = cirrus_vga_read_gr(s, 0x26); 1814 break; 1815 case (CIRRUS_MMIO_BLTSRCPITCH + 1): 1816 value = cirrus_vga_read_gr(s, 0x27); 1817 break; 1818 case (CIRRUS_MMIO_BLTDESTADDR + 0): 1819 value = cirrus_vga_read_gr(s, 0x28); 1820 break; 1821 case (CIRRUS_MMIO_BLTDESTADDR + 1): 1822 value = cirrus_vga_read_gr(s, 0x29); 1823 break; 1824 case (CIRRUS_MMIO_BLTDESTADDR + 2): 1825 value = cirrus_vga_read_gr(s, 0x2a); 1826 break; 1827 case (CIRRUS_MMIO_BLTSRCADDR + 0): 1828 value = cirrus_vga_read_gr(s, 0x2c); 1829 break; 1830 case (CIRRUS_MMIO_BLTSRCADDR + 1): 1831 value = cirrus_vga_read_gr(s, 0x2d); 1832 break; 1833 case (CIRRUS_MMIO_BLTSRCADDR + 2): 1834 value = cirrus_vga_read_gr(s, 0x2e); 1835 break; 1836 case CIRRUS_MMIO_BLTWRITEMASK: 1837 value = cirrus_vga_read_gr(s, 0x2f); 1838 break; 1839 case CIRRUS_MMIO_BLTMODE: 1840 value = cirrus_vga_read_gr(s, 0x30); 1841 break; 1842 case CIRRUS_MMIO_BLTROP: 1843 value = cirrus_vga_read_gr(s, 0x32); 1844 break; 1845 case CIRRUS_MMIO_BLTMODEEXT: 1846 value = cirrus_vga_read_gr(s, 0x33); 1847 break; 1848 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): 1849 value = cirrus_vga_read_gr(s, 0x34); 1850 break; 1851 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): 1852 value = cirrus_vga_read_gr(s, 0x35); 1853 break; 1854 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): 1855 value = cirrus_vga_read_gr(s, 0x38); 1856 break; 1857 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): 1858 value = cirrus_vga_read_gr(s, 0x39); 1859 break; 1860 case CIRRUS_MMIO_BLTSTATUS: 1861 value = cirrus_vga_read_gr(s, 0x31); 1862 break; 1863 default: 1864 #ifdef DEBUG_CIRRUS 1865 printf("cirrus: mmio read - address 0x%04x\n", address); 1866 #endif 1867 break; 1868 } 1869 1870 trace_vga_cirrus_write_blt(address, value); 1871 return (uint8_t) value; 1872 } 1873 1874 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address, 1875 uint8_t value) 1876 { 1877 trace_vga_cirrus_write_blt(address, value); 1878 switch (address) { 1879 case (CIRRUS_MMIO_BLTBGCOLOR + 0): 1880 cirrus_vga_write_gr(s, 0x00, value); 1881 break; 1882 case (CIRRUS_MMIO_BLTBGCOLOR + 1): 1883 cirrus_vga_write_gr(s, 0x10, value); 1884 break; 1885 case (CIRRUS_MMIO_BLTBGCOLOR + 2): 1886 cirrus_vga_write_gr(s, 0x12, value); 1887 break; 1888 case (CIRRUS_MMIO_BLTBGCOLOR + 3): 1889 cirrus_vga_write_gr(s, 0x14, value); 1890 break; 1891 case (CIRRUS_MMIO_BLTFGCOLOR + 0): 1892 cirrus_vga_write_gr(s, 0x01, value); 1893 break; 1894 case (CIRRUS_MMIO_BLTFGCOLOR + 1): 1895 cirrus_vga_write_gr(s, 0x11, value); 1896 break; 1897 case (CIRRUS_MMIO_BLTFGCOLOR + 2): 1898 cirrus_vga_write_gr(s, 0x13, value); 1899 break; 1900 case (CIRRUS_MMIO_BLTFGCOLOR + 3): 1901 cirrus_vga_write_gr(s, 0x15, value); 1902 break; 1903 case (CIRRUS_MMIO_BLTWIDTH + 0): 1904 cirrus_vga_write_gr(s, 0x20, value); 1905 break; 1906 case (CIRRUS_MMIO_BLTWIDTH + 1): 1907 cirrus_vga_write_gr(s, 0x21, value); 1908 break; 1909 case (CIRRUS_MMIO_BLTHEIGHT + 0): 1910 cirrus_vga_write_gr(s, 0x22, value); 1911 break; 1912 case (CIRRUS_MMIO_BLTHEIGHT + 1): 1913 cirrus_vga_write_gr(s, 0x23, value); 1914 break; 1915 case (CIRRUS_MMIO_BLTDESTPITCH + 0): 1916 cirrus_vga_write_gr(s, 0x24, value); 1917 break; 1918 case (CIRRUS_MMIO_BLTDESTPITCH + 1): 1919 cirrus_vga_write_gr(s, 0x25, value); 1920 break; 1921 case (CIRRUS_MMIO_BLTSRCPITCH + 0): 1922 cirrus_vga_write_gr(s, 0x26, value); 1923 break; 1924 case (CIRRUS_MMIO_BLTSRCPITCH + 1): 1925 cirrus_vga_write_gr(s, 0x27, value); 1926 break; 1927 case (CIRRUS_MMIO_BLTDESTADDR + 0): 1928 cirrus_vga_write_gr(s, 0x28, value); 1929 break; 1930 case (CIRRUS_MMIO_BLTDESTADDR + 1): 1931 cirrus_vga_write_gr(s, 0x29, value); 1932 break; 1933 case (CIRRUS_MMIO_BLTDESTADDR + 2): 1934 cirrus_vga_write_gr(s, 0x2a, value); 1935 break; 1936 case (CIRRUS_MMIO_BLTDESTADDR + 3): 1937 /* ignored */ 1938 break; 1939 case (CIRRUS_MMIO_BLTSRCADDR + 0): 1940 cirrus_vga_write_gr(s, 0x2c, value); 1941 break; 1942 case (CIRRUS_MMIO_BLTSRCADDR + 1): 1943 cirrus_vga_write_gr(s, 0x2d, value); 1944 break; 1945 case (CIRRUS_MMIO_BLTSRCADDR + 2): 1946 cirrus_vga_write_gr(s, 0x2e, value); 1947 break; 1948 case CIRRUS_MMIO_BLTWRITEMASK: 1949 cirrus_vga_write_gr(s, 0x2f, value); 1950 break; 1951 case CIRRUS_MMIO_BLTMODE: 1952 cirrus_vga_write_gr(s, 0x30, value); 1953 break; 1954 case CIRRUS_MMIO_BLTROP: 1955 cirrus_vga_write_gr(s, 0x32, value); 1956 break; 1957 case CIRRUS_MMIO_BLTMODEEXT: 1958 cirrus_vga_write_gr(s, 0x33, value); 1959 break; 1960 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): 1961 cirrus_vga_write_gr(s, 0x34, value); 1962 break; 1963 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): 1964 cirrus_vga_write_gr(s, 0x35, value); 1965 break; 1966 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): 1967 cirrus_vga_write_gr(s, 0x38, value); 1968 break; 1969 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): 1970 cirrus_vga_write_gr(s, 0x39, value); 1971 break; 1972 case CIRRUS_MMIO_BLTSTATUS: 1973 cirrus_vga_write_gr(s, 0x31, value); 1974 break; 1975 default: 1976 #ifdef DEBUG_CIRRUS 1977 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n", 1978 address, value); 1979 #endif 1980 break; 1981 } 1982 } 1983 1984 /*************************************** 1985 * 1986 * write mode 4/5 1987 * 1988 ***************************************/ 1989 1990 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s, 1991 unsigned mode, 1992 unsigned offset, 1993 uint32_t mem_value) 1994 { 1995 int x; 1996 unsigned val = mem_value; 1997 uint8_t *dst; 1998 1999 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask); 2000 for (x = 0; x < 8; x++) { 2001 if (val & 0x80) { 2002 *dst = s->cirrus_shadow_gr1; 2003 } else if (mode == 5) { 2004 *dst = s->cirrus_shadow_gr0; 2005 } 2006 val <<= 1; 2007 dst++; 2008 } 2009 memory_region_set_dirty(&s->vga.vram, offset, 8); 2010 } 2011 2012 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, 2013 unsigned mode, 2014 unsigned offset, 2015 uint32_t mem_value) 2016 { 2017 int x; 2018 unsigned val = mem_value; 2019 uint8_t *dst; 2020 2021 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask); 2022 for (x = 0; x < 8; x++) { 2023 if (val & 0x80) { 2024 *dst = s->cirrus_shadow_gr1; 2025 *(dst + 1) = s->vga.gr[0x11]; 2026 } else if (mode == 5) { 2027 *dst = s->cirrus_shadow_gr0; 2028 *(dst + 1) = s->vga.gr[0x10]; 2029 } 2030 val <<= 1; 2031 dst += 2; 2032 } 2033 memory_region_set_dirty(&s->vga.vram, offset, 16); 2034 } 2035 2036 /*************************************** 2037 * 2038 * memory access between 0xa0000-0xbffff 2039 * 2040 ***************************************/ 2041 2042 static uint64_t cirrus_vga_mem_read(void *opaque, 2043 hwaddr addr, 2044 uint32_t size) 2045 { 2046 CirrusVGAState *s = opaque; 2047 unsigned bank_index; 2048 unsigned bank_offset; 2049 uint32_t val; 2050 2051 if ((s->vga.sr[0x07] & 0x01) == 0) { 2052 return vga_mem_readb(&s->vga, addr); 2053 } 2054 2055 if (addr < 0x10000) { 2056 /* XXX handle bitblt */ 2057 /* video memory */ 2058 bank_index = addr >> 15; 2059 bank_offset = addr & 0x7fff; 2060 if (bank_offset < s->cirrus_bank_limit[bank_index]) { 2061 bank_offset += s->cirrus_bank_base[bank_index]; 2062 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { 2063 bank_offset <<= 4; 2064 } else if (s->vga.gr[0x0B] & 0x02) { 2065 bank_offset <<= 3; 2066 } 2067 bank_offset &= s->cirrus_addr_mask; 2068 val = *(s->vga.vram_ptr + bank_offset); 2069 } else 2070 val = 0xff; 2071 } else if (addr >= 0x18000 && addr < 0x18100) { 2072 /* memory-mapped I/O */ 2073 val = 0xff; 2074 if ((s->vga.sr[0x17] & 0x44) == 0x04) { 2075 val = cirrus_mmio_blt_read(s, addr & 0xff); 2076 } 2077 } else { 2078 val = 0xff; 2079 #ifdef DEBUG_CIRRUS 2080 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr); 2081 #endif 2082 } 2083 return val; 2084 } 2085 2086 static void cirrus_vga_mem_write(void *opaque, 2087 hwaddr addr, 2088 uint64_t mem_value, 2089 uint32_t size) 2090 { 2091 CirrusVGAState *s = opaque; 2092 unsigned bank_index; 2093 unsigned bank_offset; 2094 unsigned mode; 2095 2096 if ((s->vga.sr[0x07] & 0x01) == 0) { 2097 vga_mem_writeb(&s->vga, addr, mem_value); 2098 return; 2099 } 2100 2101 if (addr < 0x10000) { 2102 if (s->cirrus_srcptr != s->cirrus_srcptr_end) { 2103 /* bitblt */ 2104 *s->cirrus_srcptr++ = (uint8_t) mem_value; 2105 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) { 2106 cirrus_bitblt_cputovideo_next(s); 2107 } 2108 } else { 2109 /* video memory */ 2110 bank_index = addr >> 15; 2111 bank_offset = addr & 0x7fff; 2112 if (bank_offset < s->cirrus_bank_limit[bank_index]) { 2113 bank_offset += s->cirrus_bank_base[bank_index]; 2114 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { 2115 bank_offset <<= 4; 2116 } else if (s->vga.gr[0x0B] & 0x02) { 2117 bank_offset <<= 3; 2118 } 2119 bank_offset &= s->cirrus_addr_mask; 2120 mode = s->vga.gr[0x05] & 0x7; 2121 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { 2122 *(s->vga.vram_ptr + bank_offset) = mem_value; 2123 memory_region_set_dirty(&s->vga.vram, bank_offset, 2124 sizeof(mem_value)); 2125 } else { 2126 if ((s->vga.gr[0x0B] & 0x14) != 0x14) { 2127 cirrus_mem_writeb_mode4and5_8bpp(s, mode, 2128 bank_offset, 2129 mem_value); 2130 } else { 2131 cirrus_mem_writeb_mode4and5_16bpp(s, mode, 2132 bank_offset, 2133 mem_value); 2134 } 2135 } 2136 } 2137 } 2138 } else if (addr >= 0x18000 && addr < 0x18100) { 2139 /* memory-mapped I/O */ 2140 if ((s->vga.sr[0x17] & 0x44) == 0x04) { 2141 cirrus_mmio_blt_write(s, addr & 0xff, mem_value); 2142 } 2143 } else { 2144 #ifdef DEBUG_CIRRUS 2145 printf("cirrus: mem_writeb " TARGET_FMT_plx " value 0x%02" PRIu64 "\n", addr, 2146 mem_value); 2147 #endif 2148 } 2149 } 2150 2151 static const MemoryRegionOps cirrus_vga_mem_ops = { 2152 .read = cirrus_vga_mem_read, 2153 .write = cirrus_vga_mem_write, 2154 .endianness = DEVICE_LITTLE_ENDIAN, 2155 .impl = { 2156 .min_access_size = 1, 2157 .max_access_size = 1, 2158 }, 2159 }; 2160 2161 /*************************************** 2162 * 2163 * hardware cursor 2164 * 2165 ***************************************/ 2166 2167 static inline void invalidate_cursor1(CirrusVGAState *s) 2168 { 2169 if (s->last_hw_cursor_size) { 2170 vga_invalidate_scanlines(&s->vga, 2171 s->last_hw_cursor_y + s->last_hw_cursor_y_start, 2172 s->last_hw_cursor_y + s->last_hw_cursor_y_end); 2173 } 2174 } 2175 2176 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s) 2177 { 2178 const uint8_t *src; 2179 uint32_t content; 2180 int y, y_min, y_max; 2181 2182 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024; 2183 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { 2184 src += (s->vga.sr[0x13] & 0x3c) * 256; 2185 y_min = 64; 2186 y_max = -1; 2187 for(y = 0; y < 64; y++) { 2188 content = ((uint32_t *)src)[0] | 2189 ((uint32_t *)src)[1] | 2190 ((uint32_t *)src)[2] | 2191 ((uint32_t *)src)[3]; 2192 if (content) { 2193 if (y < y_min) 2194 y_min = y; 2195 if (y > y_max) 2196 y_max = y; 2197 } 2198 src += 16; 2199 } 2200 } else { 2201 src += (s->vga.sr[0x13] & 0x3f) * 256; 2202 y_min = 32; 2203 y_max = -1; 2204 for(y = 0; y < 32; y++) { 2205 content = ((uint32_t *)src)[0] | 2206 ((uint32_t *)(src + 128))[0]; 2207 if (content) { 2208 if (y < y_min) 2209 y_min = y; 2210 if (y > y_max) 2211 y_max = y; 2212 } 2213 src += 4; 2214 } 2215 } 2216 if (y_min > y_max) { 2217 s->last_hw_cursor_y_start = 0; 2218 s->last_hw_cursor_y_end = 0; 2219 } else { 2220 s->last_hw_cursor_y_start = y_min; 2221 s->last_hw_cursor_y_end = y_max + 1; 2222 } 2223 } 2224 2225 /* NOTE: we do not currently handle the cursor bitmap change, so we 2226 update the cursor only if it moves. */ 2227 static void cirrus_cursor_invalidate(VGACommonState *s1) 2228 { 2229 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga); 2230 int size; 2231 2232 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) { 2233 size = 0; 2234 } else { 2235 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) 2236 size = 64; 2237 else 2238 size = 32; 2239 } 2240 /* invalidate last cursor and new cursor if any change */ 2241 if (s->last_hw_cursor_size != size || 2242 s->last_hw_cursor_x != s->vga.hw_cursor_x || 2243 s->last_hw_cursor_y != s->vga.hw_cursor_y) { 2244 2245 invalidate_cursor1(s); 2246 2247 s->last_hw_cursor_size = size; 2248 s->last_hw_cursor_x = s->vga.hw_cursor_x; 2249 s->last_hw_cursor_y = s->vga.hw_cursor_y; 2250 /* compute the real cursor min and max y */ 2251 cirrus_cursor_compute_yrange(s); 2252 invalidate_cursor1(s); 2253 } 2254 } 2255 2256 static void vga_draw_cursor_line(uint8_t *d1, 2257 const uint8_t *src1, 2258 int poffset, int w, 2259 unsigned int color0, 2260 unsigned int color1, 2261 unsigned int color_xor) 2262 { 2263 const uint8_t *plane0, *plane1; 2264 int x, b0, b1; 2265 uint8_t *d; 2266 2267 d = d1; 2268 plane0 = src1; 2269 plane1 = src1 + poffset; 2270 for (x = 0; x < w; x++) { 2271 b0 = (plane0[x >> 3] >> (7 - (x & 7))) & 1; 2272 b1 = (plane1[x >> 3] >> (7 - (x & 7))) & 1; 2273 switch (b0 | (b1 << 1)) { 2274 case 0: 2275 break; 2276 case 1: 2277 ((uint32_t *)d)[0] ^= color_xor; 2278 break; 2279 case 2: 2280 ((uint32_t *)d)[0] = color0; 2281 break; 2282 case 3: 2283 ((uint32_t *)d)[0] = color1; 2284 break; 2285 } 2286 d += 4; 2287 } 2288 } 2289 2290 static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y) 2291 { 2292 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga); 2293 int w, h, x1, x2, poffset; 2294 unsigned int color0, color1; 2295 const uint8_t *palette, *src; 2296 uint32_t content; 2297 2298 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) 2299 return; 2300 /* fast test to see if the cursor intersects with the scan line */ 2301 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { 2302 h = 64; 2303 } else { 2304 h = 32; 2305 } 2306 if (scr_y < s->vga.hw_cursor_y || 2307 scr_y >= (s->vga.hw_cursor_y + h)) { 2308 return; 2309 } 2310 2311 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024; 2312 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { 2313 src += (s->vga.sr[0x13] & 0x3c) * 256; 2314 src += (scr_y - s->vga.hw_cursor_y) * 16; 2315 poffset = 8; 2316 content = ((uint32_t *)src)[0] | 2317 ((uint32_t *)src)[1] | 2318 ((uint32_t *)src)[2] | 2319 ((uint32_t *)src)[3]; 2320 } else { 2321 src += (s->vga.sr[0x13] & 0x3f) * 256; 2322 src += (scr_y - s->vga.hw_cursor_y) * 4; 2323 2324 2325 poffset = 128; 2326 content = ((uint32_t *)src)[0] | 2327 ((uint32_t *)(src + 128))[0]; 2328 } 2329 /* if nothing to draw, no need to continue */ 2330 if (!content) 2331 return; 2332 w = h; 2333 2334 x1 = s->vga.hw_cursor_x; 2335 if (x1 >= s->vga.last_scr_width) 2336 return; 2337 x2 = s->vga.hw_cursor_x + w; 2338 if (x2 > s->vga.last_scr_width) 2339 x2 = s->vga.last_scr_width; 2340 w = x2 - x1; 2341 palette = s->cirrus_hidden_palette; 2342 color0 = rgb_to_pixel32(c6_to_8(palette[0x0 * 3]), 2343 c6_to_8(palette[0x0 * 3 + 1]), 2344 c6_to_8(palette[0x0 * 3 + 2])); 2345 color1 = rgb_to_pixel32(c6_to_8(palette[0xf * 3]), 2346 c6_to_8(palette[0xf * 3 + 1]), 2347 c6_to_8(palette[0xf * 3 + 2])); 2348 d1 += x1 * 4; 2349 vga_draw_cursor_line(d1, src, poffset, w, color0, color1, 0xffffff); 2350 } 2351 2352 /*************************************** 2353 * 2354 * LFB memory access 2355 * 2356 ***************************************/ 2357 2358 static uint64_t cirrus_linear_read(void *opaque, hwaddr addr, 2359 unsigned size) 2360 { 2361 CirrusVGAState *s = opaque; 2362 uint32_t ret; 2363 2364 addr &= s->cirrus_addr_mask; 2365 2366 if (((s->vga.sr[0x17] & 0x44) == 0x44) && 2367 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { 2368 /* memory-mapped I/O */ 2369 ret = cirrus_mmio_blt_read(s, addr & 0xff); 2370 } else if (0) { 2371 /* XXX handle bitblt */ 2372 ret = 0xff; 2373 } else { 2374 /* video memory */ 2375 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { 2376 addr <<= 4; 2377 } else if (s->vga.gr[0x0B] & 0x02) { 2378 addr <<= 3; 2379 } 2380 addr &= s->cirrus_addr_mask; 2381 ret = *(s->vga.vram_ptr + addr); 2382 } 2383 2384 return ret; 2385 } 2386 2387 static void cirrus_linear_write(void *opaque, hwaddr addr, 2388 uint64_t val, unsigned size) 2389 { 2390 CirrusVGAState *s = opaque; 2391 unsigned mode; 2392 2393 addr &= s->cirrus_addr_mask; 2394 2395 if (((s->vga.sr[0x17] & 0x44) == 0x44) && 2396 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { 2397 /* memory-mapped I/O */ 2398 cirrus_mmio_blt_write(s, addr & 0xff, val); 2399 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { 2400 /* bitblt */ 2401 *s->cirrus_srcptr++ = (uint8_t) val; 2402 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) { 2403 cirrus_bitblt_cputovideo_next(s); 2404 } 2405 } else { 2406 /* video memory */ 2407 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { 2408 addr <<= 4; 2409 } else if (s->vga.gr[0x0B] & 0x02) { 2410 addr <<= 3; 2411 } 2412 addr &= s->cirrus_addr_mask; 2413 2414 mode = s->vga.gr[0x05] & 0x7; 2415 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { 2416 *(s->vga.vram_ptr + addr) = (uint8_t) val; 2417 memory_region_set_dirty(&s->vga.vram, addr, 1); 2418 } else { 2419 if ((s->vga.gr[0x0B] & 0x14) != 0x14) { 2420 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val); 2421 } else { 2422 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val); 2423 } 2424 } 2425 } 2426 } 2427 2428 /*************************************** 2429 * 2430 * system to screen memory access 2431 * 2432 ***************************************/ 2433 2434 2435 static uint64_t cirrus_linear_bitblt_read(void *opaque, 2436 hwaddr addr, 2437 unsigned size) 2438 { 2439 CirrusVGAState *s = opaque; 2440 uint32_t ret; 2441 2442 /* XXX handle bitblt */ 2443 (void)s; 2444 ret = 0xff; 2445 return ret; 2446 } 2447 2448 static void cirrus_linear_bitblt_write(void *opaque, 2449 hwaddr addr, 2450 uint64_t val, 2451 unsigned size) 2452 { 2453 CirrusVGAState *s = opaque; 2454 2455 if (s->cirrus_srcptr != s->cirrus_srcptr_end) { 2456 /* bitblt */ 2457 *s->cirrus_srcptr++ = (uint8_t) val; 2458 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) { 2459 cirrus_bitblt_cputovideo_next(s); 2460 } 2461 } 2462 } 2463 2464 static const MemoryRegionOps cirrus_linear_bitblt_io_ops = { 2465 .read = cirrus_linear_bitblt_read, 2466 .write = cirrus_linear_bitblt_write, 2467 .endianness = DEVICE_LITTLE_ENDIAN, 2468 .impl = { 2469 .min_access_size = 1, 2470 .max_access_size = 1, 2471 }, 2472 }; 2473 2474 static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank) 2475 { 2476 MemoryRegion *mr = &s->cirrus_bank[bank]; 2477 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end) 2478 && !((s->vga.sr[0x07] & 0x01) == 0) 2479 && !((s->vga.gr[0x0B] & 0x14) == 0x14) 2480 && !(s->vga.gr[0x0B] & 0x02); 2481 2482 memory_region_set_enabled(mr, enabled); 2483 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]); 2484 } 2485 2486 static void map_linear_vram(CirrusVGAState *s) 2487 { 2488 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) { 2489 s->linear_vram = true; 2490 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1); 2491 } 2492 map_linear_vram_bank(s, 0); 2493 map_linear_vram_bank(s, 1); 2494 } 2495 2496 static void unmap_linear_vram(CirrusVGAState *s) 2497 { 2498 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) { 2499 s->linear_vram = false; 2500 memory_region_del_subregion(&s->pci_bar, &s->vga.vram); 2501 } 2502 memory_region_set_enabled(&s->cirrus_bank[0], false); 2503 memory_region_set_enabled(&s->cirrus_bank[1], false); 2504 } 2505 2506 /* Compute the memory access functions */ 2507 static void cirrus_update_memory_access(CirrusVGAState *s) 2508 { 2509 unsigned mode; 2510 2511 memory_region_transaction_begin(); 2512 if ((s->vga.sr[0x17] & 0x44) == 0x44) { 2513 goto generic_io; 2514 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { 2515 goto generic_io; 2516 } else { 2517 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { 2518 goto generic_io; 2519 } else if (s->vga.gr[0x0B] & 0x02) { 2520 goto generic_io; 2521 } 2522 2523 mode = s->vga.gr[0x05] & 0x7; 2524 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { 2525 map_linear_vram(s); 2526 } else { 2527 generic_io: 2528 unmap_linear_vram(s); 2529 } 2530 } 2531 memory_region_transaction_commit(); 2532 } 2533 2534 2535 /* I/O ports */ 2536 2537 static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr, 2538 unsigned size) 2539 { 2540 CirrusVGAState *c = opaque; 2541 VGACommonState *s = &c->vga; 2542 int val, index; 2543 2544 addr += 0x3b0; 2545 2546 if (vga_ioport_invalid(s, addr)) { 2547 val = 0xff; 2548 } else { 2549 switch (addr) { 2550 case 0x3c0: 2551 if (s->ar_flip_flop == 0) { 2552 val = s->ar_index; 2553 } else { 2554 val = 0; 2555 } 2556 break; 2557 case 0x3c1: 2558 index = s->ar_index & 0x1f; 2559 if (index < 21) 2560 val = s->ar[index]; 2561 else 2562 val = 0; 2563 break; 2564 case 0x3c2: 2565 val = s->st00; 2566 break; 2567 case 0x3c4: 2568 val = s->sr_index; 2569 break; 2570 case 0x3c5: 2571 val = cirrus_vga_read_sr(c); 2572 break; 2573 #ifdef DEBUG_VGA_REG 2574 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val); 2575 #endif 2576 break; 2577 case 0x3c6: 2578 val = cirrus_read_hidden_dac(c); 2579 break; 2580 case 0x3c7: 2581 val = s->dac_state; 2582 break; 2583 case 0x3c8: 2584 val = s->dac_write_index; 2585 c->cirrus_hidden_dac_lockindex = 0; 2586 break; 2587 case 0x3c9: 2588 val = cirrus_vga_read_palette(c); 2589 break; 2590 case 0x3ca: 2591 val = s->fcr; 2592 break; 2593 case 0x3cc: 2594 val = s->msr; 2595 break; 2596 case 0x3ce: 2597 val = s->gr_index; 2598 break; 2599 case 0x3cf: 2600 val = cirrus_vga_read_gr(c, s->gr_index); 2601 #ifdef DEBUG_VGA_REG 2602 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val); 2603 #endif 2604 break; 2605 case 0x3b4: 2606 case 0x3d4: 2607 val = s->cr_index; 2608 break; 2609 case 0x3b5: 2610 case 0x3d5: 2611 val = cirrus_vga_read_cr(c, s->cr_index); 2612 #ifdef DEBUG_VGA_REG 2613 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val); 2614 #endif 2615 break; 2616 case 0x3ba: 2617 case 0x3da: 2618 /* just toggle to fool polling */ 2619 val = s->st01 = s->retrace(s); 2620 s->ar_flip_flop = 0; 2621 break; 2622 default: 2623 val = 0x00; 2624 break; 2625 } 2626 } 2627 trace_vga_cirrus_read_io(addr, val); 2628 return val; 2629 } 2630 2631 static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val, 2632 unsigned size) 2633 { 2634 CirrusVGAState *c = opaque; 2635 VGACommonState *s = &c->vga; 2636 int index; 2637 2638 addr += 0x3b0; 2639 2640 /* check port range access depending on color/monochrome mode */ 2641 if (vga_ioport_invalid(s, addr)) { 2642 return; 2643 } 2644 trace_vga_cirrus_write_io(addr, val); 2645 2646 switch (addr) { 2647 case 0x3c0: 2648 if (s->ar_flip_flop == 0) { 2649 val &= 0x3f; 2650 s->ar_index = val; 2651 } else { 2652 index = s->ar_index & 0x1f; 2653 switch (index) { 2654 case 0x00 ... 0x0f: 2655 s->ar[index] = val & 0x3f; 2656 break; 2657 case 0x10: 2658 s->ar[index] = val & ~0x10; 2659 break; 2660 case 0x11: 2661 s->ar[index] = val; 2662 break; 2663 case 0x12: 2664 s->ar[index] = val & ~0xc0; 2665 break; 2666 case 0x13: 2667 s->ar[index] = val & ~0xf0; 2668 break; 2669 case 0x14: 2670 s->ar[index] = val & ~0xf0; 2671 break; 2672 default: 2673 break; 2674 } 2675 } 2676 s->ar_flip_flop ^= 1; 2677 break; 2678 case 0x3c2: 2679 s->msr = val & ~0x10; 2680 s->update_retrace_info(s); 2681 break; 2682 case 0x3c4: 2683 s->sr_index = val; 2684 break; 2685 case 0x3c5: 2686 #ifdef DEBUG_VGA_REG 2687 printf("vga: write SR%x = 0x%02" PRIu64 "\n", s->sr_index, val); 2688 #endif 2689 cirrus_vga_write_sr(c, val); 2690 break; 2691 case 0x3c6: 2692 cirrus_write_hidden_dac(c, val); 2693 break; 2694 case 0x3c7: 2695 s->dac_read_index = val; 2696 s->dac_sub_index = 0; 2697 s->dac_state = 3; 2698 break; 2699 case 0x3c8: 2700 s->dac_write_index = val; 2701 s->dac_sub_index = 0; 2702 s->dac_state = 0; 2703 break; 2704 case 0x3c9: 2705 cirrus_vga_write_palette(c, val); 2706 break; 2707 case 0x3ce: 2708 s->gr_index = val; 2709 break; 2710 case 0x3cf: 2711 #ifdef DEBUG_VGA_REG 2712 printf("vga: write GR%x = 0x%02" PRIu64 "\n", s->gr_index, val); 2713 #endif 2714 cirrus_vga_write_gr(c, s->gr_index, val); 2715 break; 2716 case 0x3b4: 2717 case 0x3d4: 2718 s->cr_index = val; 2719 break; 2720 case 0x3b5: 2721 case 0x3d5: 2722 #ifdef DEBUG_VGA_REG 2723 printf("vga: write CR%x = 0x%02"PRIu64"\n", s->cr_index, val); 2724 #endif 2725 cirrus_vga_write_cr(c, val); 2726 break; 2727 case 0x3ba: 2728 case 0x3da: 2729 s->fcr = val & 0x10; 2730 break; 2731 } 2732 } 2733 2734 /*************************************** 2735 * 2736 * memory-mapped I/O access 2737 * 2738 ***************************************/ 2739 2740 static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr, 2741 unsigned size) 2742 { 2743 CirrusVGAState *s = opaque; 2744 2745 if (addr >= 0x100) { 2746 return cirrus_mmio_blt_read(s, addr - 0x100); 2747 } else { 2748 return cirrus_vga_ioport_read(s, addr + 0x10, size); 2749 } 2750 } 2751 2752 static void cirrus_mmio_write(void *opaque, hwaddr addr, 2753 uint64_t val, unsigned size) 2754 { 2755 CirrusVGAState *s = opaque; 2756 2757 if (addr >= 0x100) { 2758 cirrus_mmio_blt_write(s, addr - 0x100, val); 2759 } else { 2760 cirrus_vga_ioport_write(s, addr + 0x10, val, size); 2761 } 2762 } 2763 2764 static const MemoryRegionOps cirrus_mmio_io_ops = { 2765 .read = cirrus_mmio_read, 2766 .write = cirrus_mmio_write, 2767 .endianness = DEVICE_LITTLE_ENDIAN, 2768 .impl = { 2769 .min_access_size = 1, 2770 .max_access_size = 1, 2771 }, 2772 }; 2773 2774 /* load/save state */ 2775 2776 static int cirrus_post_load(void *opaque, int version_id) 2777 { 2778 CirrusVGAState *s = opaque; 2779 2780 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f; 2781 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f; 2782 2783 cirrus_update_memory_access(s); 2784 /* force refresh */ 2785 s->vga.graphic_mode = -1; 2786 cirrus_update_bank_ptr(s, 0); 2787 cirrus_update_bank_ptr(s, 1); 2788 return 0; 2789 } 2790 2791 static const VMStateDescription vmstate_cirrus_vga = { 2792 .name = "cirrus_vga", 2793 .version_id = 2, 2794 .minimum_version_id = 1, 2795 .post_load = cirrus_post_load, 2796 .fields = (VMStateField[]) { 2797 VMSTATE_UINT32(vga.latch, CirrusVGAState), 2798 VMSTATE_UINT8(vga.sr_index, CirrusVGAState), 2799 VMSTATE_BUFFER(vga.sr, CirrusVGAState), 2800 VMSTATE_UINT8(vga.gr_index, CirrusVGAState), 2801 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState), 2802 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState), 2803 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2), 2804 VMSTATE_UINT8(vga.ar_index, CirrusVGAState), 2805 VMSTATE_BUFFER(vga.ar, CirrusVGAState), 2806 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState), 2807 VMSTATE_UINT8(vga.cr_index, CirrusVGAState), 2808 VMSTATE_BUFFER(vga.cr, CirrusVGAState), 2809 VMSTATE_UINT8(vga.msr, CirrusVGAState), 2810 VMSTATE_UINT8(vga.fcr, CirrusVGAState), 2811 VMSTATE_UINT8(vga.st00, CirrusVGAState), 2812 VMSTATE_UINT8(vga.st01, CirrusVGAState), 2813 VMSTATE_UINT8(vga.dac_state, CirrusVGAState), 2814 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState), 2815 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState), 2816 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState), 2817 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState), 2818 VMSTATE_BUFFER(vga.palette, CirrusVGAState), 2819 VMSTATE_INT32(vga.bank_offset, CirrusVGAState), 2820 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState), 2821 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState), 2822 VMSTATE_UINT32(vga.hw_cursor_x, CirrusVGAState), 2823 VMSTATE_UINT32(vga.hw_cursor_y, CirrusVGAState), 2824 /* XXX: we do not save the bitblt state - we assume we do not save 2825 the state when the blitter is active */ 2826 VMSTATE_END_OF_LIST() 2827 } 2828 }; 2829 2830 static const VMStateDescription vmstate_pci_cirrus_vga = { 2831 .name = "cirrus_vga", 2832 .version_id = 2, 2833 .minimum_version_id = 2, 2834 .fields = (VMStateField[]) { 2835 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState), 2836 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0, 2837 vmstate_cirrus_vga, CirrusVGAState), 2838 VMSTATE_END_OF_LIST() 2839 } 2840 }; 2841 2842 /*************************************** 2843 * 2844 * initialize 2845 * 2846 ***************************************/ 2847 2848 static void cirrus_reset(void *opaque) 2849 { 2850 CirrusVGAState *s = opaque; 2851 2852 vga_common_reset(&s->vga); 2853 unmap_linear_vram(s); 2854 s->vga.sr[0x06] = 0x0f; 2855 if (s->device_id == CIRRUS_ID_CLGD5446) { 2856 /* 4MB 64 bit memory config, always PCI */ 2857 s->vga.sr[0x1F] = 0x2d; // MemClock 2858 s->vga.gr[0x18] = 0x0f; // fastest memory configuration 2859 s->vga.sr[0x0f] = 0x98; 2860 s->vga.sr[0x17] = 0x20; 2861 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */ 2862 } else { 2863 s->vga.sr[0x1F] = 0x22; // MemClock 2864 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M; 2865 s->vga.sr[0x17] = s->bustype; 2866 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */ 2867 } 2868 s->vga.cr[0x27] = s->device_id; 2869 2870 s->cirrus_hidden_dac_lockindex = 5; 2871 s->cirrus_hidden_dac_data = 0; 2872 } 2873 2874 static const MemoryRegionOps cirrus_linear_io_ops = { 2875 .read = cirrus_linear_read, 2876 .write = cirrus_linear_write, 2877 .endianness = DEVICE_LITTLE_ENDIAN, 2878 .impl = { 2879 .min_access_size = 1, 2880 .max_access_size = 1, 2881 }, 2882 }; 2883 2884 static const MemoryRegionOps cirrus_vga_io_ops = { 2885 .read = cirrus_vga_ioport_read, 2886 .write = cirrus_vga_ioport_write, 2887 .endianness = DEVICE_LITTLE_ENDIAN, 2888 .impl = { 2889 .min_access_size = 1, 2890 .max_access_size = 1, 2891 }, 2892 }; 2893 2894 static void cirrus_init_common(CirrusVGAState *s, Object *owner, 2895 int device_id, int is_pci, 2896 MemoryRegion *system_memory, 2897 MemoryRegion *system_io) 2898 { 2899 int i; 2900 static int inited; 2901 2902 if (!inited) { 2903 inited = 1; 2904 for(i = 0;i < 256; i++) 2905 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */ 2906 rop_to_index[CIRRUS_ROP_0] = 0; 2907 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1; 2908 rop_to_index[CIRRUS_ROP_NOP] = 2; 2909 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3; 2910 rop_to_index[CIRRUS_ROP_NOTDST] = 4; 2911 rop_to_index[CIRRUS_ROP_SRC] = 5; 2912 rop_to_index[CIRRUS_ROP_1] = 6; 2913 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7; 2914 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8; 2915 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9; 2916 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10; 2917 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11; 2918 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12; 2919 rop_to_index[CIRRUS_ROP_NOTSRC] = 13; 2920 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14; 2921 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15; 2922 s->device_id = device_id; 2923 if (is_pci) 2924 s->bustype = CIRRUS_BUSTYPE_PCI; 2925 else 2926 s->bustype = CIRRUS_BUSTYPE_ISA; 2927 } 2928 2929 /* Register ioport 0x3b0 - 0x3df */ 2930 memory_region_init_io(&s->cirrus_vga_io, owner, &cirrus_vga_io_ops, s, 2931 "cirrus-io", 0x30); 2932 memory_region_set_flush_coalesced(&s->cirrus_vga_io); 2933 memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io); 2934 2935 memory_region_init(&s->low_mem_container, owner, 2936 "cirrus-lowmem-container", 2937 0x20000); 2938 2939 memory_region_init_io(&s->low_mem, owner, &cirrus_vga_mem_ops, s, 2940 "cirrus-low-memory", 0x20000); 2941 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem); 2942 for (i = 0; i < 2; ++i) { 2943 static const char *names[] = { "vga.bank0", "vga.bank1" }; 2944 MemoryRegion *bank = &s->cirrus_bank[i]; 2945 memory_region_init_alias(bank, owner, names[i], &s->vga.vram, 2946 0, 0x8000); 2947 memory_region_set_enabled(bank, false); 2948 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000, 2949 bank, 1); 2950 } 2951 memory_region_add_subregion_overlap(system_memory, 2952 0x000a0000, 2953 &s->low_mem_container, 2954 1); 2955 memory_region_set_coalescing(&s->low_mem); 2956 2957 /* I/O handler for LFB */ 2958 memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s, 2959 "cirrus-linear-io", s->vga.vram_size_mb 2960 * 1024 * 1024); 2961 memory_region_set_flush_coalesced(&s->cirrus_linear_io); 2962 2963 /* I/O handler for LFB */ 2964 memory_region_init_io(&s->cirrus_linear_bitblt_io, owner, 2965 &cirrus_linear_bitblt_io_ops, 2966 s, 2967 "cirrus-bitblt-mmio", 2968 0x400000); 2969 memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io); 2970 2971 /* I/O handler for memory-mapped I/O */ 2972 memory_region_init_io(&s->cirrus_mmio_io, owner, &cirrus_mmio_io_ops, s, 2973 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE); 2974 memory_region_set_flush_coalesced(&s->cirrus_mmio_io); 2975 2976 s->real_vram_size = 2977 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024; 2978 2979 /* XXX: s->vga.vram_size must be a power of two */ 2980 s->cirrus_addr_mask = s->real_vram_size - 1; 2981 s->linear_mmio_mask = s->real_vram_size - 256; 2982 2983 s->vga.get_bpp = cirrus_get_bpp; 2984 s->vga.get_offsets = cirrus_get_offsets; 2985 s->vga.get_resolution = cirrus_get_resolution; 2986 s->vga.cursor_invalidate = cirrus_cursor_invalidate; 2987 s->vga.cursor_draw_line = cirrus_cursor_draw_line; 2988 2989 qemu_register_reset(cirrus_reset, s); 2990 } 2991 2992 /*************************************** 2993 * 2994 * ISA bus support 2995 * 2996 ***************************************/ 2997 2998 static void isa_cirrus_vga_realizefn(DeviceState *dev, Error **errp) 2999 { 3000 ISADevice *isadev = ISA_DEVICE(dev); 3001 ISACirrusVGAState *d = ISA_CIRRUS_VGA(dev); 3002 VGACommonState *s = &d->cirrus_vga.vga; 3003 3004 /* follow real hardware, cirrus card emulated has 4 MB video memory. 3005 Also accept 8 MB/16 MB for backward compatibility. */ 3006 if (s->vram_size_mb != 4 && s->vram_size_mb != 8 && 3007 s->vram_size_mb != 16) { 3008 error_setg(errp, "Invalid cirrus_vga ram size '%u'", 3009 s->vram_size_mb); 3010 return; 3011 } 3012 vga_common_init(s, OBJECT(dev), true); 3013 cirrus_init_common(&d->cirrus_vga, OBJECT(dev), CIRRUS_ID_CLGD5430, 0, 3014 isa_address_space(isadev), 3015 isa_address_space_io(isadev)); 3016 s->con = graphic_console_init(dev, 0, s->hw_ops, s); 3017 rom_add_vga(VGABIOS_CIRRUS_FILENAME); 3018 /* XXX ISA-LFB support */ 3019 /* FIXME not qdev yet */ 3020 } 3021 3022 static Property isa_cirrus_vga_properties[] = { 3023 DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState, 3024 cirrus_vga.vga.vram_size_mb, 8), 3025 DEFINE_PROP_END_OF_LIST(), 3026 }; 3027 3028 static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data) 3029 { 3030 DeviceClass *dc = DEVICE_CLASS(klass); 3031 3032 dc->vmsd = &vmstate_cirrus_vga; 3033 dc->realize = isa_cirrus_vga_realizefn; 3034 dc->props = isa_cirrus_vga_properties; 3035 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 3036 } 3037 3038 static const TypeInfo isa_cirrus_vga_info = { 3039 .name = TYPE_ISA_CIRRUS_VGA, 3040 .parent = TYPE_ISA_DEVICE, 3041 .instance_size = sizeof(ISACirrusVGAState), 3042 .class_init = isa_cirrus_vga_class_init, 3043 }; 3044 3045 /*************************************** 3046 * 3047 * PCI bus support 3048 * 3049 ***************************************/ 3050 3051 static void pci_cirrus_vga_realize(PCIDevice *dev, Error **errp) 3052 { 3053 PCICirrusVGAState *d = PCI_CIRRUS_VGA(dev); 3054 CirrusVGAState *s = &d->cirrus_vga; 3055 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 3056 int16_t device_id = pc->device_id; 3057 3058 /* follow real hardware, cirrus card emulated has 4 MB video memory. 3059 Also accept 8 MB/16 MB for backward compatibility. */ 3060 if (s->vga.vram_size_mb != 4 && s->vga.vram_size_mb != 8 && 3061 s->vga.vram_size_mb != 16) { 3062 error_setg(errp, "Invalid cirrus_vga ram size '%u'", 3063 s->vga.vram_size_mb); 3064 return; 3065 } 3066 /* setup VGA */ 3067 vga_common_init(&s->vga, OBJECT(dev), true); 3068 cirrus_init_common(s, OBJECT(dev), device_id, 1, pci_address_space(dev), 3069 pci_address_space_io(dev)); 3070 s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga); 3071 3072 /* setup PCI */ 3073 3074 memory_region_init(&s->pci_bar, OBJECT(dev), "cirrus-pci-bar0", 0x2000000); 3075 3076 /* XXX: add byte swapping apertures */ 3077 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io); 3078 memory_region_add_subregion(&s->pci_bar, 0x1000000, 3079 &s->cirrus_linear_bitblt_io); 3080 3081 /* setup memory space */ 3082 /* memory #0 LFB */ 3083 /* memory #1 memory-mapped I/O */ 3084 /* XXX: s->vga.vram_size must be a power of two */ 3085 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar); 3086 if (device_id == CIRRUS_ID_CLGD5446) { 3087 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io); 3088 } 3089 } 3090 3091 static Property pci_vga_cirrus_properties[] = { 3092 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState, 3093 cirrus_vga.vga.vram_size_mb, 8), 3094 DEFINE_PROP_END_OF_LIST(), 3095 }; 3096 3097 static void cirrus_vga_class_init(ObjectClass *klass, void *data) 3098 { 3099 DeviceClass *dc = DEVICE_CLASS(klass); 3100 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3101 3102 k->realize = pci_cirrus_vga_realize; 3103 k->romfile = VGABIOS_CIRRUS_FILENAME; 3104 k->vendor_id = PCI_VENDOR_ID_CIRRUS; 3105 k->device_id = CIRRUS_ID_CLGD5446; 3106 k->class_id = PCI_CLASS_DISPLAY_VGA; 3107 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 3108 dc->desc = "Cirrus CLGD 54xx VGA"; 3109 dc->vmsd = &vmstate_pci_cirrus_vga; 3110 dc->props = pci_vga_cirrus_properties; 3111 dc->hotpluggable = false; 3112 } 3113 3114 static const TypeInfo cirrus_vga_info = { 3115 .name = TYPE_PCI_CIRRUS_VGA, 3116 .parent = TYPE_PCI_DEVICE, 3117 .instance_size = sizeof(PCICirrusVGAState), 3118 .class_init = cirrus_vga_class_init, 3119 }; 3120 3121 static void cirrus_vga_register_types(void) 3122 { 3123 type_register_static(&isa_cirrus_vga_info); 3124 type_register_static(&cirrus_vga_info); 3125 } 3126 3127 type_init(cirrus_vga_register_types) 3128