1 /* 2 * QEMU CG3 Frame buffer 3 * 4 * Copyright (c) 2012 Bob Breuer 5 * Copyright (c) 2013 Mark Cave-Ayland 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu-common.h" 28 #include "qemu/error-report.h" 29 #include "ui/console.h" 30 #include "hw/sysbus.h" 31 #include "hw/loader.h" 32 33 /* Change to 1 to enable debugging */ 34 #define DEBUG_CG3 0 35 36 #define CG3_ROM_FILE "QEMU,cgthree.bin" 37 #define FCODE_MAX_ROM_SIZE 0x10000 38 39 #define CG3_REG_SIZE 0x20 40 41 #define CG3_REG_BT458_ADDR 0x0 42 #define CG3_REG_BT458_COLMAP 0x4 43 #define CG3_REG_FBC_CTRL 0x10 44 #define CG3_REG_FBC_STATUS 0x11 45 #define CG3_REG_FBC_CURSTART 0x12 46 #define CG3_REG_FBC_CUREND 0x13 47 #define CG3_REG_FBC_VCTRL 0x14 48 49 /* Control register flags */ 50 #define CG3_CR_ENABLE_INTS 0x80 51 52 /* Status register flags */ 53 #define CG3_SR_PENDING_INT 0x80 54 #define CG3_SR_1152_900_76_B 0x60 55 #define CG3_SR_ID_COLOR 0x01 56 57 #define CG3_VRAM_SIZE 0x100000 58 #define CG3_VRAM_OFFSET 0x800000 59 60 #define DPRINTF(fmt, ...) do { \ 61 if (DEBUG_CG3) { \ 62 printf("CG3: " fmt , ## __VA_ARGS__); \ 63 } \ 64 } while (0); 65 66 #define TYPE_CG3 "cgthree" 67 #define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3) 68 69 typedef struct CG3State { 70 SysBusDevice parent_obj; 71 72 QemuConsole *con; 73 qemu_irq irq; 74 hwaddr prom_addr; 75 MemoryRegion vram_mem; 76 MemoryRegion rom; 77 MemoryRegion reg; 78 uint32_t vram_size; 79 int full_update; 80 uint8_t regs[16]; 81 uint8_t r[256], g[256], b[256]; 82 uint16_t width, height, depth; 83 uint8_t dac_index, dac_state; 84 } CG3State; 85 86 static void cg3_update_display(void *opaque) 87 { 88 CG3State *s = opaque; 89 DisplaySurface *surface = qemu_console_surface(s->con); 90 const uint8_t *pix; 91 uint32_t *data; 92 uint32_t dval; 93 int x, y, y_start; 94 unsigned int width, height; 95 ram_addr_t page, page_min, page_max; 96 97 if (surface_bits_per_pixel(surface) != 32) { 98 return; 99 } 100 width = s->width; 101 height = s->height; 102 103 y_start = -1; 104 page_min = -1; 105 page_max = 0; 106 page = 0; 107 pix = memory_region_get_ram_ptr(&s->vram_mem); 108 data = (uint32_t *)surface_data(surface); 109 110 memory_region_sync_dirty_bitmap(&s->vram_mem); 111 for (y = 0; y < height; y++) { 112 int update = s->full_update; 113 114 page = (y * width) & TARGET_PAGE_MASK; 115 update |= memory_region_get_dirty(&s->vram_mem, page, page + width, 116 DIRTY_MEMORY_VGA); 117 if (update) { 118 if (y_start < 0) { 119 y_start = y; 120 } 121 if (page < page_min) { 122 page_min = page; 123 } 124 if (page > page_max) { 125 page_max = page; 126 } 127 128 for (x = 0; x < width; x++) { 129 dval = *pix++; 130 dval = (s->r[dval] << 16) | (s->g[dval] << 8) | s->b[dval]; 131 *data++ = dval; 132 } 133 } else { 134 if (y_start >= 0) { 135 dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start); 136 y_start = -1; 137 } 138 pix += width; 139 data += width; 140 } 141 } 142 s->full_update = 0; 143 if (y_start >= 0) { 144 dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start); 145 } 146 if (page_max >= page_min) { 147 memory_region_reset_dirty(&s->vram_mem, 148 page_min, page_max - page_min + TARGET_PAGE_SIZE, 149 DIRTY_MEMORY_VGA); 150 } 151 /* vsync interrupt? */ 152 if (s->regs[0] & CG3_CR_ENABLE_INTS) { 153 s->regs[1] |= CG3_SR_PENDING_INT; 154 qemu_irq_raise(s->irq); 155 } 156 } 157 158 static void cg3_invalidate_display(void *opaque) 159 { 160 CG3State *s = opaque; 161 162 memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE); 163 } 164 165 static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size) 166 { 167 CG3State *s = opaque; 168 int val; 169 170 switch (addr) { 171 case CG3_REG_BT458_ADDR: 172 case CG3_REG_BT458_COLMAP: 173 val = 0; 174 break; 175 case CG3_REG_FBC_CTRL: 176 val = s->regs[0]; 177 break; 178 case CG3_REG_FBC_STATUS: 179 /* monitor ID 6, board type = 1 (color) */ 180 val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR; 181 break; 182 case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1: 183 val = s->regs[addr - 0x10]; 184 break; 185 default: 186 qemu_log_mask(LOG_UNIMP, 187 "cg3: Unimplemented register read " 188 "reg 0x%" HWADDR_PRIx " size 0x%x\n", 189 addr, size); 190 val = 0; 191 break; 192 } 193 DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", val, addr); 194 return val; 195 } 196 197 static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val, 198 unsigned size) 199 { 200 CG3State *s = opaque; 201 uint8_t regval; 202 int i; 203 204 DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " size %d\n", 205 val, addr, size); 206 207 switch (addr) { 208 case CG3_REG_BT458_ADDR: 209 s->dac_index = val; 210 s->dac_state = 0; 211 break; 212 case CG3_REG_BT458_COLMAP: 213 /* This register can be written to as either a long word or a byte */ 214 if (size == 1) { 215 val <<= 24; 216 } 217 218 for (i = 0; i < size; i++) { 219 regval = val >> 24; 220 221 switch (s->dac_state) { 222 case 0: 223 s->r[s->dac_index] = regval; 224 s->dac_state++; 225 break; 226 case 1: 227 s->g[s->dac_index] = regval; 228 s->dac_state++; 229 break; 230 case 2: 231 s->b[s->dac_index] = regval; 232 /* Index autoincrement */ 233 s->dac_index = (s->dac_index + 1) & 0xff; 234 default: 235 s->dac_state = 0; 236 break; 237 } 238 val <<= 8; 239 } 240 s->full_update = 1; 241 break; 242 case CG3_REG_FBC_CTRL: 243 s->regs[0] = val; 244 break; 245 case CG3_REG_FBC_STATUS: 246 if (s->regs[1] & CG3_SR_PENDING_INT) { 247 /* clear interrupt */ 248 s->regs[1] &= ~CG3_SR_PENDING_INT; 249 qemu_irq_lower(s->irq); 250 } 251 break; 252 case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1: 253 s->regs[addr - 0x10] = val; 254 break; 255 default: 256 qemu_log_mask(LOG_UNIMP, 257 "cg3: Unimplemented register write " 258 "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n", 259 addr, size, val); 260 break; 261 } 262 } 263 264 static const MemoryRegionOps cg3_reg_ops = { 265 .read = cg3_reg_read, 266 .write = cg3_reg_write, 267 .endianness = DEVICE_NATIVE_ENDIAN, 268 .valid = { 269 .min_access_size = 1, 270 .max_access_size = 4, 271 }, 272 }; 273 274 static const GraphicHwOps cg3_ops = { 275 .invalidate = cg3_invalidate_display, 276 .gfx_update = cg3_update_display, 277 }; 278 279 static void cg3_initfn(Object *obj) 280 { 281 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 282 CG3State *s = CG3(obj); 283 284 memory_region_init_ram(&s->rom, obj, "cg3.prom", FCODE_MAX_ROM_SIZE, 285 &error_fatal); 286 memory_region_set_readonly(&s->rom, true); 287 sysbus_init_mmio(sbd, &s->rom); 288 289 memory_region_init_io(&s->reg, obj, &cg3_reg_ops, s, "cg3.reg", 290 CG3_REG_SIZE); 291 sysbus_init_mmio(sbd, &s->reg); 292 } 293 294 static void cg3_realizefn(DeviceState *dev, Error **errp) 295 { 296 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 297 CG3State *s = CG3(dev); 298 int ret; 299 char *fcode_filename; 300 301 /* FCode ROM */ 302 vmstate_register_ram_global(&s->rom); 303 fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE); 304 if (fcode_filename) { 305 ret = load_image_targphys(fcode_filename, s->prom_addr, 306 FCODE_MAX_ROM_SIZE); 307 g_free(fcode_filename); 308 if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) { 309 error_report("cg3: could not load prom '%s'", CG3_ROM_FILE); 310 } 311 } 312 313 memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size, 314 &error_fatal); 315 memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA); 316 vmstate_register_ram_global(&s->vram_mem); 317 sysbus_init_mmio(sbd, &s->vram_mem); 318 319 sysbus_init_irq(sbd, &s->irq); 320 321 s->con = graphic_console_init(DEVICE(dev), 0, &cg3_ops, s); 322 qemu_console_resize(s->con, s->width, s->height); 323 } 324 325 static int vmstate_cg3_post_load(void *opaque, int version_id) 326 { 327 CG3State *s = opaque; 328 329 cg3_invalidate_display(s); 330 331 return 0; 332 } 333 334 static const VMStateDescription vmstate_cg3 = { 335 .name = "cg3", 336 .version_id = 1, 337 .minimum_version_id = 1, 338 .post_load = vmstate_cg3_post_load, 339 .fields = (VMStateField[]) { 340 VMSTATE_UINT16(height, CG3State), 341 VMSTATE_UINT16(width, CG3State), 342 VMSTATE_UINT16(depth, CG3State), 343 VMSTATE_BUFFER(r, CG3State), 344 VMSTATE_BUFFER(g, CG3State), 345 VMSTATE_BUFFER(b, CG3State), 346 VMSTATE_UINT8(dac_index, CG3State), 347 VMSTATE_UINT8(dac_state, CG3State), 348 VMSTATE_END_OF_LIST() 349 } 350 }; 351 352 static void cg3_reset(DeviceState *d) 353 { 354 CG3State *s = CG3(d); 355 356 /* Initialize palette */ 357 memset(s->r, 0, 256); 358 memset(s->g, 0, 256); 359 memset(s->b, 0, 256); 360 361 s->dac_state = 0; 362 s->full_update = 1; 363 qemu_irq_lower(s->irq); 364 } 365 366 static Property cg3_properties[] = { 367 DEFINE_PROP_UINT32("vram-size", CG3State, vram_size, -1), 368 DEFINE_PROP_UINT16("width", CG3State, width, -1), 369 DEFINE_PROP_UINT16("height", CG3State, height, -1), 370 DEFINE_PROP_UINT16("depth", CG3State, depth, -1), 371 DEFINE_PROP_UINT64("prom-addr", CG3State, prom_addr, -1), 372 DEFINE_PROP_END_OF_LIST(), 373 }; 374 375 static void cg3_class_init(ObjectClass *klass, void *data) 376 { 377 DeviceClass *dc = DEVICE_CLASS(klass); 378 379 dc->realize = cg3_realizefn; 380 dc->reset = cg3_reset; 381 dc->vmsd = &vmstate_cg3; 382 dc->props = cg3_properties; 383 } 384 385 static const TypeInfo cg3_info = { 386 .name = TYPE_CG3, 387 .parent = TYPE_SYS_BUS_DEVICE, 388 .instance_size = sizeof(CG3State), 389 .instance_init = cg3_initfn, 390 .class_init = cg3_class_init, 391 }; 392 393 static void cg3_register_types(void) 394 { 395 type_register_static(&cg3_info); 396 } 397 398 type_init(cg3_register_types) 399