1 /* 2 * QEMU CG3 Frame buffer 3 * 4 * Copyright (c) 2012 Bob Breuer 5 * Copyright (c) 2013 Mark Cave-Ayland 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu-common.h" 27 #include "qemu/error-report.h" 28 #include "ui/console.h" 29 #include "hw/sysbus.h" 30 #include "hw/loader.h" 31 32 /* Change to 1 to enable debugging */ 33 #define DEBUG_CG3 0 34 35 #define CG3_ROM_FILE "QEMU,cgthree.bin" 36 #define FCODE_MAX_ROM_SIZE 0x10000 37 38 #define CG3_REG_SIZE 0x20 39 40 #define CG3_REG_BT458_ADDR 0x0 41 #define CG3_REG_BT458_COLMAP 0x4 42 #define CG3_REG_FBC_CTRL 0x10 43 #define CG3_REG_FBC_STATUS 0x11 44 #define CG3_REG_FBC_CURSTART 0x12 45 #define CG3_REG_FBC_CUREND 0x13 46 #define CG3_REG_FBC_VCTRL 0x14 47 48 /* Control register flags */ 49 #define CG3_CR_ENABLE_INTS 0x80 50 51 /* Status register flags */ 52 #define CG3_SR_PENDING_INT 0x80 53 #define CG3_SR_1152_900_76_B 0x60 54 #define CG3_SR_ID_COLOR 0x01 55 56 #define CG3_VRAM_SIZE 0x100000 57 #define CG3_VRAM_OFFSET 0x800000 58 59 #define DPRINTF(fmt, ...) do { \ 60 if (DEBUG_CG3) { \ 61 printf("CG3: " fmt , ## __VA_ARGS__); \ 62 } \ 63 } while (0); 64 65 #define TYPE_CG3 "cgthree" 66 #define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3) 67 68 typedef struct CG3State { 69 SysBusDevice parent_obj; 70 71 QemuConsole *con; 72 qemu_irq irq; 73 hwaddr prom_addr; 74 MemoryRegion vram_mem; 75 MemoryRegion rom; 76 MemoryRegion reg; 77 uint32_t vram_size; 78 int full_update; 79 uint8_t regs[16]; 80 uint8_t r[256], g[256], b[256]; 81 uint16_t width, height, depth; 82 uint8_t dac_index, dac_state; 83 } CG3State; 84 85 static void cg3_update_display(void *opaque) 86 { 87 CG3State *s = opaque; 88 DisplaySurface *surface = qemu_console_surface(s->con); 89 const uint8_t *pix; 90 uint32_t *data; 91 uint32_t dval; 92 int x, y, y_start; 93 unsigned int width, height; 94 ram_addr_t page, page_min, page_max; 95 96 if (surface_bits_per_pixel(surface) != 32) { 97 return; 98 } 99 width = s->width; 100 height = s->height; 101 102 y_start = -1; 103 page_min = -1; 104 page_max = 0; 105 page = 0; 106 pix = memory_region_get_ram_ptr(&s->vram_mem); 107 data = (uint32_t *)surface_data(surface); 108 109 memory_region_sync_dirty_bitmap(&s->vram_mem); 110 for (y = 0; y < height; y++) { 111 int update = s->full_update; 112 113 page = (y * width) & TARGET_PAGE_MASK; 114 update |= memory_region_get_dirty(&s->vram_mem, page, page + width, 115 DIRTY_MEMORY_VGA); 116 if (update) { 117 if (y_start < 0) { 118 y_start = y; 119 } 120 if (page < page_min) { 121 page_min = page; 122 } 123 if (page > page_max) { 124 page_max = page; 125 } 126 127 for (x = 0; x < width; x++) { 128 dval = *pix++; 129 dval = (s->r[dval] << 16) | (s->g[dval] << 8) | s->b[dval]; 130 *data++ = dval; 131 } 132 } else { 133 if (y_start >= 0) { 134 dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start); 135 y_start = -1; 136 } 137 pix += width; 138 data += width; 139 } 140 } 141 s->full_update = 0; 142 if (y_start >= 0) { 143 dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start); 144 } 145 if (page_max >= page_min) { 146 memory_region_reset_dirty(&s->vram_mem, 147 page_min, page_max - page_min + TARGET_PAGE_SIZE, 148 DIRTY_MEMORY_VGA); 149 } 150 /* vsync interrupt? */ 151 if (s->regs[0] & CG3_CR_ENABLE_INTS) { 152 s->regs[1] |= CG3_SR_PENDING_INT; 153 qemu_irq_raise(s->irq); 154 } 155 } 156 157 static void cg3_invalidate_display(void *opaque) 158 { 159 CG3State *s = opaque; 160 161 memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE); 162 } 163 164 static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size) 165 { 166 CG3State *s = opaque; 167 int val; 168 169 switch (addr) { 170 case CG3_REG_BT458_ADDR: 171 case CG3_REG_BT458_COLMAP: 172 val = 0; 173 break; 174 case CG3_REG_FBC_CTRL: 175 val = s->regs[0]; 176 break; 177 case CG3_REG_FBC_STATUS: 178 /* monitor ID 6, board type = 1 (color) */ 179 val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR; 180 break; 181 case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1: 182 val = s->regs[addr - 0x10]; 183 break; 184 default: 185 qemu_log_mask(LOG_UNIMP, 186 "cg3: Unimplemented register read " 187 "reg 0x%" HWADDR_PRIx " size 0x%x\n", 188 addr, size); 189 val = 0; 190 break; 191 } 192 DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", val, addr); 193 return val; 194 } 195 196 static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val, 197 unsigned size) 198 { 199 CG3State *s = opaque; 200 uint8_t regval; 201 int i; 202 203 DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " size %d\n", 204 val, addr, size); 205 206 switch (addr) { 207 case CG3_REG_BT458_ADDR: 208 s->dac_index = val; 209 s->dac_state = 0; 210 break; 211 case CG3_REG_BT458_COLMAP: 212 /* This register can be written to as either a long word or a byte */ 213 if (size == 1) { 214 val <<= 24; 215 } 216 217 for (i = 0; i < size; i++) { 218 regval = val >> 24; 219 220 switch (s->dac_state) { 221 case 0: 222 s->r[s->dac_index] = regval; 223 s->dac_state++; 224 break; 225 case 1: 226 s->g[s->dac_index] = regval; 227 s->dac_state++; 228 break; 229 case 2: 230 s->b[s->dac_index] = regval; 231 /* Index autoincrement */ 232 s->dac_index = (s->dac_index + 1) & 0xff; 233 default: 234 s->dac_state = 0; 235 break; 236 } 237 val <<= 8; 238 } 239 s->full_update = 1; 240 break; 241 case CG3_REG_FBC_CTRL: 242 s->regs[0] = val; 243 break; 244 case CG3_REG_FBC_STATUS: 245 if (s->regs[1] & CG3_SR_PENDING_INT) { 246 /* clear interrupt */ 247 s->regs[1] &= ~CG3_SR_PENDING_INT; 248 qemu_irq_lower(s->irq); 249 } 250 break; 251 case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1: 252 s->regs[addr - 0x10] = val; 253 break; 254 default: 255 qemu_log_mask(LOG_UNIMP, 256 "cg3: Unimplemented register write " 257 "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n", 258 addr, size, val); 259 break; 260 } 261 } 262 263 static const MemoryRegionOps cg3_reg_ops = { 264 .read = cg3_reg_read, 265 .write = cg3_reg_write, 266 .endianness = DEVICE_NATIVE_ENDIAN, 267 .valid = { 268 .min_access_size = 1, 269 .max_access_size = 4, 270 }, 271 }; 272 273 static const GraphicHwOps cg3_ops = { 274 .invalidate = cg3_invalidate_display, 275 .gfx_update = cg3_update_display, 276 }; 277 278 static void cg3_initfn(Object *obj) 279 { 280 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 281 CG3State *s = CG3(obj); 282 283 memory_region_init_ram(&s->rom, obj, "cg3.prom", FCODE_MAX_ROM_SIZE, 284 &error_fatal); 285 memory_region_set_readonly(&s->rom, true); 286 sysbus_init_mmio(sbd, &s->rom); 287 288 memory_region_init_io(&s->reg, obj, &cg3_reg_ops, s, "cg3.reg", 289 CG3_REG_SIZE); 290 sysbus_init_mmio(sbd, &s->reg); 291 } 292 293 static void cg3_realizefn(DeviceState *dev, Error **errp) 294 { 295 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 296 CG3State *s = CG3(dev); 297 int ret; 298 char *fcode_filename; 299 300 /* FCode ROM */ 301 vmstate_register_ram_global(&s->rom); 302 fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE); 303 if (fcode_filename) { 304 ret = load_image_targphys(fcode_filename, s->prom_addr, 305 FCODE_MAX_ROM_SIZE); 306 g_free(fcode_filename); 307 if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) { 308 error_report("cg3: could not load prom '%s'", CG3_ROM_FILE); 309 } 310 } 311 312 memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size, 313 &error_fatal); 314 memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA); 315 vmstate_register_ram_global(&s->vram_mem); 316 sysbus_init_mmio(sbd, &s->vram_mem); 317 318 sysbus_init_irq(sbd, &s->irq); 319 320 s->con = graphic_console_init(DEVICE(dev), 0, &cg3_ops, s); 321 qemu_console_resize(s->con, s->width, s->height); 322 } 323 324 static int vmstate_cg3_post_load(void *opaque, int version_id) 325 { 326 CG3State *s = opaque; 327 328 cg3_invalidate_display(s); 329 330 return 0; 331 } 332 333 static const VMStateDescription vmstate_cg3 = { 334 .name = "cg3", 335 .version_id = 1, 336 .minimum_version_id = 1, 337 .post_load = vmstate_cg3_post_load, 338 .fields = (VMStateField[]) { 339 VMSTATE_UINT16(height, CG3State), 340 VMSTATE_UINT16(width, CG3State), 341 VMSTATE_UINT16(depth, CG3State), 342 VMSTATE_BUFFER(r, CG3State), 343 VMSTATE_BUFFER(g, CG3State), 344 VMSTATE_BUFFER(b, CG3State), 345 VMSTATE_UINT8(dac_index, CG3State), 346 VMSTATE_UINT8(dac_state, CG3State), 347 VMSTATE_END_OF_LIST() 348 } 349 }; 350 351 static void cg3_reset(DeviceState *d) 352 { 353 CG3State *s = CG3(d); 354 355 /* Initialize palette */ 356 memset(s->r, 0, 256); 357 memset(s->g, 0, 256); 358 memset(s->b, 0, 256); 359 360 s->dac_state = 0; 361 s->full_update = 1; 362 qemu_irq_lower(s->irq); 363 } 364 365 static Property cg3_properties[] = { 366 DEFINE_PROP_UINT32("vram-size", CG3State, vram_size, -1), 367 DEFINE_PROP_UINT16("width", CG3State, width, -1), 368 DEFINE_PROP_UINT16("height", CG3State, height, -1), 369 DEFINE_PROP_UINT16("depth", CG3State, depth, -1), 370 DEFINE_PROP_UINT64("prom-addr", CG3State, prom_addr, -1), 371 DEFINE_PROP_END_OF_LIST(), 372 }; 373 374 static void cg3_class_init(ObjectClass *klass, void *data) 375 { 376 DeviceClass *dc = DEVICE_CLASS(klass); 377 378 dc->realize = cg3_realizefn; 379 dc->reset = cg3_reset; 380 dc->vmsd = &vmstate_cg3; 381 dc->props = cg3_properties; 382 } 383 384 static const TypeInfo cg3_info = { 385 .name = TYPE_CG3, 386 .parent = TYPE_SYS_BUS_DEVICE, 387 .instance_size = sizeof(CG3State), 388 .instance_init = cg3_initfn, 389 .class_init = cg3_class_init, 390 }; 391 392 static void cg3_register_types(void) 393 { 394 type_register_static(&cg3_info); 395 } 396 397 type_init(cg3_register_types) 398