1 /* 2 * QEMU CG3 Frame buffer 3 * 4 * Copyright (c) 2012 Bob Breuer 5 * Copyright (c) 2013 Mark Cave-Ayland 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu-common.h" 28 #include "qapi/error.h" 29 #include "qemu/error-report.h" 30 #include "ui/console.h" 31 #include "hw/sysbus.h" 32 #include "migration/vmstate.h" 33 #include "hw/irq.h" 34 #include "hw/loader.h" 35 #include "hw/qdev-properties.h" 36 #include "qemu/log.h" 37 #include "qemu/module.h" 38 #include "trace.h" 39 #include "qom/object.h" 40 41 /* Change to 1 to enable debugging */ 42 #define DEBUG_CG3 0 43 44 #define CG3_ROM_FILE "QEMU,cgthree.bin" 45 #define FCODE_MAX_ROM_SIZE 0x10000 46 47 #define CG3_REG_SIZE 0x20 48 49 #define CG3_REG_BT458_ADDR 0x0 50 #define CG3_REG_BT458_COLMAP 0x4 51 #define CG3_REG_FBC_CTRL 0x10 52 #define CG3_REG_FBC_STATUS 0x11 53 #define CG3_REG_FBC_CURSTART 0x12 54 #define CG3_REG_FBC_CUREND 0x13 55 #define CG3_REG_FBC_VCTRL 0x14 56 57 /* Control register flags */ 58 #define CG3_CR_ENABLE_INTS 0x80 59 60 /* Status register flags */ 61 #define CG3_SR_PENDING_INT 0x80 62 #define CG3_SR_1152_900_76_B 0x60 63 #define CG3_SR_ID_COLOR 0x01 64 65 #define CG3_VRAM_SIZE 0x100000 66 #define CG3_VRAM_OFFSET 0x800000 67 68 #define TYPE_CG3 "cgthree" 69 typedef struct CG3State CG3State; 70 DECLARE_INSTANCE_CHECKER(CG3State, CG3, 71 TYPE_CG3) 72 73 struct CG3State { 74 SysBusDevice parent_obj; 75 76 QemuConsole *con; 77 qemu_irq irq; 78 hwaddr prom_addr; 79 MemoryRegion vram_mem; 80 MemoryRegion rom; 81 MemoryRegion reg; 82 uint32_t vram_size; 83 int full_update; 84 uint8_t regs[16]; 85 uint8_t r[256], g[256], b[256]; 86 uint16_t width, height, depth; 87 uint8_t dac_index, dac_state; 88 }; 89 90 static void cg3_update_display(void *opaque) 91 { 92 CG3State *s = opaque; 93 DisplaySurface *surface = qemu_console_surface(s->con); 94 const uint8_t *pix; 95 uint32_t *data; 96 uint32_t dval; 97 int x, y, y_start; 98 unsigned int width, height; 99 ram_addr_t page; 100 DirtyBitmapSnapshot *snap = NULL; 101 102 if (surface_bits_per_pixel(surface) != 32) { 103 return; 104 } 105 width = s->width; 106 height = s->height; 107 108 y_start = -1; 109 pix = memory_region_get_ram_ptr(&s->vram_mem); 110 data = (uint32_t *)surface_data(surface); 111 112 if (!s->full_update) { 113 snap = memory_region_snapshot_and_clear_dirty(&s->vram_mem, 0x0, 114 memory_region_size(&s->vram_mem), 115 DIRTY_MEMORY_VGA); 116 } 117 118 for (y = 0; y < height; y++) { 119 int update; 120 121 page = (ram_addr_t)y * width; 122 123 if (s->full_update) { 124 update = 1; 125 } else { 126 update = memory_region_snapshot_get_dirty(&s->vram_mem, snap, page, 127 width); 128 } 129 130 if (update) { 131 if (y_start < 0) { 132 y_start = y; 133 } 134 135 for (x = 0; x < width; x++) { 136 dval = *pix++; 137 dval = (s->r[dval] << 16) | (s->g[dval] << 8) | s->b[dval]; 138 *data++ = dval; 139 } 140 } else { 141 if (y_start >= 0) { 142 dpy_gfx_update(s->con, 0, y_start, width, y - y_start); 143 y_start = -1; 144 } 145 pix += width; 146 data += width; 147 } 148 } 149 s->full_update = 0; 150 if (y_start >= 0) { 151 dpy_gfx_update(s->con, 0, y_start, width, y - y_start); 152 } 153 /* vsync interrupt? */ 154 if (s->regs[0] & CG3_CR_ENABLE_INTS) { 155 s->regs[1] |= CG3_SR_PENDING_INT; 156 qemu_irq_raise(s->irq); 157 } 158 g_free(snap); 159 } 160 161 static void cg3_invalidate_display(void *opaque) 162 { 163 CG3State *s = opaque; 164 165 memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE); 166 } 167 168 static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size) 169 { 170 CG3State *s = opaque; 171 int val; 172 173 switch (addr) { 174 case CG3_REG_BT458_ADDR: 175 case CG3_REG_BT458_COLMAP: 176 val = 0; 177 break; 178 case CG3_REG_FBC_CTRL: 179 val = s->regs[0]; 180 break; 181 case CG3_REG_FBC_STATUS: 182 /* monitor ID 6, board type = 1 (color) */ 183 val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR; 184 break; 185 case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1: 186 val = s->regs[addr - 0x10]; 187 break; 188 default: 189 qemu_log_mask(LOG_UNIMP, 190 "cg3: Unimplemented register read " 191 "reg 0x%" HWADDR_PRIx " size 0x%x\n", 192 addr, size); 193 val = 0; 194 break; 195 } 196 trace_cg3_read(addr, val, size); 197 198 return val; 199 } 200 201 static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val, 202 unsigned size) 203 { 204 CG3State *s = opaque; 205 uint8_t regval; 206 int i; 207 208 trace_cg3_write(addr, val, size); 209 switch (addr) { 210 case CG3_REG_BT458_ADDR: 211 s->dac_index = val; 212 s->dac_state = 0; 213 break; 214 case CG3_REG_BT458_COLMAP: 215 /* This register can be written to as either a long word or a byte */ 216 if (size == 1) { 217 val <<= 24; 218 } 219 220 for (i = 0; i < size; i++) { 221 regval = val >> 24; 222 223 switch (s->dac_state) { 224 case 0: 225 s->r[s->dac_index] = regval; 226 s->dac_state++; 227 break; 228 case 1: 229 s->g[s->dac_index] = regval; 230 s->dac_state++; 231 break; 232 case 2: 233 s->b[s->dac_index] = regval; 234 /* Index autoincrement */ 235 s->dac_index = (s->dac_index + 1) & 0xff; 236 /* fall through */ 237 default: 238 s->dac_state = 0; 239 break; 240 } 241 val <<= 8; 242 } 243 s->full_update = 1; 244 break; 245 case CG3_REG_FBC_CTRL: 246 s->regs[0] = val; 247 break; 248 case CG3_REG_FBC_STATUS: 249 if (s->regs[1] & CG3_SR_PENDING_INT) { 250 /* clear interrupt */ 251 s->regs[1] &= ~CG3_SR_PENDING_INT; 252 qemu_irq_lower(s->irq); 253 } 254 break; 255 case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1: 256 s->regs[addr - 0x10] = val; 257 break; 258 default: 259 qemu_log_mask(LOG_UNIMP, 260 "cg3: Unimplemented register write " 261 "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n", 262 addr, size, val); 263 break; 264 } 265 } 266 267 static const MemoryRegionOps cg3_reg_ops = { 268 .read = cg3_reg_read, 269 .write = cg3_reg_write, 270 .endianness = DEVICE_NATIVE_ENDIAN, 271 .valid = { 272 .min_access_size = 1, 273 .max_access_size = 4, 274 }, 275 }; 276 277 static const GraphicHwOps cg3_ops = { 278 .invalidate = cg3_invalidate_display, 279 .gfx_update = cg3_update_display, 280 }; 281 282 static void cg3_initfn(Object *obj) 283 { 284 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 285 CG3State *s = CG3(obj); 286 287 memory_region_init_rom_nomigrate(&s->rom, obj, "cg3.prom", 288 FCODE_MAX_ROM_SIZE, &error_fatal); 289 sysbus_init_mmio(sbd, &s->rom); 290 291 memory_region_init_io(&s->reg, obj, &cg3_reg_ops, s, "cg3.reg", 292 CG3_REG_SIZE); 293 sysbus_init_mmio(sbd, &s->reg); 294 } 295 296 static void cg3_realizefn(DeviceState *dev, Error **errp) 297 { 298 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 299 CG3State *s = CG3(dev); 300 int ret; 301 char *fcode_filename; 302 303 /* FCode ROM */ 304 vmstate_register_ram_global(&s->rom); 305 fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE); 306 if (fcode_filename) { 307 ret = load_image_mr(fcode_filename, &s->rom); 308 g_free(fcode_filename); 309 if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) { 310 warn_report("cg3: could not load prom '%s'", CG3_ROM_FILE); 311 } 312 } 313 314 memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size, 315 &error_fatal); 316 memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA); 317 sysbus_init_mmio(sbd, &s->vram_mem); 318 319 sysbus_init_irq(sbd, &s->irq); 320 321 s->con = graphic_console_init(dev, 0, &cg3_ops, s); 322 qemu_console_resize(s->con, s->width, s->height); 323 } 324 325 static int vmstate_cg3_post_load(void *opaque, int version_id) 326 { 327 CG3State *s = opaque; 328 329 cg3_invalidate_display(s); 330 331 return 0; 332 } 333 334 static const VMStateDescription vmstate_cg3 = { 335 .name = "cg3", 336 .version_id = 1, 337 .minimum_version_id = 1, 338 .post_load = vmstate_cg3_post_load, 339 .fields = (VMStateField[]) { 340 VMSTATE_UINT16(height, CG3State), 341 VMSTATE_UINT16(width, CG3State), 342 VMSTATE_UINT16(depth, CG3State), 343 VMSTATE_BUFFER(r, CG3State), 344 VMSTATE_BUFFER(g, CG3State), 345 VMSTATE_BUFFER(b, CG3State), 346 VMSTATE_UINT8(dac_index, CG3State), 347 VMSTATE_UINT8(dac_state, CG3State), 348 VMSTATE_END_OF_LIST() 349 } 350 }; 351 352 static void cg3_reset(DeviceState *d) 353 { 354 CG3State *s = CG3(d); 355 356 /* Initialize palette */ 357 memset(s->r, 0, 256); 358 memset(s->g, 0, 256); 359 memset(s->b, 0, 256); 360 361 s->dac_state = 0; 362 s->full_update = 1; 363 qemu_irq_lower(s->irq); 364 } 365 366 static Property cg3_properties[] = { 367 DEFINE_PROP_UINT32("vram-size", CG3State, vram_size, -1), 368 DEFINE_PROP_UINT16("width", CG3State, width, -1), 369 DEFINE_PROP_UINT16("height", CG3State, height, -1), 370 DEFINE_PROP_UINT16("depth", CG3State, depth, -1), 371 DEFINE_PROP_END_OF_LIST(), 372 }; 373 374 static void cg3_class_init(ObjectClass *klass, void *data) 375 { 376 DeviceClass *dc = DEVICE_CLASS(klass); 377 378 dc->realize = cg3_realizefn; 379 dc->reset = cg3_reset; 380 dc->vmsd = &vmstate_cg3; 381 device_class_set_props(dc, cg3_properties); 382 } 383 384 static const TypeInfo cg3_info = { 385 .name = TYPE_CG3, 386 .parent = TYPE_SYS_BUS_DEVICE, 387 .instance_size = sizeof(CG3State), 388 .instance_init = cg3_initfn, 389 .class_init = cg3_class_init, 390 }; 391 392 static void cg3_register_types(void) 393 { 394 type_register_static(&cg3_info); 395 } 396 397 type_init(cg3_register_types) 398