1 /* 2 * QEMU CG3 Frame buffer 3 * 4 * Copyright (c) 2012 Bob Breuer 5 * Copyright (c) 2013 Mark Cave-Ayland 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu-common.h" 28 #include "qapi/error.h" 29 #include "qemu/error-report.h" 30 #include "ui/console.h" 31 #include "hw/sysbus.h" 32 #include "migration/vmstate.h" 33 #include "hw/irq.h" 34 #include "hw/loader.h" 35 #include "hw/qdev-properties.h" 36 #include "qemu/log.h" 37 #include "qemu/module.h" 38 #include "trace.h" 39 40 /* Change to 1 to enable debugging */ 41 #define DEBUG_CG3 0 42 43 #define CG3_ROM_FILE "QEMU,cgthree.bin" 44 #define FCODE_MAX_ROM_SIZE 0x10000 45 46 #define CG3_REG_SIZE 0x20 47 48 #define CG3_REG_BT458_ADDR 0x0 49 #define CG3_REG_BT458_COLMAP 0x4 50 #define CG3_REG_FBC_CTRL 0x10 51 #define CG3_REG_FBC_STATUS 0x11 52 #define CG3_REG_FBC_CURSTART 0x12 53 #define CG3_REG_FBC_CUREND 0x13 54 #define CG3_REG_FBC_VCTRL 0x14 55 56 /* Control register flags */ 57 #define CG3_CR_ENABLE_INTS 0x80 58 59 /* Status register flags */ 60 #define CG3_SR_PENDING_INT 0x80 61 #define CG3_SR_1152_900_76_B 0x60 62 #define CG3_SR_ID_COLOR 0x01 63 64 #define CG3_VRAM_SIZE 0x100000 65 #define CG3_VRAM_OFFSET 0x800000 66 67 #define TYPE_CG3 "cgthree" 68 #define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3) 69 70 typedef struct CG3State { 71 SysBusDevice parent_obj; 72 73 QemuConsole *con; 74 qemu_irq irq; 75 hwaddr prom_addr; 76 MemoryRegion vram_mem; 77 MemoryRegion rom; 78 MemoryRegion reg; 79 uint32_t vram_size; 80 int full_update; 81 uint8_t regs[16]; 82 uint8_t r[256], g[256], b[256]; 83 uint16_t width, height, depth; 84 uint8_t dac_index, dac_state; 85 } CG3State; 86 87 static void cg3_update_display(void *opaque) 88 { 89 CG3State *s = opaque; 90 DisplaySurface *surface = qemu_console_surface(s->con); 91 const uint8_t *pix; 92 uint32_t *data; 93 uint32_t dval; 94 int x, y, y_start; 95 unsigned int width, height; 96 ram_addr_t page; 97 DirtyBitmapSnapshot *snap = NULL; 98 99 if (surface_bits_per_pixel(surface) != 32) { 100 return; 101 } 102 width = s->width; 103 height = s->height; 104 105 y_start = -1; 106 pix = memory_region_get_ram_ptr(&s->vram_mem); 107 data = (uint32_t *)surface_data(surface); 108 109 if (!s->full_update) { 110 snap = memory_region_snapshot_and_clear_dirty(&s->vram_mem, 0x0, 111 memory_region_size(&s->vram_mem), 112 DIRTY_MEMORY_VGA); 113 } 114 115 for (y = 0; y < height; y++) { 116 int update; 117 118 page = (ram_addr_t)y * width; 119 120 if (s->full_update) { 121 update = 1; 122 } else { 123 update = memory_region_snapshot_get_dirty(&s->vram_mem, snap, page, 124 width); 125 } 126 127 if (update) { 128 if (y_start < 0) { 129 y_start = y; 130 } 131 132 for (x = 0; x < width; x++) { 133 dval = *pix++; 134 dval = (s->r[dval] << 16) | (s->g[dval] << 8) | s->b[dval]; 135 *data++ = dval; 136 } 137 } else { 138 if (y_start >= 0) { 139 dpy_gfx_update(s->con, 0, y_start, width, y - y_start); 140 y_start = -1; 141 } 142 pix += width; 143 data += width; 144 } 145 } 146 s->full_update = 0; 147 if (y_start >= 0) { 148 dpy_gfx_update(s->con, 0, y_start, width, y - y_start); 149 } 150 /* vsync interrupt? */ 151 if (s->regs[0] & CG3_CR_ENABLE_INTS) { 152 s->regs[1] |= CG3_SR_PENDING_INT; 153 qemu_irq_raise(s->irq); 154 } 155 g_free(snap); 156 } 157 158 static void cg3_invalidate_display(void *opaque) 159 { 160 CG3State *s = opaque; 161 162 memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE); 163 } 164 165 static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size) 166 { 167 CG3State *s = opaque; 168 int val; 169 170 switch (addr) { 171 case CG3_REG_BT458_ADDR: 172 case CG3_REG_BT458_COLMAP: 173 val = 0; 174 break; 175 case CG3_REG_FBC_CTRL: 176 val = s->regs[0]; 177 break; 178 case CG3_REG_FBC_STATUS: 179 /* monitor ID 6, board type = 1 (color) */ 180 val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR; 181 break; 182 case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1: 183 val = s->regs[addr - 0x10]; 184 break; 185 default: 186 qemu_log_mask(LOG_UNIMP, 187 "cg3: Unimplemented register read " 188 "reg 0x%" HWADDR_PRIx " size 0x%x\n", 189 addr, size); 190 val = 0; 191 break; 192 } 193 trace_cg3_read(addr, val, size); 194 195 return val; 196 } 197 198 static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val, 199 unsigned size) 200 { 201 CG3State *s = opaque; 202 uint8_t regval; 203 int i; 204 205 trace_cg3_write(addr, val, size); 206 switch (addr) { 207 case CG3_REG_BT458_ADDR: 208 s->dac_index = val; 209 s->dac_state = 0; 210 break; 211 case CG3_REG_BT458_COLMAP: 212 /* This register can be written to as either a long word or a byte */ 213 if (size == 1) { 214 val <<= 24; 215 } 216 217 for (i = 0; i < size; i++) { 218 regval = val >> 24; 219 220 switch (s->dac_state) { 221 case 0: 222 s->r[s->dac_index] = regval; 223 s->dac_state++; 224 break; 225 case 1: 226 s->g[s->dac_index] = regval; 227 s->dac_state++; 228 break; 229 case 2: 230 s->b[s->dac_index] = regval; 231 /* Index autoincrement */ 232 s->dac_index = (s->dac_index + 1) & 0xff; 233 /* fall through */ 234 default: 235 s->dac_state = 0; 236 break; 237 } 238 val <<= 8; 239 } 240 s->full_update = 1; 241 break; 242 case CG3_REG_FBC_CTRL: 243 s->regs[0] = val; 244 break; 245 case CG3_REG_FBC_STATUS: 246 if (s->regs[1] & CG3_SR_PENDING_INT) { 247 /* clear interrupt */ 248 s->regs[1] &= ~CG3_SR_PENDING_INT; 249 qemu_irq_lower(s->irq); 250 } 251 break; 252 case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1: 253 s->regs[addr - 0x10] = val; 254 break; 255 default: 256 qemu_log_mask(LOG_UNIMP, 257 "cg3: Unimplemented register write " 258 "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n", 259 addr, size, val); 260 break; 261 } 262 } 263 264 static const MemoryRegionOps cg3_reg_ops = { 265 .read = cg3_reg_read, 266 .write = cg3_reg_write, 267 .endianness = DEVICE_NATIVE_ENDIAN, 268 .valid = { 269 .min_access_size = 1, 270 .max_access_size = 4, 271 }, 272 }; 273 274 static const GraphicHwOps cg3_ops = { 275 .invalidate = cg3_invalidate_display, 276 .gfx_update = cg3_update_display, 277 }; 278 279 static void cg3_initfn(Object *obj) 280 { 281 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 282 CG3State *s = CG3(obj); 283 284 memory_region_init_rom_nomigrate(&s->rom, obj, "cg3.prom", 285 FCODE_MAX_ROM_SIZE, &error_fatal); 286 sysbus_init_mmio(sbd, &s->rom); 287 288 memory_region_init_io(&s->reg, obj, &cg3_reg_ops, s, "cg3.reg", 289 CG3_REG_SIZE); 290 sysbus_init_mmio(sbd, &s->reg); 291 } 292 293 static void cg3_realizefn(DeviceState *dev, Error **errp) 294 { 295 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 296 CG3State *s = CG3(dev); 297 int ret; 298 char *fcode_filename; 299 300 /* FCode ROM */ 301 vmstate_register_ram_global(&s->rom); 302 fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE); 303 if (fcode_filename) { 304 ret = load_image_mr(fcode_filename, &s->rom); 305 g_free(fcode_filename); 306 if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) { 307 warn_report("cg3: could not load prom '%s'", CG3_ROM_FILE); 308 } 309 } 310 311 memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size, 312 &error_fatal); 313 memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA); 314 sysbus_init_mmio(sbd, &s->vram_mem); 315 316 sysbus_init_irq(sbd, &s->irq); 317 318 s->con = graphic_console_init(dev, 0, &cg3_ops, s); 319 qemu_console_resize(s->con, s->width, s->height); 320 } 321 322 static int vmstate_cg3_post_load(void *opaque, int version_id) 323 { 324 CG3State *s = opaque; 325 326 cg3_invalidate_display(s); 327 328 return 0; 329 } 330 331 static const VMStateDescription vmstate_cg3 = { 332 .name = "cg3", 333 .version_id = 1, 334 .minimum_version_id = 1, 335 .post_load = vmstate_cg3_post_load, 336 .fields = (VMStateField[]) { 337 VMSTATE_UINT16(height, CG3State), 338 VMSTATE_UINT16(width, CG3State), 339 VMSTATE_UINT16(depth, CG3State), 340 VMSTATE_BUFFER(r, CG3State), 341 VMSTATE_BUFFER(g, CG3State), 342 VMSTATE_BUFFER(b, CG3State), 343 VMSTATE_UINT8(dac_index, CG3State), 344 VMSTATE_UINT8(dac_state, CG3State), 345 VMSTATE_END_OF_LIST() 346 } 347 }; 348 349 static void cg3_reset(DeviceState *d) 350 { 351 CG3State *s = CG3(d); 352 353 /* Initialize palette */ 354 memset(s->r, 0, 256); 355 memset(s->g, 0, 256); 356 memset(s->b, 0, 256); 357 358 s->dac_state = 0; 359 s->full_update = 1; 360 qemu_irq_lower(s->irq); 361 } 362 363 static Property cg3_properties[] = { 364 DEFINE_PROP_UINT32("vram-size", CG3State, vram_size, -1), 365 DEFINE_PROP_UINT16("width", CG3State, width, -1), 366 DEFINE_PROP_UINT16("height", CG3State, height, -1), 367 DEFINE_PROP_UINT16("depth", CG3State, depth, -1), 368 DEFINE_PROP_END_OF_LIST(), 369 }; 370 371 static void cg3_class_init(ObjectClass *klass, void *data) 372 { 373 DeviceClass *dc = DEVICE_CLASS(klass); 374 375 dc->realize = cg3_realizefn; 376 dc->reset = cg3_reset; 377 dc->vmsd = &vmstate_cg3; 378 device_class_set_props(dc, cg3_properties); 379 } 380 381 static const TypeInfo cg3_info = { 382 .name = TYPE_CG3, 383 .parent = TYPE_SYS_BUS_DEVICE, 384 .instance_size = sizeof(CG3State), 385 .instance_init = cg3_initfn, 386 .class_init = cg3_class_init, 387 }; 388 389 static void cg3_register_types(void) 390 { 391 type_register_static(&cg3_info); 392 } 393 394 type_init(cg3_register_types) 395