1 /* 2 * QEMU CG3 Frame buffer 3 * 4 * Copyright (c) 2012 Bob Breuer 5 * Copyright (c) 2013 Mark Cave-Ayland 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "qemu-common.h" 29 #include "qemu/error-report.h" 30 #include "ui/console.h" 31 #include "hw/sysbus.h" 32 #include "hw/loader.h" 33 #include "qemu/log.h" 34 35 /* Change to 1 to enable debugging */ 36 #define DEBUG_CG3 0 37 38 #define CG3_ROM_FILE "QEMU,cgthree.bin" 39 #define FCODE_MAX_ROM_SIZE 0x10000 40 41 #define CG3_REG_SIZE 0x20 42 43 #define CG3_REG_BT458_ADDR 0x0 44 #define CG3_REG_BT458_COLMAP 0x4 45 #define CG3_REG_FBC_CTRL 0x10 46 #define CG3_REG_FBC_STATUS 0x11 47 #define CG3_REG_FBC_CURSTART 0x12 48 #define CG3_REG_FBC_CUREND 0x13 49 #define CG3_REG_FBC_VCTRL 0x14 50 51 /* Control register flags */ 52 #define CG3_CR_ENABLE_INTS 0x80 53 54 /* Status register flags */ 55 #define CG3_SR_PENDING_INT 0x80 56 #define CG3_SR_1152_900_76_B 0x60 57 #define CG3_SR_ID_COLOR 0x01 58 59 #define CG3_VRAM_SIZE 0x100000 60 #define CG3_VRAM_OFFSET 0x800000 61 62 #define DPRINTF(fmt, ...) do { \ 63 if (DEBUG_CG3) { \ 64 printf("CG3: " fmt , ## __VA_ARGS__); \ 65 } \ 66 } while (0); 67 68 #define TYPE_CG3 "cgthree" 69 #define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3) 70 71 typedef struct CG3State { 72 SysBusDevice parent_obj; 73 74 QemuConsole *con; 75 qemu_irq irq; 76 hwaddr prom_addr; 77 MemoryRegion vram_mem; 78 MemoryRegion rom; 79 MemoryRegion reg; 80 uint32_t vram_size; 81 int full_update; 82 uint8_t regs[16]; 83 uint8_t r[256], g[256], b[256]; 84 uint16_t width, height, depth; 85 uint8_t dac_index, dac_state; 86 } CG3State; 87 88 static void cg3_update_display(void *opaque) 89 { 90 CG3State *s = opaque; 91 DisplaySurface *surface = qemu_console_surface(s->con); 92 const uint8_t *pix; 93 uint32_t *data; 94 uint32_t dval; 95 int x, y, y_start; 96 unsigned int width, height; 97 ram_addr_t page; 98 DirtyBitmapSnapshot *snap = NULL; 99 100 if (surface_bits_per_pixel(surface) != 32) { 101 return; 102 } 103 width = s->width; 104 height = s->height; 105 106 y_start = -1; 107 pix = memory_region_get_ram_ptr(&s->vram_mem); 108 data = (uint32_t *)surface_data(surface); 109 110 if (!s->full_update) { 111 memory_region_sync_dirty_bitmap(&s->vram_mem); 112 snap = memory_region_snapshot_and_clear_dirty(&s->vram_mem, 0x0, 113 memory_region_size(&s->vram_mem), 114 DIRTY_MEMORY_VGA); 115 } 116 117 for (y = 0; y < height; y++) { 118 int update; 119 120 page = (ram_addr_t)y * width; 121 122 if (s->full_update) { 123 update = 1; 124 } else { 125 update = memory_region_snapshot_get_dirty(&s->vram_mem, snap, page, 126 width); 127 } 128 129 if (update) { 130 if (y_start < 0) { 131 y_start = y; 132 } 133 134 for (x = 0; x < width; x++) { 135 dval = *pix++; 136 dval = (s->r[dval] << 16) | (s->g[dval] << 8) | s->b[dval]; 137 *data++ = dval; 138 } 139 } else { 140 if (y_start >= 0) { 141 dpy_gfx_update(s->con, 0, y_start, width, y - y_start); 142 y_start = -1; 143 } 144 pix += width; 145 data += width; 146 } 147 } 148 s->full_update = 0; 149 if (y_start >= 0) { 150 dpy_gfx_update(s->con, 0, y_start, width, y - y_start); 151 } 152 /* vsync interrupt? */ 153 if (s->regs[0] & CG3_CR_ENABLE_INTS) { 154 s->regs[1] |= CG3_SR_PENDING_INT; 155 qemu_irq_raise(s->irq); 156 } 157 g_free(snap); 158 } 159 160 static void cg3_invalidate_display(void *opaque) 161 { 162 CG3State *s = opaque; 163 164 memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE); 165 } 166 167 static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size) 168 { 169 CG3State *s = opaque; 170 int val; 171 172 switch (addr) { 173 case CG3_REG_BT458_ADDR: 174 case CG3_REG_BT458_COLMAP: 175 val = 0; 176 break; 177 case CG3_REG_FBC_CTRL: 178 val = s->regs[0]; 179 break; 180 case CG3_REG_FBC_STATUS: 181 /* monitor ID 6, board type = 1 (color) */ 182 val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR; 183 break; 184 case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1: 185 val = s->regs[addr - 0x10]; 186 break; 187 default: 188 qemu_log_mask(LOG_UNIMP, 189 "cg3: Unimplemented register read " 190 "reg 0x%" HWADDR_PRIx " size 0x%x\n", 191 addr, size); 192 val = 0; 193 break; 194 } 195 DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", val, addr); 196 return val; 197 } 198 199 static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val, 200 unsigned size) 201 { 202 CG3State *s = opaque; 203 uint8_t regval; 204 int i; 205 206 DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " size %d\n", 207 val, addr, size); 208 209 switch (addr) { 210 case CG3_REG_BT458_ADDR: 211 s->dac_index = val; 212 s->dac_state = 0; 213 break; 214 case CG3_REG_BT458_COLMAP: 215 /* This register can be written to as either a long word or a byte */ 216 if (size == 1) { 217 val <<= 24; 218 } 219 220 for (i = 0; i < size; i++) { 221 regval = val >> 24; 222 223 switch (s->dac_state) { 224 case 0: 225 s->r[s->dac_index] = regval; 226 s->dac_state++; 227 break; 228 case 1: 229 s->g[s->dac_index] = regval; 230 s->dac_state++; 231 break; 232 case 2: 233 s->b[s->dac_index] = regval; 234 /* Index autoincrement */ 235 s->dac_index = (s->dac_index + 1) & 0xff; 236 default: 237 s->dac_state = 0; 238 break; 239 } 240 val <<= 8; 241 } 242 s->full_update = 1; 243 break; 244 case CG3_REG_FBC_CTRL: 245 s->regs[0] = val; 246 break; 247 case CG3_REG_FBC_STATUS: 248 if (s->regs[1] & CG3_SR_PENDING_INT) { 249 /* clear interrupt */ 250 s->regs[1] &= ~CG3_SR_PENDING_INT; 251 qemu_irq_lower(s->irq); 252 } 253 break; 254 case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1: 255 s->regs[addr - 0x10] = val; 256 break; 257 default: 258 qemu_log_mask(LOG_UNIMP, 259 "cg3: Unimplemented register write " 260 "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n", 261 addr, size, val); 262 break; 263 } 264 } 265 266 static const MemoryRegionOps cg3_reg_ops = { 267 .read = cg3_reg_read, 268 .write = cg3_reg_write, 269 .endianness = DEVICE_NATIVE_ENDIAN, 270 .valid = { 271 .min_access_size = 1, 272 .max_access_size = 4, 273 }, 274 }; 275 276 static const GraphicHwOps cg3_ops = { 277 .invalidate = cg3_invalidate_display, 278 .gfx_update = cg3_update_display, 279 }; 280 281 static void cg3_initfn(Object *obj) 282 { 283 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 284 CG3State *s = CG3(obj); 285 286 memory_region_init_ram_nomigrate(&s->rom, obj, "cg3.prom", FCODE_MAX_ROM_SIZE, 287 &error_fatal); 288 memory_region_set_readonly(&s->rom, true); 289 sysbus_init_mmio(sbd, &s->rom); 290 291 memory_region_init_io(&s->reg, obj, &cg3_reg_ops, s, "cg3.reg", 292 CG3_REG_SIZE); 293 sysbus_init_mmio(sbd, &s->reg); 294 } 295 296 static void cg3_realizefn(DeviceState *dev, Error **errp) 297 { 298 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 299 CG3State *s = CG3(dev); 300 int ret; 301 char *fcode_filename; 302 303 /* FCode ROM */ 304 vmstate_register_ram_global(&s->rom); 305 fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE); 306 if (fcode_filename) { 307 ret = load_image_mr(fcode_filename, &s->rom); 308 g_free(fcode_filename); 309 if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) { 310 error_report("cg3: could not load prom '%s'", CG3_ROM_FILE); 311 } 312 } 313 314 memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size, 315 &error_fatal); 316 memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA); 317 sysbus_init_mmio(sbd, &s->vram_mem); 318 319 sysbus_init_irq(sbd, &s->irq); 320 321 s->con = graphic_console_init(DEVICE(dev), 0, &cg3_ops, s); 322 qemu_console_resize(s->con, s->width, s->height); 323 } 324 325 static int vmstate_cg3_post_load(void *opaque, int version_id) 326 { 327 CG3State *s = opaque; 328 329 cg3_invalidate_display(s); 330 331 return 0; 332 } 333 334 static const VMStateDescription vmstate_cg3 = { 335 .name = "cg3", 336 .version_id = 1, 337 .minimum_version_id = 1, 338 .post_load = vmstate_cg3_post_load, 339 .fields = (VMStateField[]) { 340 VMSTATE_UINT16(height, CG3State), 341 VMSTATE_UINT16(width, CG3State), 342 VMSTATE_UINT16(depth, CG3State), 343 VMSTATE_BUFFER(r, CG3State), 344 VMSTATE_BUFFER(g, CG3State), 345 VMSTATE_BUFFER(b, CG3State), 346 VMSTATE_UINT8(dac_index, CG3State), 347 VMSTATE_UINT8(dac_state, CG3State), 348 VMSTATE_END_OF_LIST() 349 } 350 }; 351 352 static void cg3_reset(DeviceState *d) 353 { 354 CG3State *s = CG3(d); 355 356 /* Initialize palette */ 357 memset(s->r, 0, 256); 358 memset(s->g, 0, 256); 359 memset(s->b, 0, 256); 360 361 s->dac_state = 0; 362 s->full_update = 1; 363 qemu_irq_lower(s->irq); 364 } 365 366 static Property cg3_properties[] = { 367 DEFINE_PROP_UINT32("vram-size", CG3State, vram_size, -1), 368 DEFINE_PROP_UINT16("width", CG3State, width, -1), 369 DEFINE_PROP_UINT16("height", CG3State, height, -1), 370 DEFINE_PROP_UINT16("depth", CG3State, depth, -1), 371 DEFINE_PROP_END_OF_LIST(), 372 }; 373 374 static void cg3_class_init(ObjectClass *klass, void *data) 375 { 376 DeviceClass *dc = DEVICE_CLASS(klass); 377 378 dc->realize = cg3_realizefn; 379 dc->reset = cg3_reset; 380 dc->vmsd = &vmstate_cg3; 381 dc->props = cg3_properties; 382 } 383 384 static const TypeInfo cg3_info = { 385 .name = TYPE_CG3, 386 .parent = TYPE_SYS_BUS_DEVICE, 387 .instance_size = sizeof(CG3State), 388 .instance_init = cg3_initfn, 389 .class_init = cg3_class_init, 390 }; 391 392 static void cg3_register_types(void) 393 { 394 type_register_static(&cg3_info); 395 } 396 397 type_init(cg3_register_types) 398