xref: /openbmc/qemu/hw/display/ati_regs.h (revision ed75658a)
1  /*
2   * ATI VGA register definitions
3   *
4   * based on:
5   * linux/include/video/aty128.h
6   *     Register definitions for ATI Rage128 boards
7   *     Anthony Tong <atong@uiuc.edu>, 1999
8   *     Brad Douglas <brad@neruo.com>, 2000
9   *
10   * and linux/include/video/radeon.h
11   *
12   * This work is licensed under the GNU GPL license version 2.
13   */
14  
15  /*
16   * Register mapping:
17   * 0x0000-0x00ff Misc regs also accessible via io and mmio space
18   * 0x0100-0x0eff Misc regs only accessible via mmio
19   * 0x0f00-0x0fff Read-only copy of PCI config regs
20   * 0x1000-0x13ff Concurrent Command Engine (CCE) regs
21   * 0x1400-0x1fff GUI (drawing engine) regs
22   */
23  
24  #ifndef ATI_REGS_H
25  #define ATI_REGS_H
26  
27  #undef DEFAULT_PITCH /* needed for mingw builds */
28  
29  #define MM_INDEX                                0x0000
30  #define MM_DATA                                 0x0004
31  #define CLOCK_CNTL_INDEX                        0x0008
32  #define CLOCK_CNTL_DATA                         0x000c
33  #define BIOS_0_SCRATCH                          0x0010
34  #define BUS_CNTL                                0x0030
35  #define BUS_CNTL1                               0x0034
36  #define GEN_INT_CNTL                            0x0040
37  #define GEN_INT_STATUS                          0x0044
38  #define CRTC_GEN_CNTL                           0x0050
39  #define CRTC_EXT_CNTL                           0x0054
40  #define DAC_CNTL                                0x0058
41  #define GPIO_VGA_DDC                            0x0060
42  #define GPIO_DVI_DDC                            0x0064
43  #define GPIO_MONID                              0x0068
44  #define I2C_CNTL_1                              0x0094
45  #define AMCGPIO_MASK_MIR                        0x009c
46  #define AMCGPIO_A_MIR                           0x00a0
47  #define AMCGPIO_Y_MIR                           0x00a4
48  #define AMCGPIO_EN_MIR                          0x00a8
49  #define PALETTE_INDEX                           0x00b0
50  #define PALETTE_DATA                            0x00b4
51  #define PALETTE_30_DATA                         0x00b8
52  #define CNFG_CNTL                               0x00e0
53  #define GEN_RESET_CNTL                          0x00f0
54  #define CNFG_MEMSIZE                            0x00f8
55  #define CONFIG_APER_0_BASE                      0x0100
56  #define CONFIG_APER_1_BASE                      0x0104
57  #define CONFIG_APER_SIZE                        0x0108
58  #define CONFIG_REG_1_BASE                       0x010c
59  #define CONFIG_REG_APER_SIZE                    0x0110
60  #define HOST_PATH_CNTL                          0x0130
61  #define MEM_CNTL                                0x0140
62  #define MC_FB_LOCATION                          0x0148
63  #define MC_AGP_LOCATION                         0x014C
64  #define MC_STATUS                               0x0150
65  #define MEM_SDRAM_MODE_REG                      0x0158
66  #define MEM_POWER_MISC                          0x015c
67  #define AGP_BASE                                0x0170
68  #define AGP_CNTL                                0x0174
69  #define AGP_APER_OFFSET                         0x0178
70  #define PCI_GART_PAGE                           0x017c
71  #define PC_NGUI_MODE                            0x0180
72  #define PC_NGUI_CTLSTAT                         0x0184
73  #define MPP_TB_CONFIG                           0x01C0
74  #define MPP_GP_CONFIG                           0x01C8
75  #define VIPH_CONTROL                            0x01D0
76  #define CRTC_H_TOTAL_DISP                       0x0200
77  #define CRTC_H_SYNC_STRT_WID                    0x0204
78  #define CRTC_V_TOTAL_DISP                       0x0208
79  #define CRTC_V_SYNC_STRT_WID                    0x020c
80  #define CRTC_VLINE_CRNT_VLINE                   0x0210
81  #define CRTC_CRNT_FRAME                         0x0214
82  #define CRTC_GUI_TRIG_VLINE                     0x0218
83  #define CRTC_OFFSET                             0x0224
84  #define CRTC_OFFSET_CNTL                        0x0228
85  #define CRTC_PITCH                              0x022c
86  #define OVR_CLR                                 0x0230
87  #define OVR_WID_LEFT_RIGHT                      0x0234
88  #define OVR_WID_TOP_BOTTOM                      0x0238
89  #define CUR_OFFSET                              0x0260
90  #define CUR_HORZ_VERT_POSN                      0x0264
91  #define CUR_HORZ_VERT_OFF                       0x0268
92  #define CUR_CLR0                                0x026c
93  #define CUR_CLR1                                0x0270
94  #define LVDS_GEN_CNTL                           0x02d0
95  #define DDA_CONFIG                              0x02e0
96  #define DDA_ON_OFF                              0x02e4
97  #define VGA_DDA_CONFIG                          0x02e8
98  #define VGA_DDA_ON_OFF                          0x02ec
99  #define CRTC2_H_TOTAL_DISP                      0x0300
100  #define CRTC2_H_SYNC_STRT_WID                   0x0304
101  #define CRTC2_V_TOTAL_DISP                      0x0308
102  #define CRTC2_V_SYNC_STRT_WID                   0x030c
103  #define CRTC2_VLINE_CRNT_VLINE                  0x0310
104  #define CRTC2_CRNT_FRAME                        0x0314
105  #define CRTC2_GUI_TRIG_VLINE                    0x0318
106  #define CRTC2_OFFSET                            0x0324
107  #define CRTC2_OFFSET_CNTL                       0x0328
108  #define CRTC2_PITCH                             0x032c
109  #define DDA2_CONFIG                             0x03e0
110  #define DDA2_ON_OFF                             0x03e4
111  #define CRTC2_GEN_CNTL                          0x03f8
112  #define CRTC2_STATUS                            0x03fc
113  #define OV0_SCALE_CNTL                          0x0420
114  #define SUBPIC_CNTL                             0x0540
115  #define PM4_BUFFER_OFFSET                       0x0700
116  #define PM4_BUFFER_CNTL                         0x0704
117  #define PM4_BUFFER_WM_CNTL                      0x0708
118  #define PM4_BUFFER_DL_RPTR_ADDR                 0x070c
119  #define PM4_BUFFER_DL_RPTR                      0x0710
120  #define PM4_BUFFER_DL_WPTR                      0x0714
121  #define PM4_VC_FPU_SETUP                        0x071c
122  #define PM4_FPU_CNTL                            0x0720
123  #define PM4_VC_FORMAT                           0x0724
124  #define PM4_VC_CNTL                             0x0728
125  #define PM4_VC_I01                              0x072c
126  #define PM4_VC_VLOFF                            0x0730
127  #define PM4_VC_VLSIZE                           0x0734
128  #define PM4_IW_INDOFF                           0x0738
129  #define PM4_IW_INDSIZE                          0x073c
130  #define PM4_FPU_FPX0                            0x0740
131  #define PM4_FPU_FPY0                            0x0744
132  #define PM4_FPU_FPX1                            0x0748
133  #define PM4_FPU_FPY1                            0x074c
134  #define PM4_FPU_FPX2                            0x0750
135  #define PM4_FPU_FPY2                            0x0754
136  #define PM4_FPU_FPY3                            0x0758
137  #define PM4_FPU_FPY4                            0x075c
138  #define PM4_FPU_FPY5                            0x0760
139  #define PM4_FPU_FPY6                            0x0764
140  #define PM4_FPU_FPR                             0x0768
141  #define PM4_FPU_FPG                             0x076c
142  #define PM4_FPU_FPB                             0x0770
143  #define PM4_FPU_FPA                             0x0774
144  #define PM4_FPU_INTXY0                          0x0780
145  #define PM4_FPU_INTXY1                          0x0784
146  #define PM4_FPU_INTXY2                          0x0788
147  #define PM4_FPU_INTARGB                         0x078c
148  #define PM4_FPU_FPTWICEAREA                     0x0790
149  #define PM4_FPU_DMAJOR01                        0x0794
150  #define PM4_FPU_DMAJOR12                        0x0798
151  #define PM4_FPU_DMAJOR02                        0x079c
152  #define PM4_FPU_STAT                            0x07a0
153  #define PM4_STAT                                0x07b8
154  #define PM4_TEST_CNTL                           0x07d0
155  #define PM4_MICROCODE_ADDR                      0x07d4
156  #define PM4_MICROCODE_RADDR                     0x07d8
157  #define PM4_MICROCODE_DATAH                     0x07dc
158  #define PM4_MICROCODE_DATAL                     0x07e0
159  #define PM4_CMDFIFO_ADDR                        0x07e4
160  #define PM4_CMDFIFO_DATAH                       0x07e8
161  #define PM4_CMDFIFO_DATAL                       0x07ec
162  #define PM4_BUFFER_ADDR                         0x07f0
163  #define PM4_BUFFER_DATAH                        0x07f4
164  #define PM4_BUFFER_DATAL                        0x07f8
165  #define PM4_MICRO_CNTL                          0x07fc
166  #define CAP0_TRIG_CNTL                          0x0950
167  #define CAP1_TRIG_CNTL                          0x09c0
168  
169  #define RBBM_STATUS                             0x0e40
170  
171  /*
172   * GUI Block Memory Mapped Registers
173   * These registers are FIFOed.
174   */
175  #define PM4_FIFO_DATA_EVEN                      0x1000
176  #define PM4_FIFO_DATA_ODD                       0x1004
177  
178  #define DST_OFFSET                              0x1404
179  #define DST_PITCH                               0x1408
180  #define DST_WIDTH                               0x140c
181  #define DST_HEIGHT                              0x1410
182  #define SRC_X                                   0x1414
183  #define SRC_Y                                   0x1418
184  #define DST_X                                   0x141c
185  #define DST_Y                                   0x1420
186  #define SRC_PITCH_OFFSET                        0x1428
187  #define DST_PITCH_OFFSET                        0x142c
188  #define SRC_Y_X                                 0x1434
189  #define DST_Y_X                                 0x1438
190  #define DST_HEIGHT_WIDTH                        0x143c
191  #define DP_GUI_MASTER_CNTL                      0x146c
192  #define BRUSH_SCALE                             0x1470
193  #define BRUSH_Y_X                               0x1474
194  #define DP_BRUSH_BKGD_CLR                       0x1478
195  #define DP_BRUSH_FRGD_CLR                       0x147c
196  #define DST_WIDTH_X                             0x1588
197  #define DST_HEIGHT_WIDTH_8                      0x158c
198  #define SRC_X_Y                                 0x1590
199  #define DST_X_Y                                 0x1594
200  #define DST_WIDTH_HEIGHT                        0x1598
201  #define DST_WIDTH_X_INCY                        0x159c
202  #define DST_HEIGHT_Y                            0x15a0
203  #define DST_X_SUB                               0x15a4
204  #define DST_Y_SUB                               0x15a8
205  #define SRC_OFFSET                              0x15ac
206  #define SRC_PITCH                               0x15b0
207  #define DST_HEIGHT_WIDTH_BW                     0x15b4
208  #define CLR_CMP_CNTL                            0x15c0
209  #define CLR_CMP_CLR_SRC                         0x15c4
210  #define CLR_CMP_CLR_DST                         0x15c8
211  #define CLR_CMP_MASK                            0x15cc
212  #define DP_SRC_FRGD_CLR                         0x15d8
213  #define DP_SRC_BKGD_CLR                         0x15dc
214  #define DST_BRES_ERR                            0x1628
215  #define DST_BRES_INC                            0x162c
216  #define DST_BRES_DEC                            0x1630
217  #define DST_BRES_LNTH                           0x1634
218  #define DST_BRES_LNTH_SUB                       0x1638
219  #define SC_LEFT                                 0x1640
220  #define SC_RIGHT                                0x1644
221  #define SC_TOP                                  0x1648
222  #define SC_BOTTOM                               0x164c
223  #define SRC_SC_RIGHT                            0x1654
224  #define SRC_SC_BOTTOM                           0x165c
225  #define GUI_DEBUG0                              0x16a0
226  #define GUI_DEBUG1                              0x16a4
227  #define GUI_TIMEOUT                             0x16b0
228  #define GUI_TIMEOUT0                            0x16b4
229  #define GUI_TIMEOUT1                            0x16b8
230  #define GUI_PROBE                               0x16bc
231  #define DP_CNTL                                 0x16c0
232  #define DP_DATATYPE                             0x16c4
233  #define DP_MIX                                  0x16c8
234  #define DP_WRITE_MASK                           0x16cc
235  #define DP_CNTL_XDIR_YDIR_YMAJOR                0x16d0
236  #define DEFAULT_OFFSET                          0x16e0
237  #define DEFAULT_PITCH                           0x16e4
238  #define DEFAULT_SC_BOTTOM_RIGHT                 0x16e8
239  #define SC_TOP_LEFT                             0x16ec
240  #define SC_BOTTOM_RIGHT                         0x16f0
241  #define SRC_SC_BOTTOM_RIGHT                     0x16f4
242  #define DST_TILE                                0x1700
243  #define WAIT_UNTIL                              0x1720
244  #define CACHE_CNTL                              0x1724
245  #define GUI_STAT                                0x1740
246  #define PC_GUI_MODE                             0x1744
247  #define PC_GUI_CTLSTAT                          0x1748
248  #define PC_DEBUG_MODE                           0x1760
249  #define BRES_DST_ERR_DEC                        0x1780
250  #define TRAIL_BRES_T12_ERR_DEC                  0x1784
251  #define TRAIL_BRES_T12_INC                      0x1788
252  #define DP_T12_CNTL                             0x178c
253  #define DST_BRES_T1_LNTH                        0x1790
254  #define DST_BRES_T2_LNTH                        0x1794
255  #define SCALE_SRC_HEIGHT_WIDTH                  0x1994
256  #define SCALE_OFFSET_0                          0x1998
257  #define SCALE_PITCH                             0x199c
258  #define SCALE_X_INC                             0x19a0
259  #define SCALE_Y_INC                             0x19a4
260  #define SCALE_HACC                              0x19a8
261  #define SCALE_VACC                              0x19ac
262  #define SCALE_DST_X_Y                           0x19b0
263  #define SCALE_DST_HEIGHT_WIDTH                  0x19b4
264  #define SCALE_3D_CNTL                           0x1a00
265  #define SCALE_3D_DATATYPE                       0x1a20
266  #define SETUP_CNTL                              0x1bc4
267  #define SOLID_COLOR                             0x1bc8
268  #define WINDOW_XY_OFFSET                        0x1bcc
269  #define DRAW_LINE_POINT                         0x1bd0
270  #define SETUP_CNTL_PM4                          0x1bd4
271  #define DST_PITCH_OFFSET_C                      0x1c80
272  #define DP_GUI_MASTER_CNTL_C                    0x1c84
273  #define SC_TOP_LEFT_C                           0x1c88
274  #define SC_BOTTOM_RIGHT_C                       0x1c8c
275  
276  #define CLR_CMP_MASK_3D                         0x1A28
277  #define MISC_3D_STATE_CNTL_REG                  0x1CA0
278  #define MC_SRC1_CNTL                            0x19D8
279  #define TEX_CNTL                                0x1800
280  
281  /* CONSTANTS */
282  #define GUI_ACTIVE                              0x80000000
283  #define ENGINE_IDLE                             0x0
284  
285  #define PLL_WR_EN                               0x00000080
286  
287  #define CLK_PIN_CNTL                            0x01
288  #define PPLL_CNTL                               0x02
289  #define PPLL_REF_DIV                            0x03
290  #define PPLL_DIV_0                              0x04
291  #define PPLL_DIV_1                              0x05
292  #define PPLL_DIV_2                              0x06
293  #define PPLL_DIV_3                              0x07
294  #define VCLK_ECP_CNTL                           0x08
295  #define HTOTAL_CNTL                             0x09
296  #define X_MPLL_REF_FB_DIV                       0x0a
297  #define XPLL_CNTL                               0x0b
298  #define XDLL_CNTL                               0x0c
299  #define XCLK_CNTL                               0x0d
300  #define MPLL_CNTL                               0x0e
301  #define MCLK_CNTL                               0x0f
302  #define AGP_PLL_CNTL                            0x10
303  #define FCP_CNTL                                0x12
304  #define PLL_TEST_CNTL                           0x13
305  #define P2PLL_CNTL                              0x2a
306  #define P2PLL_REF_DIV                           0x2b
307  #define P2PLL_DIV_0                             0x2b
308  #define POWER_MANAGEMENT                        0x2f
309  
310  #define PPLL_RESET                              0x00000001
311  #define PPLL_ATOMIC_UPDATE_EN                   0x00010000
312  #define PPLL_VGA_ATOMIC_UPDATE_EN               0x00020000
313  #define PPLL_REF_DIV_MASK                       0x000003FF
314  #define PPLL_FB3_DIV_MASK                       0x000007FF
315  #define PPLL_POST3_DIV_MASK                     0x00070000
316  #define PPLL_ATOMIC_UPDATE_R                    0x00008000
317  #define PPLL_ATOMIC_UPDATE_W                    0x00008000
318  #define MEM_CFG_TYPE_MASK                       0x00000003
319  #define XCLK_SRC_SEL_MASK                       0x00000007
320  #define XPLL_FB_DIV_MASK                        0x0000FF00
321  #define X_MPLL_REF_DIV_MASK                     0x000000FF
322  
323  /* GEN_INT_CNTL) */
324  #define CRTC_VBLANK_INT                         0x00000001
325  #define CRTC_VLINE_INT                          0x00000002
326  #define CRTC_VSYNC_INT                          0x00000004
327  
328  /* Config control values (CONFIG_CNTL) */
329  #define APER_0_ENDIAN                           0x00000003
330  #define APER_1_ENDIAN                           0x0000000c
331  #define CFG_VGA_IO_DIS                          0x00000400
332  
333  /* CRTC control values (CRTC_GEN_CNTL) */
334  #define CRTC_CSYNC_EN                           0x00000010
335  
336  #define CRTC2_DBL_SCAN_EN                       0x00000001
337  #define CRTC2_DISPLAY_DIS                       0x00800000
338  #define CRTC2_FIFO_EXTSENSE                     0x00200000
339  #define CRTC2_ICON_EN                           0x00100000
340  #define CRTC2_CUR_EN                            0x00010000
341  #define CRTC2_EXT_DISP_EN                       0x01000000
342  #define CRTC2_EN                                0x02000000
343  #define CRTC2_DISP_REQ_EN_B                     0x04000000
344  
345  #define CRTC_PIX_WIDTH_MASK                     0x00000700
346  #define CRTC_PIX_WIDTH_4BPP                     0x00000100
347  #define CRTC_PIX_WIDTH_8BPP                     0x00000200
348  #define CRTC_PIX_WIDTH_15BPP                    0x00000300
349  #define CRTC_PIX_WIDTH_16BPP                    0x00000400
350  #define CRTC_PIX_WIDTH_24BPP                    0x00000500
351  #define CRTC_PIX_WIDTH_32BPP                    0x00000600
352  
353  /* DAC_CNTL bit constants */
354  #define DAC_8BIT_EN                             0x00000100
355  #define DAC_MASK                                0xFF000000
356  #define DAC_BLANKING                            0x00000004
357  #define DAC_RANGE_CNTL                          0x00000003
358  #define DAC_CLK_SEL                             0x00000010
359  #define DAC_PALETTE_ACCESS_CNTL                 0x00000020
360  #define DAC_PALETTE2_SNOOP_EN                   0x00000040
361  #define DAC_PDWN                                0x00008000
362  
363  /* CRTC_EXT_CNTL */
364  #define CRT_CRTC_DISPLAY_DIS                    0x00000400
365  #define CRT_CRTC_ON                             0x00008000
366  
367  /* GEN_RESET_CNTL bit constants */
368  #define SOFT_RESET_GUI                          0x00000001
369  #define SOFT_RESET_VCLK                         0x00000100
370  #define SOFT_RESET_PCLK                         0x00000200
371  #define SOFT_RESET_ECP                          0x00000400
372  #define SOFT_RESET_DISPENG_XCLK                 0x00000800
373  
374  /* PC_GUI_CTLSTAT bit constants */
375  #define PC_BUSY_INIT                            0x10000000
376  #define PC_BUSY_GUI                             0x20000000
377  #define PC_BUSY_NGUI                            0x40000000
378  #define PC_BUSY                                 0x80000000
379  
380  #define BUS_MASTER_DIS                          0x00000040
381  #define PM4_BUFFER_CNTL_NONPM4                  0x00000000
382  
383  /* DP_DATATYPE bit constants */
384  #define DST_8BPP                                0x00000002
385  #define DST_15BPP                               0x00000003
386  #define DST_16BPP                               0x00000004
387  #define DST_24BPP                               0x00000005
388  #define DST_32BPP                               0x00000006
389  
390  #define BRUSH_SOLIDCOLOR                        0x00000d00
391  
392  /* DP_GUI_MASTER_CNTL bit constants */
393  #define GMC_SRC_PITCH_OFFSET_CNTL               0x00000001
394  #define GMC_DST_PITCH_OFFSET_CNTL               0x00000002
395  #define GMC_SRC_CLIP_DEFAULT                    0x00000000
396  #define GMC_DST_CLIP_DEFAULT                    0x00000000
397  #define GMC_BRUSH_SOLIDCOLOR                    0x000000d0
398  #define GMC_SRC_DSTCOLOR                        0x00003000
399  #define GMC_BYTE_ORDER_MSB_TO_LSB               0x00000000
400  #define GMC_DP_SRC_RECT                         0x02000000
401  #define GMC_3D_FCN_EN_CLR                       0x00000000
402  #define GMC_AUX_CLIP_CLEAR                      0x20000000
403  #define GMC_DST_CLR_CMP_FCN_CLEAR               0x10000000
404  #define GMC_WRITE_MASK_SET                      0x40000000
405  #define GMC_DP_CONVERSION_TEMP_6500             0x00000000
406  
407  /* DP_GUI_MASTER_CNTL ROP3 named constants */
408  #define GMC_ROP3_MASK                           0x00ff0000
409  #define ROP3_BLACKNESS                          0x00000000
410  #define ROP3_SRCCOPY                            0x00cc0000
411  #define ROP3_PATCOPY                            0x00f00000
412  #define ROP3_WHITENESS                          0x00ff0000
413  
414  #define SRC_DSTCOLOR                            0x00030000
415  
416  /* DP_CNTL bit constants */
417  #define DST_X_RIGHT_TO_LEFT                     0x00000000
418  #define DST_X_LEFT_TO_RIGHT                     0x00000001
419  #define DST_Y_BOTTOM_TO_TOP                     0x00000000
420  #define DST_Y_TOP_TO_BOTTOM                     0x00000002
421  #define DST_X_MAJOR                             0x00000000
422  #define DST_Y_MAJOR                             0x00000004
423  #define DST_X_TILE                              0x00000008
424  #define DST_Y_TILE                              0x00000010
425  #define DST_LAST_PEL                            0x00000020
426  #define DST_TRAIL_X_RIGHT_TO_LEFT               0x00000000
427  #define DST_TRAIL_X_LEFT_TO_RIGHT               0x00000040
428  #define DST_TRAP_FILL_RIGHT_TO_LEFT             0x00000000
429  #define DST_TRAP_FILL_LEFT_TO_RIGHT             0x00000080
430  #define DST_BRES_SIGN                           0x00000100
431  #define DST_HOST_BIG_ENDIAN_EN                  0x00000200
432  #define DST_POLYLINE_NONLAST                    0x00008000
433  #define DST_RASTER_STALL                        0x00010000
434  #define DST_POLY_EDGE                           0x00040000
435  
436  /* DP_MIX bit constants */
437  #define DP_SRC_RECT                             0x00000200
438  #define DP_SRC_HOST                             0x00000300
439  #define DP_SRC_HOST_BYTEALIGN                   0x00000400
440  
441  /* LVDS_GEN_CNTL constants */
442  #define LVDS_BL_MOD_LEVEL_MASK                  0x0000ff00
443  #define LVDS_BL_MOD_LEVEL_SHIFT                 8
444  #define LVDS_BL_MOD_EN                          0x00010000
445  #define LVDS_DIGION                             0x00040000
446  #define LVDS_BLON                               0x00080000
447  #define LVDS_ON                                 0x00000001
448  #define LVDS_DISPLAY_DIS                        0x00000002
449  #define LVDS_PANEL_TYPE_2PIX_PER_CLK            0x00000004
450  #define LVDS_PANEL_24BITS_TFT                   0x00000008
451  #define LVDS_FRAME_MOD_NO                       0x00000000
452  #define LVDS_FRAME_MOD_2_LEVELS                 0x00000010
453  #define LVDS_FRAME_MOD_4_LEVELS                 0x00000020
454  #define LVDS_RST_FM                             0x00000040
455  #define LVDS_EN                                 0x00000080
456  
457  /* CRTC2_GEN_CNTL constants */
458  #define CRTC2_EN                                0x02000000
459  
460  /* POWER_MANAGEMENT constants */
461  #define PWR_MGT_ON                              0x00000001
462  #define PWR_MGT_MODE_MASK                       0x00000006
463  #define PWR_MGT_MODE_PIN                        0x00000000
464  #define PWR_MGT_MODE_REGISTER                   0x00000002
465  #define PWR_MGT_MODE_TIMER                      0x00000004
466  #define PWR_MGT_MODE_PCI                        0x00000006
467  #define PWR_MGT_AUTO_PWR_UP_EN                  0x00000008
468  #define PWR_MGT_ACTIVITY_PIN_ON                 0x00000010
469  #define PWR_MGT_STANDBY_POL                     0x00000020
470  #define PWR_MGT_SUSPEND_POL                     0x00000040
471  #define PWR_MGT_SELF_REFRESH                    0x00000080
472  #define PWR_MGT_ACTIVITY_PIN_EN                 0x00000100
473  #define PWR_MGT_KEYBD_SNOOP                     0x00000200
474  #define PWR_MGT_TRISTATE_MEM_EN                 0x00000800
475  #define PWR_MGT_SELW4MS                         0x00001000
476  #define PWR_MGT_SLOWDOWN_MCLK                   0x00002000
477  
478  #define PMI_PMSCR_REG                           0x60
479  
480  /* used by ATI bug fix for hardware ROM */
481  #define RAGE128_MPP_TB_CONFIG                   0x01c0
482  
483  #endif /* ATI_REGS_H */
484