1 /* 2 * ATI VGA register definitions 3 * 4 * based on: 5 * linux/include/video/aty128.h 6 * Register definitions for ATI Rage128 boards 7 * Anthony Tong <atong@uiuc.edu>, 1999 8 * Brad Douglas <brad@neruo.com>, 2000 9 * 10 * and linux/include/video/radeon.h 11 * 12 * This work is licensed under the GNU GPL license version 2. 13 */ 14 15 /* 16 * Register mapping: 17 * 0x0000-0x00ff Misc regs also accessible via io and mmio space 18 * 0x0100-0x0eff Misc regs only accessible via mmio 19 * 0x0f00-0x0fff Read-only copy of PCI config regs 20 * 0x1000-0x13ff Concurrent Command Engine (CCE) regs 21 * 0x1400-0x1fff GUI (drawing engine) regs 22 */ 23 24 #ifndef ATI_REGS_H 25 #define ATI_REGS_H 26 27 #undef DEFAULT_PITCH /* needed for mingw builds */ 28 29 #define MM_INDEX 0x0000 30 #define MM_DATA 0x0004 31 #define CLOCK_CNTL_INDEX 0x0008 32 #define CLOCK_CNTL_DATA 0x000c 33 #define BIOS_0_SCRATCH 0x0010 34 #define BUS_CNTL 0x0030 35 #define BUS_CNTL1 0x0034 36 #define GEN_INT_CNTL 0x0040 37 #define CRTC_GEN_CNTL 0x0050 38 #define CRTC_EXT_CNTL 0x0054 39 #define DAC_CNTL 0x0058 40 #define GPIO_VGA_DDC 0x0060 41 #define GPIO_DVI_DDC 0x0064 42 #define GPIO_MONID 0x0068 43 #define I2C_CNTL_1 0x0094 44 #define PALETTE_INDEX 0x00b0 45 #define PALETTE_DATA 0x00b4 46 #define CNFG_CNTL 0x00e0 47 #define GEN_RESET_CNTL 0x00f0 48 #define CNFG_MEMSIZE 0x00f8 49 #define MEM_CNTL 0x0140 50 #define MC_FB_LOCATION 0x0148 51 #define MC_AGP_LOCATION 0x014C 52 #define MC_STATUS 0x0150 53 #define MEM_POWER_MISC 0x015c 54 #define AGP_BASE 0x0170 55 #define AGP_CNTL 0x0174 56 #define AGP_APER_OFFSET 0x0178 57 #define PCI_GART_PAGE 0x017c 58 #define PC_NGUI_MODE 0x0180 59 #define PC_NGUI_CTLSTAT 0x0184 60 #define MPP_TB_CONFIG 0x01C0 61 #define MPP_GP_CONFIG 0x01C8 62 #define VIPH_CONTROL 0x01D0 63 #define CRTC_H_TOTAL_DISP 0x0200 64 #define CRTC_H_SYNC_STRT_WID 0x0204 65 #define CRTC_V_TOTAL_DISP 0x0208 66 #define CRTC_V_SYNC_STRT_WID 0x020c 67 #define CRTC_VLINE_CRNT_VLINE 0x0210 68 #define CRTC_CRNT_FRAME 0x0214 69 #define CRTC_GUI_TRIG_VLINE 0x0218 70 #define CRTC_OFFSET 0x0224 71 #define CRTC_OFFSET_CNTL 0x0228 72 #define CRTC_PITCH 0x022c 73 #define OVR_CLR 0x0230 74 #define OVR_WID_LEFT_RIGHT 0x0234 75 #define OVR_WID_TOP_BOTTOM 0x0238 76 #define CUR_OFFSET 0x0260 77 #define CUR_HORZ_VERT_POSN 0x0264 78 #define CUR_HORZ_VERT_OFF 0x0268 79 #define CUR_CLR0 0x026c 80 #define CUR_CLR1 0x0270 81 #define LVDS_GEN_CNTL 0x02d0 82 #define DDA_CONFIG 0x02e0 83 #define DDA_ON_OFF 0x02e4 84 #define VGA_DDA_CONFIG 0x02e8 85 #define VGA_DDA_ON_OFF 0x02ec 86 #define CRTC2_H_TOTAL_DISP 0x0300 87 #define CRTC2_H_SYNC_STRT_WID 0x0304 88 #define CRTC2_V_TOTAL_DISP 0x0308 89 #define CRTC2_V_SYNC_STRT_WID 0x030c 90 #define CRTC2_VLINE_CRNT_VLINE 0x0310 91 #define CRTC2_CRNT_FRAME 0x0314 92 #define CRTC2_GUI_TRIG_VLINE 0x0318 93 #define CRTC2_OFFSET 0x0324 94 #define CRTC2_OFFSET_CNTL 0x0328 95 #define CRTC2_PITCH 0x032c 96 #define DDA2_CONFIG 0x03e0 97 #define DDA2_ON_OFF 0x03e4 98 #define CRTC2_GEN_CNTL 0x03f8 99 #define CRTC2_STATUS 0x03fc 100 #define OV0_SCALE_CNTL 0x0420 101 #define SUBPIC_CNTL 0x0540 102 #define PM4_BUFFER_OFFSET 0x0700 103 #define PM4_BUFFER_CNTL 0x0704 104 #define PM4_BUFFER_WM_CNTL 0x0708 105 #define PM4_BUFFER_DL_RPTR_ADDR 0x070c 106 #define PM4_BUFFER_DL_RPTR 0x0710 107 #define PM4_BUFFER_DL_WPTR 0x0714 108 #define PM4_VC_FPU_SETUP 0x071c 109 #define PM4_FPU_CNTL 0x0720 110 #define PM4_VC_FORMAT 0x0724 111 #define PM4_VC_CNTL 0x0728 112 #define PM4_VC_I01 0x072c 113 #define PM4_VC_VLOFF 0x0730 114 #define PM4_VC_VLSIZE 0x0734 115 #define PM4_IW_INDOFF 0x0738 116 #define PM4_IW_INDSIZE 0x073c 117 #define PM4_FPU_FPX0 0x0740 118 #define PM4_FPU_FPY0 0x0744 119 #define PM4_FPU_FPX1 0x0748 120 #define PM4_FPU_FPY1 0x074c 121 #define PM4_FPU_FPX2 0x0750 122 #define PM4_FPU_FPY2 0x0754 123 #define PM4_FPU_FPY3 0x0758 124 #define PM4_FPU_FPY4 0x075c 125 #define PM4_FPU_FPY5 0x0760 126 #define PM4_FPU_FPY6 0x0764 127 #define PM4_FPU_FPR 0x0768 128 #define PM4_FPU_FPG 0x076c 129 #define PM4_FPU_FPB 0x0770 130 #define PM4_FPU_FPA 0x0774 131 #define PM4_FPU_INTXY0 0x0780 132 #define PM4_FPU_INTXY1 0x0784 133 #define PM4_FPU_INTXY2 0x0788 134 #define PM4_FPU_INTARGB 0x078c 135 #define PM4_FPU_FPTWICEAREA 0x0790 136 #define PM4_FPU_DMAJOR01 0x0794 137 #define PM4_FPU_DMAJOR12 0x0798 138 #define PM4_FPU_DMAJOR02 0x079c 139 #define PM4_FPU_STAT 0x07a0 140 #define PM4_STAT 0x07b8 141 #define PM4_TEST_CNTL 0x07d0 142 #define PM4_MICROCODE_ADDR 0x07d4 143 #define PM4_MICROCODE_RADDR 0x07d8 144 #define PM4_MICROCODE_DATAH 0x07dc 145 #define PM4_MICROCODE_DATAL 0x07e0 146 #define PM4_CMDFIFO_ADDR 0x07e4 147 #define PM4_CMDFIFO_DATAH 0x07e8 148 #define PM4_CMDFIFO_DATAL 0x07ec 149 #define PM4_BUFFER_ADDR 0x07f0 150 #define PM4_BUFFER_DATAH 0x07f4 151 #define PM4_BUFFER_DATAL 0x07f8 152 #define PM4_MICRO_CNTL 0x07fc 153 #define CAP0_TRIG_CNTL 0x0950 154 #define CAP1_TRIG_CNTL 0x09c0 155 156 #define RBBM_STATUS 0x0e40 157 158 /* 159 * GUI Block Memory Mapped Registers 160 * These registers are FIFOed. 161 */ 162 #define PM4_FIFO_DATA_EVEN 0x1000 163 #define PM4_FIFO_DATA_ODD 0x1004 164 165 #define DST_OFFSET 0x1404 166 #define DST_PITCH 0x1408 167 #define DST_WIDTH 0x140c 168 #define DST_HEIGHT 0x1410 169 #define SRC_X 0x1414 170 #define SRC_Y 0x1418 171 #define DST_X 0x141c 172 #define DST_Y 0x1420 173 #define SRC_PITCH_OFFSET 0x1428 174 #define DST_PITCH_OFFSET 0x142c 175 #define SRC_Y_X 0x1434 176 #define DST_Y_X 0x1438 177 #define DST_HEIGHT_WIDTH 0x143c 178 #define DP_GUI_MASTER_CNTL 0x146c 179 #define BRUSH_SCALE 0x1470 180 #define BRUSH_Y_X 0x1474 181 #define DP_BRUSH_BKGD_CLR 0x1478 182 #define DP_BRUSH_FRGD_CLR 0x147c 183 #define DST_WIDTH_X 0x1588 184 #define DST_HEIGHT_WIDTH_8 0x158c 185 #define SRC_X_Y 0x1590 186 #define DST_X_Y 0x1594 187 #define DST_WIDTH_HEIGHT 0x1598 188 #define DST_WIDTH_X_INCY 0x159c 189 #define DST_HEIGHT_Y 0x15a0 190 #define DST_X_SUB 0x15a4 191 #define DST_Y_SUB 0x15a8 192 #define SRC_OFFSET 0x15ac 193 #define SRC_PITCH 0x15b0 194 #define DST_HEIGHT_WIDTH_BW 0x15b4 195 #define CLR_CMP_CNTL 0x15c0 196 #define CLR_CMP_CLR_SRC 0x15c4 197 #define CLR_CMP_CLR_DST 0x15c8 198 #define CLR_CMP_MASK 0x15cc 199 #define DP_SRC_FRGD_CLR 0x15d8 200 #define DP_SRC_BKGD_CLR 0x15dc 201 #define DST_BRES_ERR 0x1628 202 #define DST_BRES_INC 0x162c 203 #define DST_BRES_DEC 0x1630 204 #define DST_BRES_LNTH 0x1634 205 #define DST_BRES_LNTH_SUB 0x1638 206 #define SC_LEFT 0x1640 207 #define SC_RIGHT 0x1644 208 #define SC_TOP 0x1648 209 #define SC_BOTTOM 0x164c 210 #define SRC_SC_RIGHT 0x1654 211 #define SRC_SC_BOTTOM 0x165c 212 #define GUI_DEBUG0 0x16a0 213 #define GUI_DEBUG1 0x16a4 214 #define GUI_TIMEOUT 0x16b0 215 #define GUI_TIMEOUT0 0x16b4 216 #define GUI_TIMEOUT1 0x16b8 217 #define GUI_PROBE 0x16bc 218 #define DP_CNTL 0x16c0 219 #define DP_DATATYPE 0x16c4 220 #define DP_MIX 0x16c8 221 #define DP_WRITE_MASK 0x16cc 222 #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 223 #define DEFAULT_OFFSET 0x16e0 224 #define DEFAULT_PITCH 0x16e4 225 #define DEFAULT_SC_BOTTOM_RIGHT 0x16e8 226 #define SC_TOP_LEFT 0x16ec 227 #define SC_BOTTOM_RIGHT 0x16f0 228 #define SRC_SC_BOTTOM_RIGHT 0x16f4 229 #define DST_TILE 0x1700 230 #define WAIT_UNTIL 0x1720 231 #define CACHE_CNTL 0x1724 232 #define GUI_STAT 0x1740 233 #define PC_GUI_MODE 0x1744 234 #define PC_GUI_CTLSTAT 0x1748 235 #define PC_DEBUG_MODE 0x1760 236 #define BRES_DST_ERR_DEC 0x1780 237 #define TRAIL_BRES_T12_ERR_DEC 0x1784 238 #define TRAIL_BRES_T12_INC 0x1788 239 #define DP_T12_CNTL 0x178c 240 #define DST_BRES_T1_LNTH 0x1790 241 #define DST_BRES_T2_LNTH 0x1794 242 #define SCALE_SRC_HEIGHT_WIDTH 0x1994 243 #define SCALE_OFFSET_0 0x1998 244 #define SCALE_PITCH 0x199c 245 #define SCALE_X_INC 0x19a0 246 #define SCALE_Y_INC 0x19a4 247 #define SCALE_HACC 0x19a8 248 #define SCALE_VACC 0x19ac 249 #define SCALE_DST_X_Y 0x19b0 250 #define SCALE_DST_HEIGHT_WIDTH 0x19b4 251 #define SCALE_3D_CNTL 0x1a00 252 #define SCALE_3D_DATATYPE 0x1a20 253 #define SETUP_CNTL 0x1bc4 254 #define SOLID_COLOR 0x1bc8 255 #define WINDOW_XY_OFFSET 0x1bcc 256 #define DRAW_LINE_POINT 0x1bd0 257 #define SETUP_CNTL_PM4 0x1bd4 258 #define DST_PITCH_OFFSET_C 0x1c80 259 #define DP_GUI_MASTER_CNTL_C 0x1c84 260 #define SC_TOP_LEFT_C 0x1c88 261 #define SC_BOTTOM_RIGHT_C 0x1c8c 262 263 #define CLR_CMP_MASK_3D 0x1A28 264 #define MISC_3D_STATE_CNTL_REG 0x1CA0 265 #define MC_SRC1_CNTL 0x19D8 266 #define TEX_CNTL 0x1800 267 268 /* CONSTANTS */ 269 #define GUI_ACTIVE 0x80000000 270 #define ENGINE_IDLE 0x0 271 272 #define PLL_WR_EN 0x00000080 273 274 #define CLK_PIN_CNTL 0x01 275 #define PPLL_CNTL 0x02 276 #define PPLL_REF_DIV 0x03 277 #define PPLL_DIV_0 0x04 278 #define PPLL_DIV_1 0x05 279 #define PPLL_DIV_2 0x06 280 #define PPLL_DIV_3 0x07 281 #define VCLK_ECP_CNTL 0x08 282 #define HTOTAL_CNTL 0x09 283 #define X_MPLL_REF_FB_DIV 0x0a 284 #define XPLL_CNTL 0x0b 285 #define XDLL_CNTL 0x0c 286 #define XCLK_CNTL 0x0d 287 #define MPLL_CNTL 0x0e 288 #define MCLK_CNTL 0x0f 289 #define AGP_PLL_CNTL 0x10 290 #define FCP_CNTL 0x12 291 #define PLL_TEST_CNTL 0x13 292 #define P2PLL_CNTL 0x2a 293 #define P2PLL_REF_DIV 0x2b 294 #define P2PLL_DIV_0 0x2b 295 #define POWER_MANAGEMENT 0x2f 296 297 #define PPLL_RESET 0x00000001 298 #define PPLL_ATOMIC_UPDATE_EN 0x00010000 299 #define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 300 #define PPLL_REF_DIV_MASK 0x000003FF 301 #define PPLL_FB3_DIV_MASK 0x000007FF 302 #define PPLL_POST3_DIV_MASK 0x00070000 303 #define PPLL_ATOMIC_UPDATE_R 0x00008000 304 #define PPLL_ATOMIC_UPDATE_W 0x00008000 305 #define MEM_CFG_TYPE_MASK 0x00000003 306 #define XCLK_SRC_SEL_MASK 0x00000007 307 #define XPLL_FB_DIV_MASK 0x0000FF00 308 #define X_MPLL_REF_DIV_MASK 0x000000FF 309 310 /* Config control values (CONFIG_CNTL) */ 311 #define CFG_VGA_IO_DIS 0x00000400 312 313 /* CRTC control values (CRTC_GEN_CNTL) */ 314 #define CRTC_CSYNC_EN 0x00000010 315 316 #define CRTC2_DBL_SCAN_EN 0x00000001 317 #define CRTC2_DISPLAY_DIS 0x00800000 318 #define CRTC2_FIFO_EXTSENSE 0x00200000 319 #define CRTC2_ICON_EN 0x00100000 320 #define CRTC2_CUR_EN 0x00010000 321 #define CRTC2_EXT_DISP_EN 0x01000000 322 #define CRTC2_EN 0x02000000 323 #define CRTC2_DISP_REQ_EN_B 0x04000000 324 325 #define CRTC_PIX_WIDTH_MASK 0x00000700 326 #define CRTC_PIX_WIDTH_4BPP 0x00000100 327 #define CRTC_PIX_WIDTH_8BPP 0x00000200 328 #define CRTC_PIX_WIDTH_15BPP 0x00000300 329 #define CRTC_PIX_WIDTH_16BPP 0x00000400 330 #define CRTC_PIX_WIDTH_24BPP 0x00000500 331 #define CRTC_PIX_WIDTH_32BPP 0x00000600 332 333 /* DAC_CNTL bit constants */ 334 #define DAC_8BIT_EN 0x00000100 335 #define DAC_MASK 0xFF000000 336 #define DAC_BLANKING 0x00000004 337 #define DAC_RANGE_CNTL 0x00000003 338 #define DAC_CLK_SEL 0x00000010 339 #define DAC_PALETTE_ACCESS_CNTL 0x00000020 340 #define DAC_PALETTE2_SNOOP_EN 0x00000040 341 #define DAC_PDWN 0x00008000 342 343 /* CRTC_EXT_CNTL */ 344 #define CRT_CRTC_DISPLAY_DIS 0x00000400 345 #define CRT_CRTC_ON 0x00008000 346 347 /* GEN_RESET_CNTL bit constants */ 348 #define SOFT_RESET_GUI 0x00000001 349 #define SOFT_RESET_VCLK 0x00000100 350 #define SOFT_RESET_PCLK 0x00000200 351 #define SOFT_RESET_ECP 0x00000400 352 #define SOFT_RESET_DISPENG_XCLK 0x00000800 353 354 /* PC_GUI_CTLSTAT bit constants */ 355 #define PC_BUSY_INIT 0x10000000 356 #define PC_BUSY_GUI 0x20000000 357 #define PC_BUSY_NGUI 0x40000000 358 #define PC_BUSY 0x80000000 359 360 #define BUS_MASTER_DIS 0x00000040 361 #define PM4_BUFFER_CNTL_NONPM4 0x00000000 362 363 /* DP_DATATYPE bit constants */ 364 #define DST_8BPP 0x00000002 365 #define DST_15BPP 0x00000003 366 #define DST_16BPP 0x00000004 367 #define DST_24BPP 0x00000005 368 #define DST_32BPP 0x00000006 369 370 #define BRUSH_SOLIDCOLOR 0x00000d00 371 372 /* DP_GUI_MASTER_CNTL bit constants */ 373 #define GMC_SRC_PITCH_OFFSET_CNTL 0x00000001 374 #define GMC_DST_PITCH_OFFSET_CNTL 0x00000002 375 #define GMC_SRC_CLIP_DEFAULT 0x00000000 376 #define GMC_DST_CLIP_DEFAULT 0x00000000 377 #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 378 #define GMC_SRC_DSTCOLOR 0x00003000 379 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 380 #define GMC_DP_SRC_RECT 0x02000000 381 #define GMC_3D_FCN_EN_CLR 0x00000000 382 #define GMC_AUX_CLIP_CLEAR 0x20000000 383 #define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 384 #define GMC_WRITE_MASK_SET 0x40000000 385 #define GMC_DP_CONVERSION_TEMP_6500 0x00000000 386 387 /* DP_GUI_MASTER_CNTL ROP3 named constants */ 388 #define GMC_ROP3_MASK 0x00ff0000 389 #define ROP3_BLACKNESS 0x00000000 390 #define ROP3_SRCCOPY 0x00cc0000 391 #define ROP3_PATCOPY 0x00f00000 392 #define ROP3_WHITENESS 0x00ff0000 393 394 #define SRC_DSTCOLOR 0x00030000 395 396 /* DP_CNTL bit constants */ 397 #define DST_X_RIGHT_TO_LEFT 0x00000000 398 #define DST_X_LEFT_TO_RIGHT 0x00000001 399 #define DST_Y_BOTTOM_TO_TOP 0x00000000 400 #define DST_Y_TOP_TO_BOTTOM 0x00000002 401 #define DST_X_MAJOR 0x00000000 402 #define DST_Y_MAJOR 0x00000004 403 #define DST_X_TILE 0x00000008 404 #define DST_Y_TILE 0x00000010 405 #define DST_LAST_PEL 0x00000020 406 #define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 407 #define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 408 #define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 409 #define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 410 #define DST_BRES_SIGN 0x00000100 411 #define DST_HOST_BIG_ENDIAN_EN 0x00000200 412 #define DST_POLYLINE_NONLAST 0x00008000 413 #define DST_RASTER_STALL 0x00010000 414 #define DST_POLY_EDGE 0x00040000 415 416 /* DP_MIX bit constants */ 417 #define DP_SRC_RECT 0x00000200 418 #define DP_SRC_HOST 0x00000300 419 #define DP_SRC_HOST_BYTEALIGN 0x00000400 420 421 /* LVDS_GEN_CNTL constants */ 422 #define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 423 #define LVDS_BL_MOD_LEVEL_SHIFT 8 424 #define LVDS_BL_MOD_EN 0x00010000 425 #define LVDS_DIGION 0x00040000 426 #define LVDS_BLON 0x00080000 427 #define LVDS_ON 0x00000001 428 #define LVDS_DISPLAY_DIS 0x00000002 429 #define LVDS_PANEL_TYPE_2PIX_PER_CLK 0x00000004 430 #define LVDS_PANEL_24BITS_TFT 0x00000008 431 #define LVDS_FRAME_MOD_NO 0x00000000 432 #define LVDS_FRAME_MOD_2_LEVELS 0x00000010 433 #define LVDS_FRAME_MOD_4_LEVELS 0x00000020 434 #define LVDS_RST_FM 0x00000040 435 #define LVDS_EN 0x00000080 436 437 /* CRTC2_GEN_CNTL constants */ 438 #define CRTC2_EN 0x02000000 439 440 /* POWER_MANAGEMENT constants */ 441 #define PWR_MGT_ON 0x00000001 442 #define PWR_MGT_MODE_MASK 0x00000006 443 #define PWR_MGT_MODE_PIN 0x00000000 444 #define PWR_MGT_MODE_REGISTER 0x00000002 445 #define PWR_MGT_MODE_TIMER 0x00000004 446 #define PWR_MGT_MODE_PCI 0x00000006 447 #define PWR_MGT_AUTO_PWR_UP_EN 0x00000008 448 #define PWR_MGT_ACTIVITY_PIN_ON 0x00000010 449 #define PWR_MGT_STANDBY_POL 0x00000020 450 #define PWR_MGT_SUSPEND_POL 0x00000040 451 #define PWR_MGT_SELF_REFRESH 0x00000080 452 #define PWR_MGT_ACTIVITY_PIN_EN 0x00000100 453 #define PWR_MGT_KEYBD_SNOOP 0x00000200 454 #define PWR_MGT_TRISTATE_MEM_EN 0x00000800 455 #define PWR_MGT_SELW4MS 0x00001000 456 #define PWR_MGT_SLOWDOWN_MCLK 0x00002000 457 458 #define PMI_PMSCR_REG 0x60 459 460 /* used by ATI bug fix for hardware ROM */ 461 #define RAGE128_MPP_TB_CONFIG 0x01c0 462 463 #endif /* ATI_REGS_H */ 464