xref: /openbmc/qemu/hw/display/ati_dbg.c (revision 24496b8d)
1 #include "ati_int.h"
2 
3 #ifdef DEBUG_ATI
4 struct ati_regdesc {
5     const char *name;
6     int num;
7 };
8 
9 static struct ati_regdesc ati_reg_names[] = {
10     {"MM_INDEX", 0x0000},
11     {"MM_DATA", 0x0004},
12     {"CLOCK_CNTL_INDEX", 0x0008},
13     {"CLOCK_CNTL_DATA", 0x000c},
14     {"BIOS_0_SCRATCH", 0x0010},
15     {"BUS_CNTL", 0x0030},
16     {"BUS_CNTL1", 0x0034},
17     {"GEN_INT_CNTL", 0x0040},
18     {"CRTC_GEN_CNTL", 0x0050},
19     {"CRTC_EXT_CNTL", 0x0054},
20     {"DAC_CNTL", 0x0058},
21     {"GPIO_MONID", 0x0068},
22     {"I2C_CNTL_1", 0x0094},
23     {"PALETTE_INDEX", 0x00b0},
24     {"PALETTE_DATA", 0x00b4},
25     {"CNFG_CNTL", 0x00e0},
26     {"GEN_RESET_CNTL", 0x00f0},
27     {"CNFG_MEMSIZE", 0x00f8},
28     {"MEM_CNTL", 0x0140},
29     {"MC_FB_LOCATION", 0x0148},
30     {"MC_AGP_LOCATION", 0x014C},
31     {"MC_STATUS", 0x0150},
32     {"MEM_POWER_MISC", 0x015c},
33     {"AGP_BASE", 0x0170},
34     {"AGP_CNTL", 0x0174},
35     {"AGP_APER_OFFSET", 0x0178},
36     {"PCI_GART_PAGE", 0x017c},
37     {"PC_NGUI_MODE", 0x0180},
38     {"PC_NGUI_CTLSTAT", 0x0184},
39     {"MPP_TB_CONFIG", 0x01C0},
40     {"MPP_GP_CONFIG", 0x01C8},
41     {"VIPH_CONTROL", 0x01D0},
42     {"CRTC_H_TOTAL_DISP", 0x0200},
43     {"CRTC_H_SYNC_STRT_WID", 0x0204},
44     {"CRTC_V_TOTAL_DISP", 0x0208},
45     {"CRTC_V_SYNC_STRT_WID", 0x020c},
46     {"CRTC_VLINE_CRNT_VLINE", 0x0210},
47     {"CRTC_CRNT_FRAME", 0x0214},
48     {"CRTC_GUI_TRIG_VLINE", 0x0218},
49     {"CRTC_OFFSET", 0x0224},
50     {"CRTC_OFFSET_CNTL", 0x0228},
51     {"CRTC_PITCH", 0x022c},
52     {"OVR_CLR", 0x0230},
53     {"OVR_WID_LEFT_RIGHT", 0x0234},
54     {"OVR_WID_TOP_BOTTOM", 0x0238},
55     {"CUR_OFFSET", 0x0260},
56     {"CUR_HORZ_VERT_POSN", 0x0264},
57     {"CUR_HORZ_VERT_OFF", 0x0268},
58     {"CUR_CLR0", 0x026c},
59     {"CUR_CLR1", 0x0270},
60     {"LVDS_GEN_CNTL", 0x02d0},
61     {"DDA_CONFIG", 0x02e0},
62     {"DDA_ON_OFF", 0x02e4},
63     {"VGA_DDA_CONFIG", 0x02e8},
64     {"VGA_DDA_ON_OFF", 0x02ec},
65     {"CRTC2_H_TOTAL_DISP", 0x0300},
66     {"CRTC2_H_SYNC_STRT_WID", 0x0304},
67     {"CRTC2_V_TOTAL_DISP", 0x0308},
68     {"CRTC2_V_SYNC_STRT_WID", 0x030c},
69     {"CRTC2_VLINE_CRNT_VLINE", 0x0310},
70     {"CRTC2_CRNT_FRAME", 0x0314},
71     {"CRTC2_GUI_TRIG_VLINE", 0x0318},
72     {"CRTC2_OFFSET", 0x0324},
73     {"CRTC2_OFFSET_CNTL", 0x0328},
74     {"CRTC2_PITCH", 0x032c},
75     {"DDA2_CONFIG", 0x03e0},
76     {"DDA2_ON_OFF", 0x03e4},
77     {"CRTC2_GEN_CNTL", 0x03f8},
78     {"CRTC2_STATUS", 0x03fc},
79     {"OV0_SCALE_CNTL", 0x0420},
80     {"SUBPIC_CNTL", 0x0540},
81     {"PM4_BUFFER_OFFSET", 0x0700},
82     {"PM4_BUFFER_CNTL", 0x0704},
83     {"PM4_BUFFER_WM_CNTL", 0x0708},
84     {"PM4_BUFFER_DL_RPTR_ADDR", 0x070c},
85     {"PM4_BUFFER_DL_RPTR", 0x0710},
86     {"PM4_BUFFER_DL_WPTR", 0x0714},
87     {"PM4_VC_FPU_SETUP", 0x071c},
88     {"PM4_FPU_CNTL", 0x0720},
89     {"PM4_VC_FORMAT", 0x0724},
90     {"PM4_VC_CNTL", 0x0728},
91     {"PM4_VC_I01", 0x072c},
92     {"PM4_VC_VLOFF", 0x0730},
93     {"PM4_VC_VLSIZE", 0x0734},
94     {"PM4_IW_INDOFF", 0x0738},
95     {"PM4_IW_INDSIZE", 0x073c},
96     {"PM4_FPU_FPX0", 0x0740},
97     {"PM4_FPU_FPY0", 0x0744},
98     {"PM4_FPU_FPX1", 0x0748},
99     {"PM4_FPU_FPY1", 0x074c},
100     {"PM4_FPU_FPX2", 0x0750},
101     {"PM4_FPU_FPY2", 0x0754},
102     {"PM4_FPU_FPY3", 0x0758},
103     {"PM4_FPU_FPY4", 0x075c},
104     {"PM4_FPU_FPY5", 0x0760},
105     {"PM4_FPU_FPY6", 0x0764},
106     {"PM4_FPU_FPR", 0x0768},
107     {"PM4_FPU_FPG", 0x076c},
108     {"PM4_FPU_FPB", 0x0770},
109     {"PM4_FPU_FPA", 0x0774},
110     {"PM4_FPU_INTXY0", 0x0780},
111     {"PM4_FPU_INTXY1", 0x0784},
112     {"PM4_FPU_INTXY2", 0x0788},
113     {"PM4_FPU_INTARGB", 0x078c},
114     {"PM4_FPU_FPTWICEAREA", 0x0790},
115     {"PM4_FPU_DMAJOR01", 0x0794},
116     {"PM4_FPU_DMAJOR12", 0x0798},
117     {"PM4_FPU_DMAJOR02", 0x079c},
118     {"PM4_FPU_STAT", 0x07a0},
119     {"PM4_STAT", 0x07b8},
120     {"PM4_TEST_CNTL", 0x07d0},
121     {"PM4_MICROCODE_ADDR", 0x07d4},
122     {"PM4_MICROCODE_RADDR", 0x07d8},
123     {"PM4_MICROCODE_DATAH", 0x07dc},
124     {"PM4_MICROCODE_DATAL", 0x07e0},
125     {"PM4_CMDFIFO_ADDR", 0x07e4},
126     {"PM4_CMDFIFO_DATAH", 0x07e8},
127     {"PM4_CMDFIFO_DATAL", 0x07ec},
128     {"PM4_BUFFER_ADDR", 0x07f0},
129     {"PM4_BUFFER_DATAH", 0x07f4},
130     {"PM4_BUFFER_DATAL", 0x07f8},
131     {"PM4_MICRO_CNTL", 0x07fc},
132     {"CAP0_TRIG_CNTL", 0x0950},
133     {"CAP1_TRIG_CNTL", 0x09c0},
134     {"RBBM_STATUS", 0x0e40},
135     {"PM4_FIFO_DATA_EVEN", 0x1000},
136     {"PM4_FIFO_DATA_ODD", 0x1004},
137     {"DST_OFFSET", 0x1404},
138     {"DST_PITCH", 0x1408},
139     {"DST_WIDTH", 0x140c},
140     {"DST_HEIGHT", 0x1410},
141     {"SRC_X", 0x1414},
142     {"SRC_Y", 0x1418},
143     {"DST_X", 0x141c},
144     {"DST_Y", 0x1420},
145     {"SRC_PITCH_OFFSET", 0x1428},
146     {"DST_PITCH_OFFSET", 0x142c},
147     {"SRC_Y_X", 0x1434},
148     {"DST_Y_X", 0x1438},
149     {"DST_HEIGHT_WIDTH", 0x143c},
150     {"DP_GUI_MASTER_CNTL", 0x146c},
151     {"BRUSH_SCALE", 0x1470},
152     {"BRUSH_Y_X", 0x1474},
153     {"DP_BRUSH_BKGD_CLR", 0x1478},
154     {"DP_BRUSH_FRGD_CLR", 0x147c},
155     {"DST_WIDTH_X", 0x1588},
156     {"DST_HEIGHT_WIDTH_8", 0x158c},
157     {"SRC_X_Y", 0x1590},
158     {"DST_X_Y", 0x1594},
159     {"DST_WIDTH_HEIGHT", 0x1598},
160     {"DST_WIDTH_X_INCY", 0x159c},
161     {"DST_HEIGHT_Y", 0x15a0},
162     {"DST_X_SUB", 0x15a4},
163     {"DST_Y_SUB", 0x15a8},
164     {"SRC_OFFSET", 0x15ac},
165     {"SRC_PITCH", 0x15b0},
166     {"DST_HEIGHT_WIDTH_BW", 0x15b4},
167     {"CLR_CMP_CNTL", 0x15c0},
168     {"CLR_CMP_CLR_SRC", 0x15c4},
169     {"CLR_CMP_CLR_DST", 0x15c8},
170     {"CLR_CMP_MASK", 0x15cc},
171     {"DP_SRC_FRGD_CLR", 0x15d8},
172     {"DP_SRC_BKGD_CLR", 0x15dc},
173     {"DST_BRES_ERR", 0x1628},
174     {"DST_BRES_INC", 0x162c},
175     {"DST_BRES_DEC", 0x1630},
176     {"DST_BRES_LNTH", 0x1634},
177     {"DST_BRES_LNTH_SUB", 0x1638},
178     {"SC_LEFT", 0x1640},
179     {"SC_RIGHT", 0x1644},
180     {"SC_TOP", 0x1648},
181     {"SC_BOTTOM", 0x164c},
182     {"SRC_SC_RIGHT", 0x1654},
183     {"SRC_SC_BOTTOM", 0x165c},
184     {"GUI_DEBUG0", 0x16a0},
185     {"GUI_DEBUG1", 0x16a4},
186     {"GUI_TIMEOUT", 0x16b0},
187     {"GUI_TIMEOUT0", 0x16b4},
188     {"GUI_TIMEOUT1", 0x16b8},
189     {"GUI_PROBE", 0x16bc},
190     {"DP_CNTL", 0x16c0},
191     {"DP_DATATYPE", 0x16c4},
192     {"DP_MIX", 0x16c8},
193     {"DP_WRITE_MASK", 0x16cc},
194     {"DP_CNTL_XDIR_YDIR_YMAJOR", 0x16d0},
195     {"DEFAULT_OFFSET", 0x16e0},
196     {"DEFAULT_PITCH", 0x16e4},
197     {"DEFAULT_SC_BOTTOM_RIGHT", 0x16e8},
198     {"SC_TOP_LEFT", 0x16ec},
199     {"SC_BOTTOM_RIGHT", 0x16f0},
200     {"SRC_SC_BOTTOM_RIGHT", 0x16f4},
201     {"DST_TILE", 0x1700},
202     {"WAIT_UNTIL", 0x1720},
203     {"CACHE_CNTL", 0x1724},
204     {"GUI_STAT", 0x1740},
205     {"PC_GUI_MODE", 0x1744},
206     {"PC_GUI_CTLSTAT", 0x1748},
207     {"PC_DEBUG_MODE", 0x1760},
208     {"BRES_DST_ERR_DEC", 0x1780},
209     {"TRAIL_BRES_T12_ERR_DEC", 0x1784},
210     {"TRAIL_BRES_T12_INC", 0x1788},
211     {"DP_T12_CNTL", 0x178c},
212     {"DST_BRES_T1_LNTH", 0x1790},
213     {"DST_BRES_T2_LNTH", 0x1794},
214     {"SCALE_SRC_HEIGHT_WIDTH", 0x1994},
215     {"SCALE_OFFSET_0", 0x1998},
216     {"SCALE_PITCH", 0x199c},
217     {"SCALE_X_INC", 0x19a0},
218     {"SCALE_Y_INC", 0x19a4},
219     {"SCALE_HACC", 0x19a8},
220     {"SCALE_VACC", 0x19ac},
221     {"SCALE_DST_X_Y", 0x19b0},
222     {"SCALE_DST_HEIGHT_WIDTH", 0x19b4},
223     {"SCALE_3D_CNTL", 0x1a00},
224     {"SCALE_3D_DATATYPE", 0x1a20},
225     {"SETUP_CNTL", 0x1bc4},
226     {"SOLID_COLOR", 0x1bc8},
227     {"WINDOW_XY_OFFSET", 0x1bcc},
228     {"DRAW_LINE_POINT", 0x1bd0},
229     {"SETUP_CNTL_PM4", 0x1bd4},
230     {"DST_PITCH_OFFSET_C", 0x1c80},
231     {"DP_GUI_MASTER_CNTL_C", 0x1c84},
232     {"SC_TOP_LEFT_C", 0x1c88},
233     {"SC_BOTTOM_RIGHT_C", 0x1c8c},
234     {"CLR_CMP_MASK_3D", 0x1A28},
235     {"MISC_3D_STATE_CNTL_REG", 0x1CA0},
236     {"MC_SRC1_CNTL", 0x19D8},
237     {"TEX_CNTL", 0x1800},
238     {"RAGE128_MPP_TB_CONFIG", 0x01c0},
239     {NULL, -1}
240 };
241 
242 const char *ati_reg_name(int num)
243 {
244     int i;
245 
246     num &= ~3;
247     for (i = 0; ati_reg_names[i].name; i++) {
248         if (ati_reg_names[i].num == num) {
249             return ati_reg_names[i].name;
250         }
251     }
252     return "unknown";
253 }
254 #else
255 const char *ati_reg_name(int num)
256 {
257     return "";
258 }
259 #endif
260