1 #include "qemu/osdep.h" 2 #include "ati_int.h" 3 4 #ifdef DEBUG_ATI 5 struct ati_regdesc { 6 const char *name; 7 int num; 8 }; 9 10 static struct ati_regdesc ati_reg_names[] = { 11 {"MM_INDEX", 0x0000}, 12 {"MM_DATA", 0x0004}, 13 {"CLOCK_CNTL_INDEX", 0x0008}, 14 {"CLOCK_CNTL_DATA", 0x000c}, 15 {"BIOS_0_SCRATCH", 0x0010}, 16 {"BUS_CNTL", 0x0030}, 17 {"BUS_CNTL1", 0x0034}, 18 {"GEN_INT_CNTL", 0x0040}, 19 {"GEN_INT_STATUS", 0x0044}, 20 {"CRTC_GEN_CNTL", 0x0050}, 21 {"CRTC_EXT_CNTL", 0x0054}, 22 {"DAC_CNTL", 0x0058}, 23 {"GPIO_VGA_DDC", 0x0060}, 24 {"GPIO_DVI_DDC", 0x0064}, 25 {"GPIO_MONID", 0x0068}, 26 {"I2C_CNTL_1", 0x0094}, 27 {"AMCGPIO_MASK_MIR", 0x009c}, 28 {"AMCGPIO_A_MIR", 0x00a0}, 29 {"AMCGPIO_Y_MIR", 0x00a4}, 30 {"AMCGPIO_EN_MIR", 0x00a8}, 31 {"PALETTE_INDEX", 0x00b0}, 32 {"PALETTE_DATA", 0x00b4}, 33 {"PALETTE_30_DATA", 0x00b8}, 34 {"CNFG_CNTL", 0x00e0}, 35 {"GEN_RESET_CNTL", 0x00f0}, 36 {"CNFG_MEMSIZE", 0x00f8}, 37 {"CONFIG_APER_0_BASE", 0x0100}, 38 {"CONFIG_APER_1_BASE", 0x0104}, 39 {"CONFIG_APER_SIZE", 0x0108}, 40 {"CONFIG_REG_1_BASE", 0x010c}, 41 {"CONFIG_REG_APER_SIZE", 0x0110}, 42 {"HOST_PATH_CNTL", 0x0130}, 43 {"MEM_CNTL", 0x0140}, 44 {"MC_FB_LOCATION", 0x0148}, 45 {"MC_AGP_LOCATION", 0x014C}, 46 {"MC_STATUS", 0x0150}, 47 {"MEM_SDRAM_MODE_REG", 0x0158}, 48 {"MEM_POWER_MISC", 0x015c}, 49 {"AGP_BASE", 0x0170}, 50 {"AGP_CNTL", 0x0174}, 51 {"AGP_APER_OFFSET", 0x0178}, 52 {"PCI_GART_PAGE", 0x017c}, 53 {"PC_NGUI_MODE", 0x0180}, 54 {"PC_NGUI_CTLSTAT", 0x0184}, 55 {"MPP_TB_CONFIG", 0x01C0}, 56 {"MPP_GP_CONFIG", 0x01C8}, 57 {"VIPH_CONTROL", 0x01D0}, 58 {"CRTC_H_TOTAL_DISP", 0x0200}, 59 {"CRTC_H_SYNC_STRT_WID", 0x0204}, 60 {"CRTC_V_TOTAL_DISP", 0x0208}, 61 {"CRTC_V_SYNC_STRT_WID", 0x020c}, 62 {"CRTC_VLINE_CRNT_VLINE", 0x0210}, 63 {"CRTC_CRNT_FRAME", 0x0214}, 64 {"CRTC_GUI_TRIG_VLINE", 0x0218}, 65 {"CRTC_OFFSET", 0x0224}, 66 {"CRTC_OFFSET_CNTL", 0x0228}, 67 {"CRTC_PITCH", 0x022c}, 68 {"OVR_CLR", 0x0230}, 69 {"OVR_WID_LEFT_RIGHT", 0x0234}, 70 {"OVR_WID_TOP_BOTTOM", 0x0238}, 71 {"CUR_OFFSET", 0x0260}, 72 {"CUR_HORZ_VERT_POSN", 0x0264}, 73 {"CUR_HORZ_VERT_OFF", 0x0268}, 74 {"CUR_CLR0", 0x026c}, 75 {"CUR_CLR1", 0x0270}, 76 {"LVDS_GEN_CNTL", 0x02d0}, 77 {"DDA_CONFIG", 0x02e0}, 78 {"DDA_ON_OFF", 0x02e4}, 79 {"VGA_DDA_CONFIG", 0x02e8}, 80 {"VGA_DDA_ON_OFF", 0x02ec}, 81 {"CRTC2_H_TOTAL_DISP", 0x0300}, 82 {"CRTC2_H_SYNC_STRT_WID", 0x0304}, 83 {"CRTC2_V_TOTAL_DISP", 0x0308}, 84 {"CRTC2_V_SYNC_STRT_WID", 0x030c}, 85 {"CRTC2_VLINE_CRNT_VLINE", 0x0310}, 86 {"CRTC2_CRNT_FRAME", 0x0314}, 87 {"CRTC2_GUI_TRIG_VLINE", 0x0318}, 88 {"CRTC2_OFFSET", 0x0324}, 89 {"CRTC2_OFFSET_CNTL", 0x0328}, 90 {"CRTC2_PITCH", 0x032c}, 91 {"DDA2_CONFIG", 0x03e0}, 92 {"DDA2_ON_OFF", 0x03e4}, 93 {"CRTC2_GEN_CNTL", 0x03f8}, 94 {"CRTC2_STATUS", 0x03fc}, 95 {"OV0_SCALE_CNTL", 0x0420}, 96 {"SUBPIC_CNTL", 0x0540}, 97 {"PM4_BUFFER_OFFSET", 0x0700}, 98 {"PM4_BUFFER_CNTL", 0x0704}, 99 {"PM4_BUFFER_WM_CNTL", 0x0708}, 100 {"PM4_BUFFER_DL_RPTR_ADDR", 0x070c}, 101 {"PM4_BUFFER_DL_RPTR", 0x0710}, 102 {"PM4_BUFFER_DL_WPTR", 0x0714}, 103 {"PM4_VC_FPU_SETUP", 0x071c}, 104 {"PM4_FPU_CNTL", 0x0720}, 105 {"PM4_VC_FORMAT", 0x0724}, 106 {"PM4_VC_CNTL", 0x0728}, 107 {"PM4_VC_I01", 0x072c}, 108 {"PM4_VC_VLOFF", 0x0730}, 109 {"PM4_VC_VLSIZE", 0x0734}, 110 {"PM4_IW_INDOFF", 0x0738}, 111 {"PM4_IW_INDSIZE", 0x073c}, 112 {"PM4_FPU_FPX0", 0x0740}, 113 {"PM4_FPU_FPY0", 0x0744}, 114 {"PM4_FPU_FPX1", 0x0748}, 115 {"PM4_FPU_FPY1", 0x074c}, 116 {"PM4_FPU_FPX2", 0x0750}, 117 {"PM4_FPU_FPY2", 0x0754}, 118 {"PM4_FPU_FPY3", 0x0758}, 119 {"PM4_FPU_FPY4", 0x075c}, 120 {"PM4_FPU_FPY5", 0x0760}, 121 {"PM4_FPU_FPY6", 0x0764}, 122 {"PM4_FPU_FPR", 0x0768}, 123 {"PM4_FPU_FPG", 0x076c}, 124 {"PM4_FPU_FPB", 0x0770}, 125 {"PM4_FPU_FPA", 0x0774}, 126 {"PM4_FPU_INTXY0", 0x0780}, 127 {"PM4_FPU_INTXY1", 0x0784}, 128 {"PM4_FPU_INTXY2", 0x0788}, 129 {"PM4_FPU_INTARGB", 0x078c}, 130 {"PM4_FPU_FPTWICEAREA", 0x0790}, 131 {"PM4_FPU_DMAJOR01", 0x0794}, 132 {"PM4_FPU_DMAJOR12", 0x0798}, 133 {"PM4_FPU_DMAJOR02", 0x079c}, 134 {"PM4_FPU_STAT", 0x07a0}, 135 {"PM4_STAT", 0x07b8}, 136 {"PM4_TEST_CNTL", 0x07d0}, 137 {"PM4_MICROCODE_ADDR", 0x07d4}, 138 {"PM4_MICROCODE_RADDR", 0x07d8}, 139 {"PM4_MICROCODE_DATAH", 0x07dc}, 140 {"PM4_MICROCODE_DATAL", 0x07e0}, 141 {"PM4_CMDFIFO_ADDR", 0x07e4}, 142 {"PM4_CMDFIFO_DATAH", 0x07e8}, 143 {"PM4_CMDFIFO_DATAL", 0x07ec}, 144 {"PM4_BUFFER_ADDR", 0x07f0}, 145 {"PM4_BUFFER_DATAH", 0x07f4}, 146 {"PM4_BUFFER_DATAL", 0x07f8}, 147 {"PM4_MICRO_CNTL", 0x07fc}, 148 {"CAP0_TRIG_CNTL", 0x0950}, 149 {"CAP1_TRIG_CNTL", 0x09c0}, 150 {"RBBM_STATUS", 0x0e40}, 151 {"PM4_FIFO_DATA_EVEN", 0x1000}, 152 {"PM4_FIFO_DATA_ODD", 0x1004}, 153 {"DST_OFFSET", 0x1404}, 154 {"DST_PITCH", 0x1408}, 155 {"DST_WIDTH", 0x140c}, 156 {"DST_HEIGHT", 0x1410}, 157 {"SRC_X", 0x1414}, 158 {"SRC_Y", 0x1418}, 159 {"DST_X", 0x141c}, 160 {"DST_Y", 0x1420}, 161 {"SRC_PITCH_OFFSET", 0x1428}, 162 {"DST_PITCH_OFFSET", 0x142c}, 163 {"SRC_Y_X", 0x1434}, 164 {"DST_Y_X", 0x1438}, 165 {"DST_HEIGHT_WIDTH", 0x143c}, 166 {"DP_GUI_MASTER_CNTL", 0x146c}, 167 {"BRUSH_SCALE", 0x1470}, 168 {"BRUSH_Y_X", 0x1474}, 169 {"DP_BRUSH_BKGD_CLR", 0x1478}, 170 {"DP_BRUSH_FRGD_CLR", 0x147c}, 171 {"DST_WIDTH_X", 0x1588}, 172 {"DST_HEIGHT_WIDTH_8", 0x158c}, 173 {"SRC_X_Y", 0x1590}, 174 {"DST_X_Y", 0x1594}, 175 {"DST_WIDTH_HEIGHT", 0x1598}, 176 {"DST_WIDTH_X_INCY", 0x159c}, 177 {"DST_HEIGHT_Y", 0x15a0}, 178 {"DST_X_SUB", 0x15a4}, 179 {"DST_Y_SUB", 0x15a8}, 180 {"SRC_OFFSET", 0x15ac}, 181 {"SRC_PITCH", 0x15b0}, 182 {"DST_HEIGHT_WIDTH_BW", 0x15b4}, 183 {"CLR_CMP_CNTL", 0x15c0}, 184 {"CLR_CMP_CLR_SRC", 0x15c4}, 185 {"CLR_CMP_CLR_DST", 0x15c8}, 186 {"CLR_CMP_MASK", 0x15cc}, 187 {"DP_SRC_FRGD_CLR", 0x15d8}, 188 {"DP_SRC_BKGD_CLR", 0x15dc}, 189 {"DST_BRES_ERR", 0x1628}, 190 {"DST_BRES_INC", 0x162c}, 191 {"DST_BRES_DEC", 0x1630}, 192 {"DST_BRES_LNTH", 0x1634}, 193 {"DST_BRES_LNTH_SUB", 0x1638}, 194 {"SC_LEFT", 0x1640}, 195 {"SC_RIGHT", 0x1644}, 196 {"SC_TOP", 0x1648}, 197 {"SC_BOTTOM", 0x164c}, 198 {"SRC_SC_RIGHT", 0x1654}, 199 {"SRC_SC_BOTTOM", 0x165c}, 200 {"GUI_DEBUG0", 0x16a0}, 201 {"GUI_DEBUG1", 0x16a4}, 202 {"GUI_TIMEOUT", 0x16b0}, 203 {"GUI_TIMEOUT0", 0x16b4}, 204 {"GUI_TIMEOUT1", 0x16b8}, 205 {"GUI_PROBE", 0x16bc}, 206 {"DP_CNTL", 0x16c0}, 207 {"DP_DATATYPE", 0x16c4}, 208 {"DP_MIX", 0x16c8}, 209 {"DP_WRITE_MASK", 0x16cc}, 210 {"DP_CNTL_XDIR_YDIR_YMAJOR", 0x16d0}, 211 {"DEFAULT_OFFSET", 0x16e0}, 212 {"DEFAULT_PITCH", 0x16e4}, 213 {"DEFAULT_SC_BOTTOM_RIGHT", 0x16e8}, 214 {"SC_TOP_LEFT", 0x16ec}, 215 {"SC_BOTTOM_RIGHT", 0x16f0}, 216 {"SRC_SC_BOTTOM_RIGHT", 0x16f4}, 217 {"DST_TILE", 0x1700}, 218 {"WAIT_UNTIL", 0x1720}, 219 {"CACHE_CNTL", 0x1724}, 220 {"GUI_STAT", 0x1740}, 221 {"PC_GUI_MODE", 0x1744}, 222 {"PC_GUI_CTLSTAT", 0x1748}, 223 {"PC_DEBUG_MODE", 0x1760}, 224 {"BRES_DST_ERR_DEC", 0x1780}, 225 {"TRAIL_BRES_T12_ERR_DEC", 0x1784}, 226 {"TRAIL_BRES_T12_INC", 0x1788}, 227 {"DP_T12_CNTL", 0x178c}, 228 {"DST_BRES_T1_LNTH", 0x1790}, 229 {"DST_BRES_T2_LNTH", 0x1794}, 230 {"SCALE_SRC_HEIGHT_WIDTH", 0x1994}, 231 {"SCALE_OFFSET_0", 0x1998}, 232 {"SCALE_PITCH", 0x199c}, 233 {"SCALE_X_INC", 0x19a0}, 234 {"SCALE_Y_INC", 0x19a4}, 235 {"SCALE_HACC", 0x19a8}, 236 {"SCALE_VACC", 0x19ac}, 237 {"SCALE_DST_X_Y", 0x19b0}, 238 {"SCALE_DST_HEIGHT_WIDTH", 0x19b4}, 239 {"SCALE_3D_CNTL", 0x1a00}, 240 {"SCALE_3D_DATATYPE", 0x1a20}, 241 {"SETUP_CNTL", 0x1bc4}, 242 {"SOLID_COLOR", 0x1bc8}, 243 {"WINDOW_XY_OFFSET", 0x1bcc}, 244 {"DRAW_LINE_POINT", 0x1bd0}, 245 {"SETUP_CNTL_PM4", 0x1bd4}, 246 {"DST_PITCH_OFFSET_C", 0x1c80}, 247 {"DP_GUI_MASTER_CNTL_C", 0x1c84}, 248 {"SC_TOP_LEFT_C", 0x1c88}, 249 {"SC_BOTTOM_RIGHT_C", 0x1c8c}, 250 {"CLR_CMP_MASK_3D", 0x1A28}, 251 {"MISC_3D_STATE_CNTL_REG", 0x1CA0}, 252 {"MC_SRC1_CNTL", 0x19D8}, 253 {"TEX_CNTL", 0x1800}, 254 {"RAGE128_MPP_TB_CONFIG", 0x01c0}, 255 {NULL, -1} 256 }; 257 258 const char *ati_reg_name(int num) 259 { 260 int i; 261 262 num &= ~3; 263 for (i = 0; ati_reg_names[i].name; i++) { 264 if (ati_reg_names[i].num == num) { 265 return ati_reg_names[i].name; 266 } 267 } 268 return "unknown"; 269 } 270 #else 271 const char *ati_reg_name(int num) 272 { 273 return ""; 274 } 275 #endif 276