1 /* 2 * QEMU ATI SVGA emulation 3 * 4 * Copyright (c) 2019 BALATON Zoltan 5 * 6 * This work is licensed under the GNU GPL license version 2 or later. 7 */ 8 9 /* 10 * WARNING: 11 * This is very incomplete and only enough for Linux console and some 12 * unaccelerated X output at the moment. 13 * Currently it's little more than a frame buffer with minimal functions, 14 * other more advanced features of the hardware are yet to be implemented. 15 * We only aim for Rage 128 Pro (and some RV100) and 2D only at first, 16 * No 3D at all yet (maybe after 2D works, but feel free to improve it) 17 */ 18 19 #include "qemu/osdep.h" 20 #include "ati_int.h" 21 #include "ati_regs.h" 22 #include "vga-access.h" 23 #include "hw/qdev-properties.h" 24 #include "vga_regs.h" 25 #include "qemu/log.h" 26 #include "qemu/module.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "ui/console.h" 30 #include "hw/display/i2c-ddc.h" 31 #include "trace.h" 32 33 #define ATI_DEBUG_HW_CURSOR 0 34 35 static const struct { 36 const char *name; 37 uint16_t dev_id; 38 } ati_model_aliases[] = { 39 { "rage128p", PCI_DEVICE_ID_ATI_RAGE128_PF }, 40 { "rv100", PCI_DEVICE_ID_ATI_RADEON_QY }, 41 }; 42 43 enum { VGA_MODE, EXT_MODE }; 44 45 static void ati_vga_switch_mode(ATIVGAState *s) 46 { 47 DPRINTF("%d -> %d\n", 48 s->mode, !!(s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN)); 49 if (s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN) { 50 /* Extended mode enabled */ 51 s->mode = EXT_MODE; 52 if (s->regs.crtc_gen_cntl & CRTC2_EN) { 53 /* CRT controller enabled, use CRTC values */ 54 /* FIXME Should these be the same as VGA CRTC regs? */ 55 uint32_t offs = s->regs.crtc_offset & 0x07ffffff; 56 int stride = (s->regs.crtc_pitch & 0x7ff) * 8; 57 int bpp = 0; 58 int h, v; 59 60 if (s->regs.crtc_h_total_disp == 0) { 61 s->regs.crtc_h_total_disp = ((640 / 8) - 1) << 16; 62 } 63 if (s->regs.crtc_v_total_disp == 0) { 64 s->regs.crtc_v_total_disp = (480 - 1) << 16; 65 } 66 h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8; 67 v = (s->regs.crtc_v_total_disp >> 16) + 1; 68 switch (s->regs.crtc_gen_cntl & CRTC_PIX_WIDTH_MASK) { 69 case CRTC_PIX_WIDTH_4BPP: 70 bpp = 4; 71 break; 72 case CRTC_PIX_WIDTH_8BPP: 73 bpp = 8; 74 break; 75 case CRTC_PIX_WIDTH_15BPP: 76 bpp = 15; 77 break; 78 case CRTC_PIX_WIDTH_16BPP: 79 bpp = 16; 80 break; 81 case CRTC_PIX_WIDTH_24BPP: 82 bpp = 24; 83 break; 84 case CRTC_PIX_WIDTH_32BPP: 85 bpp = 32; 86 break; 87 default: 88 qemu_log_mask(LOG_UNIMP, "Unsupported bpp value\n"); 89 return; 90 } 91 DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp, offs); 92 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); 93 vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED); 94 s->vga.big_endian_fb = (s->regs.config_cntl & APER_0_ENDIAN || 95 s->regs.config_cntl & APER_1_ENDIAN ? 96 true : false); 97 /* reset VBE regs then set up mode */ 98 s->vga.vbe_regs[VBE_DISPI_INDEX_XRES] = h; 99 s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] = v; 100 s->vga.vbe_regs[VBE_DISPI_INDEX_BPP] = bpp; 101 /* enable mode via ioport so it updates vga regs */ 102 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); 103 vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_ENABLED | 104 VBE_DISPI_LFB_ENABLED | VBE_DISPI_NOCLEARMEM | 105 (s->regs.dac_cntl & DAC_8BIT_EN ? VBE_DISPI_8BIT_DAC : 0)); 106 /* now set offset and stride after enable as that resets these */ 107 if (stride) { 108 int bypp = DIV_ROUND_UP(bpp, BITS_PER_BYTE); 109 110 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_VIRT_WIDTH); 111 vbe_ioport_write_data(&s->vga, 0, stride); 112 stride *= bypp; 113 if (offs % stride) { 114 DPRINTF("CRTC offset is not multiple of pitch\n"); 115 vbe_ioport_write_index(&s->vga, 0, 116 VBE_DISPI_INDEX_X_OFFSET); 117 vbe_ioport_write_data(&s->vga, 0, offs % stride / bypp); 118 } 119 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_Y_OFFSET); 120 vbe_ioport_write_data(&s->vga, 0, offs / stride); 121 DPRINTF("VBE offset (%d,%d), vbe_start_addr=%x\n", 122 s->vga.vbe_regs[VBE_DISPI_INDEX_X_OFFSET], 123 s->vga.vbe_regs[VBE_DISPI_INDEX_Y_OFFSET], 124 s->vga.vbe_start_addr); 125 } 126 } 127 } else { 128 /* VGA mode enabled */ 129 s->mode = VGA_MODE; 130 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); 131 vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED); 132 } 133 } 134 135 /* Used by host side hardware cursor */ 136 static void ati_cursor_define(ATIVGAState *s) 137 { 138 uint8_t data[1024]; 139 uint32_t srcoff; 140 int i, j, idx = 0; 141 142 if ((s->regs.cur_offset & BIT(31)) || s->cursor_guest_mode) { 143 return; /* Do not update cursor if locked or rendered by guest */ 144 } 145 /* FIXME handle cur_hv_offs correctly */ 146 srcoff = s->regs.cur_offset - 147 (s->regs.cur_hv_offs >> 16) - (s->regs.cur_hv_offs & 0xffff) * 16; 148 for (i = 0; i < 64; i++) { 149 for (j = 0; j < 8; j++, idx++) { 150 data[idx] = vga_read_byte(&s->vga, srcoff + i * 16 + j); 151 data[512 + idx] = vga_read_byte(&s->vga, srcoff + i * 16 + j + 8); 152 } 153 } 154 if (!s->cursor) { 155 s->cursor = cursor_alloc(64, 64); 156 } 157 cursor_set_mono(s->cursor, s->regs.cur_color1, s->regs.cur_color0, 158 &data[512], 1, &data[0]); 159 dpy_cursor_define(s->vga.con, s->cursor); 160 } 161 162 /* Alternatively support guest rendered hardware cursor */ 163 static void ati_cursor_invalidate(VGACommonState *vga) 164 { 165 ATIVGAState *s = container_of(vga, ATIVGAState, vga); 166 int size = (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) ? 64 : 0; 167 168 if (s->regs.cur_offset & BIT(31)) { 169 return; /* Do not update cursor if locked */ 170 } 171 if (s->cursor_size != size || 172 vga->hw_cursor_x != s->regs.cur_hv_pos >> 16 || 173 vga->hw_cursor_y != (s->regs.cur_hv_pos & 0xffff) || 174 s->cursor_offset != s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) - 175 (s->regs.cur_hv_offs & 0xffff) * 16) { 176 /* Remove old cursor then update and show new one if needed */ 177 vga_invalidate_scanlines(vga, vga->hw_cursor_y, vga->hw_cursor_y + 63); 178 vga->hw_cursor_x = s->regs.cur_hv_pos >> 16; 179 vga->hw_cursor_y = s->regs.cur_hv_pos & 0xffff; 180 s->cursor_offset = s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) - 181 (s->regs.cur_hv_offs & 0xffff) * 16; 182 s->cursor_size = size; 183 if (size) { 184 vga_invalidate_scanlines(vga, 185 vga->hw_cursor_y, vga->hw_cursor_y + 63); 186 } 187 } 188 } 189 190 static void ati_cursor_draw_line(VGACommonState *vga, uint8_t *d, int scr_y) 191 { 192 ATIVGAState *s = container_of(vga, ATIVGAState, vga); 193 uint32_t srcoff; 194 uint32_t *dp = (uint32_t *)d; 195 int i, j, h; 196 197 if (!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN) || 198 scr_y < vga->hw_cursor_y || scr_y >= vga->hw_cursor_y + 64 || 199 scr_y > s->regs.crtc_v_total_disp >> 16) { 200 return; 201 } 202 /* FIXME handle cur_hv_offs correctly */ 203 srcoff = s->cursor_offset + (scr_y - vga->hw_cursor_y) * 16; 204 dp = &dp[vga->hw_cursor_x]; 205 h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8; 206 for (i = 0; i < 8; i++) { 207 uint32_t color; 208 uint8_t abits = vga_read_byte(vga, srcoff + i); 209 uint8_t xbits = vga_read_byte(vga, srcoff + i + 8); 210 for (j = 0; j < 8; j++, abits <<= 1, xbits <<= 1) { 211 if (abits & BIT(7)) { 212 if (xbits & BIT(7)) { 213 color = dp[i * 8 + j] ^ 0xffffffff; /* complement */ 214 } else { 215 continue; /* transparent, no change */ 216 } 217 } else { 218 color = (xbits & BIT(7) ? s->regs.cur_color1 : 219 s->regs.cur_color0) | 0xff000000; 220 } 221 if (vga->hw_cursor_x + i * 8 + j >= h) { 222 return; /* end of screen, don't span to next line */ 223 } 224 dp[i * 8 + j] = color; 225 } 226 } 227 } 228 229 static uint64_t ati_i2c(bitbang_i2c_interface *i2c, uint64_t data, int base) 230 { 231 bool c = (data & BIT(base + 17) ? !!(data & BIT(base + 1)) : 1); 232 bool d = (data & BIT(base + 16) ? !!(data & BIT(base)) : 1); 233 234 bitbang_i2c_set(i2c, BITBANG_I2C_SCL, c); 235 d = bitbang_i2c_set(i2c, BITBANG_I2C_SDA, d); 236 237 data &= ~0xf00ULL; 238 if (c) { 239 data |= BIT(base + 9); 240 } 241 if (d) { 242 data |= BIT(base + 8); 243 } 244 return data; 245 } 246 247 static void ati_vga_update_irq(ATIVGAState *s) 248 { 249 pci_set_irq(&s->dev, !!(s->regs.gen_int_status & s->regs.gen_int_cntl)); 250 } 251 252 static void ati_vga_vblank_irq(void *opaque) 253 { 254 ATIVGAState *s = opaque; 255 256 timer_mod(&s->vblank_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 257 NANOSECONDS_PER_SECOND / 60); 258 s->regs.gen_int_status |= CRTC_VBLANK_INT; 259 ati_vga_update_irq(s); 260 } 261 262 static inline uint64_t ati_reg_read_offs(uint32_t reg, int offs, 263 unsigned int size) 264 { 265 if (offs == 0 && size == 4) { 266 return reg; 267 } else { 268 return extract32(reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE); 269 } 270 } 271 272 static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size) 273 { 274 ATIVGAState *s = opaque; 275 uint64_t val = 0; 276 277 switch (addr) { 278 case MM_INDEX: 279 val = s->regs.mm_index; 280 break; 281 case MM_DATA ... MM_DATA + 3: 282 /* indexed access to regs or memory */ 283 if (s->regs.mm_index & BIT(31)) { 284 uint32_t idx = s->regs.mm_index & ~BIT(31); 285 if (idx <= s->vga.vram_size - size) { 286 val = ldn_le_p(s->vga.vram_ptr + idx, size); 287 } 288 } else if (s->regs.mm_index > MM_DATA + 3) { 289 val = ati_mm_read(s, s->regs.mm_index + addr - MM_DATA, size); 290 } else { 291 qemu_log_mask(LOG_GUEST_ERROR, 292 "ati_mm_read: mm_index too small: %u\n", s->regs.mm_index); 293 } 294 break; 295 case BIOS_0_SCRATCH ... BUS_CNTL - 1: 296 { 297 int i = (addr - BIOS_0_SCRATCH) / 4; 298 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) { 299 break; 300 } 301 val = ati_reg_read_offs(s->regs.bios_scratch[i], 302 addr - (BIOS_0_SCRATCH + i * 4), size); 303 break; 304 } 305 case GEN_INT_CNTL: 306 val = s->regs.gen_int_cntl; 307 break; 308 case GEN_INT_STATUS: 309 val = s->regs.gen_int_status; 310 break; 311 case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3: 312 val = ati_reg_read_offs(s->regs.crtc_gen_cntl, 313 addr - CRTC_GEN_CNTL, size); 314 break; 315 case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3: 316 val = ati_reg_read_offs(s->regs.crtc_ext_cntl, 317 addr - CRTC_EXT_CNTL, size); 318 break; 319 case DAC_CNTL: 320 val = s->regs.dac_cntl; 321 break; 322 case GPIO_VGA_DDC ... GPIO_VGA_DDC + 3: 323 val = ati_reg_read_offs(s->regs.gpio_vga_ddc, 324 addr - GPIO_VGA_DDC, size); 325 break; 326 case GPIO_DVI_DDC ... GPIO_DVI_DDC + 3: 327 val = ati_reg_read_offs(s->regs.gpio_dvi_ddc, 328 addr - GPIO_DVI_DDC, size); 329 break; 330 case GPIO_MONID ... GPIO_MONID + 3: 331 val = ati_reg_read_offs(s->regs.gpio_monid, 332 addr - GPIO_MONID, size); 333 break; 334 case PALETTE_INDEX: 335 /* FIXME unaligned access */ 336 val = vga_ioport_read(&s->vga, VGA_PEL_IR) << 16; 337 val |= vga_ioport_read(&s->vga, VGA_PEL_IW) & 0xff; 338 break; 339 case PALETTE_DATA: 340 val = vga_ioport_read(&s->vga, VGA_PEL_D); 341 break; 342 case PALETTE_30_DATA: 343 val = s->regs.palette[vga_ioport_read(&s->vga, VGA_PEL_IR)]; 344 break; 345 case CNFG_CNTL: 346 val = s->regs.config_cntl; 347 break; 348 case CNFG_MEMSIZE: 349 val = s->vga.vram_size; 350 break; 351 case CONFIG_APER_0_BASE: 352 case CONFIG_APER_1_BASE: 353 val = pci_default_read_config(&s->dev, 354 PCI_BASE_ADDRESS_0, size) & 0xfffffff0; 355 break; 356 case CONFIG_APER_SIZE: 357 val = s->vga.vram_size / 2; 358 break; 359 case CONFIG_REG_1_BASE: 360 val = pci_default_read_config(&s->dev, 361 PCI_BASE_ADDRESS_2, size) & 0xfffffff0; 362 break; 363 case CONFIG_REG_APER_SIZE: 364 val = memory_region_size(&s->mm) / 2; 365 break; 366 case HOST_PATH_CNTL: 367 val = BIT(23); /* Radeon HDP_APER_CNTL */ 368 break; 369 case MC_STATUS: 370 val = 5; 371 break; 372 case MEM_SDRAM_MODE_REG: 373 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 374 val = BIT(28) | BIT(20); 375 } 376 break; 377 case RBBM_STATUS: 378 case GUI_STAT: 379 val = 64; /* free CMDFIFO entries */ 380 break; 381 case CRTC_H_TOTAL_DISP: 382 val = s->regs.crtc_h_total_disp; 383 break; 384 case CRTC_H_SYNC_STRT_WID: 385 val = s->regs.crtc_h_sync_strt_wid; 386 break; 387 case CRTC_V_TOTAL_DISP: 388 val = s->regs.crtc_v_total_disp; 389 break; 390 case CRTC_V_SYNC_STRT_WID: 391 val = s->regs.crtc_v_sync_strt_wid; 392 break; 393 case CRTC_OFFSET: 394 val = s->regs.crtc_offset; 395 break; 396 case CRTC_OFFSET_CNTL: 397 val = s->regs.crtc_offset_cntl; 398 break; 399 case CRTC_PITCH: 400 val = s->regs.crtc_pitch; 401 break; 402 case 0xf00 ... 0xfff: 403 val = pci_default_read_config(&s->dev, addr - 0xf00, size); 404 break; 405 case CUR_OFFSET ... CUR_OFFSET + 3: 406 val = ati_reg_read_offs(s->regs.cur_offset, addr - CUR_OFFSET, size); 407 break; 408 case CUR_HORZ_VERT_POSN ... CUR_HORZ_VERT_POSN + 3: 409 val = ati_reg_read_offs(s->regs.cur_hv_pos, 410 addr - CUR_HORZ_VERT_POSN, size); 411 if (addr + size > CUR_HORZ_VERT_POSN + 3) { 412 val |= (s->regs.cur_offset & BIT(31)) >> (4 - size); 413 } 414 break; 415 case CUR_HORZ_VERT_OFF ... CUR_HORZ_VERT_OFF + 3: 416 val = ati_reg_read_offs(s->regs.cur_hv_offs, 417 addr - CUR_HORZ_VERT_OFF, size); 418 if (addr + size > CUR_HORZ_VERT_OFF + 3) { 419 val |= (s->regs.cur_offset & BIT(31)) >> (4 - size); 420 } 421 break; 422 case CUR_CLR0 ... CUR_CLR0 + 3: 423 val = ati_reg_read_offs(s->regs.cur_color0, addr - CUR_CLR0, size); 424 break; 425 case CUR_CLR1 ... CUR_CLR1 + 3: 426 val = ati_reg_read_offs(s->regs.cur_color1, addr - CUR_CLR1, size); 427 break; 428 case DST_OFFSET: 429 val = s->regs.dst_offset; 430 break; 431 case DST_PITCH: 432 val = s->regs.dst_pitch; 433 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 434 val &= s->regs.dst_tile << 16; 435 } 436 break; 437 case DST_WIDTH: 438 val = s->regs.dst_width; 439 break; 440 case DST_HEIGHT: 441 val = s->regs.dst_height; 442 break; 443 case SRC_X: 444 val = s->regs.src_x; 445 break; 446 case SRC_Y: 447 val = s->regs.src_y; 448 break; 449 case DST_X: 450 val = s->regs.dst_x; 451 break; 452 case DST_Y: 453 val = s->regs.dst_y; 454 break; 455 case DP_GUI_MASTER_CNTL: 456 val = s->regs.dp_gui_master_cntl; 457 break; 458 case SRC_OFFSET: 459 val = s->regs.src_offset; 460 break; 461 case SRC_PITCH: 462 val = s->regs.src_pitch; 463 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 464 val &= s->regs.src_tile << 16; 465 } 466 break; 467 case DP_BRUSH_BKGD_CLR: 468 val = s->regs.dp_brush_bkgd_clr; 469 break; 470 case DP_BRUSH_FRGD_CLR: 471 val = s->regs.dp_brush_frgd_clr; 472 break; 473 case DP_SRC_FRGD_CLR: 474 val = s->regs.dp_src_frgd_clr; 475 break; 476 case DP_SRC_BKGD_CLR: 477 val = s->regs.dp_src_bkgd_clr; 478 break; 479 case DP_CNTL: 480 val = s->regs.dp_cntl; 481 break; 482 case DP_DATATYPE: 483 val = s->regs.dp_datatype; 484 break; 485 case DP_MIX: 486 val = s->regs.dp_mix; 487 break; 488 case DP_WRITE_MASK: 489 val = s->regs.dp_write_mask; 490 break; 491 case DEFAULT_OFFSET: 492 val = s->regs.default_offset; 493 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 494 val >>= 10; 495 val |= s->regs.default_pitch << 16; 496 val |= s->regs.default_tile << 30; 497 } 498 break; 499 case DEFAULT_PITCH: 500 val = s->regs.default_pitch; 501 val |= s->regs.default_tile << 16; 502 break; 503 case DEFAULT_SC_BOTTOM_RIGHT: 504 val = s->regs.default_sc_bottom_right; 505 break; 506 default: 507 break; 508 } 509 if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) { 510 trace_ati_mm_read(size, addr, ati_reg_name(addr & ~3ULL), val); 511 } 512 return val; 513 } 514 515 static inline void ati_reg_write_offs(uint32_t *reg, int offs, 516 uint64_t data, unsigned int size) 517 { 518 if (offs == 0 && size == 4) { 519 *reg = data; 520 } else { 521 *reg = deposit32(*reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE, 522 data); 523 } 524 } 525 526 static void ati_mm_write(void *opaque, hwaddr addr, 527 uint64_t data, unsigned int size) 528 { 529 ATIVGAState *s = opaque; 530 531 if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) { 532 trace_ati_mm_write(size, addr, ati_reg_name(addr & ~3ULL), data); 533 } 534 switch (addr) { 535 case MM_INDEX: 536 s->regs.mm_index = data & ~3; 537 break; 538 case MM_DATA ... MM_DATA + 3: 539 /* indexed access to regs or memory */ 540 if (s->regs.mm_index & BIT(31)) { 541 uint32_t idx = s->regs.mm_index & ~BIT(31); 542 if (idx <= s->vga.vram_size - size) { 543 stn_le_p(s->vga.vram_ptr + idx, size, data); 544 } 545 } else if (s->regs.mm_index > MM_DATA + 3) { 546 ati_mm_write(s, s->regs.mm_index + addr - MM_DATA, data, size); 547 } else { 548 qemu_log_mask(LOG_GUEST_ERROR, 549 "ati_mm_write: mm_index too small: %u\n", s->regs.mm_index); 550 } 551 break; 552 case BIOS_0_SCRATCH ... BUS_CNTL - 1: 553 { 554 int i = (addr - BIOS_0_SCRATCH) / 4; 555 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) { 556 break; 557 } 558 ati_reg_write_offs(&s->regs.bios_scratch[i], 559 addr - (BIOS_0_SCRATCH + i * 4), data, size); 560 break; 561 } 562 case GEN_INT_CNTL: 563 s->regs.gen_int_cntl = data; 564 if (data & CRTC_VBLANK_INT) { 565 ati_vga_vblank_irq(s); 566 } else { 567 timer_del(&s->vblank_timer); 568 ati_vga_update_irq(s); 569 } 570 break; 571 case GEN_INT_STATUS: 572 data &= (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF ? 573 0x000f040fUL : 0xfc080effUL); 574 s->regs.gen_int_status &= ~data; 575 ati_vga_update_irq(s); 576 break; 577 case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3: 578 { 579 uint32_t val = s->regs.crtc_gen_cntl; 580 ati_reg_write_offs(&s->regs.crtc_gen_cntl, 581 addr - CRTC_GEN_CNTL, data, size); 582 if ((val & CRTC2_CUR_EN) != (s->regs.crtc_gen_cntl & CRTC2_CUR_EN)) { 583 if (s->cursor_guest_mode) { 584 s->vga.force_shadow = !!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN); 585 } else { 586 if (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) { 587 ati_cursor_define(s); 588 } 589 dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16, 590 s->regs.cur_hv_pos & 0xffff, 591 (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) != 0); 592 } 593 } 594 if ((val & (CRTC2_EXT_DISP_EN | CRTC2_EN)) != 595 (s->regs.crtc_gen_cntl & (CRTC2_EXT_DISP_EN | CRTC2_EN))) { 596 ati_vga_switch_mode(s); 597 } 598 break; 599 } 600 case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3: 601 { 602 uint32_t val = s->regs.crtc_ext_cntl; 603 ati_reg_write_offs(&s->regs.crtc_ext_cntl, 604 addr - CRTC_EXT_CNTL, data, size); 605 if (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS) { 606 DPRINTF("Display disabled\n"); 607 s->vga.ar_index &= ~BIT(5); 608 } else { 609 DPRINTF("Display enabled\n"); 610 s->vga.ar_index |= BIT(5); 611 ati_vga_switch_mode(s); 612 } 613 if ((val & CRT_CRTC_DISPLAY_DIS) != 614 (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS)) { 615 ati_vga_switch_mode(s); 616 } 617 break; 618 } 619 case DAC_CNTL: 620 s->regs.dac_cntl = data & 0xffffe3ff; 621 s->vga.dac_8bit = !!(data & DAC_8BIT_EN); 622 break; 623 /* 624 * GPIO regs for DDC access. Because some drivers access these via 625 * multiple byte writes we have to be careful when we send bits to 626 * avoid spurious changes in bitbang_i2c state. Only do it when either 627 * the enable bits are changed or output bits changed while enabled. 628 */ 629 case GPIO_VGA_DDC ... GPIO_VGA_DDC + 3: 630 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 631 /* FIXME: Maybe add a property to select VGA or DVI port? */ 632 } 633 break; 634 case GPIO_DVI_DDC ... GPIO_DVI_DDC + 3: 635 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 636 ati_reg_write_offs(&s->regs.gpio_dvi_ddc, 637 addr - GPIO_DVI_DDC, data, size); 638 if ((addr <= GPIO_DVI_DDC + 2 && addr + size > GPIO_DVI_DDC + 2) || 639 (addr == GPIO_DVI_DDC && (s->regs.gpio_dvi_ddc & 0x30000))) { 640 s->regs.gpio_dvi_ddc = ati_i2c(&s->bbi2c, 641 s->regs.gpio_dvi_ddc, 0); 642 } 643 } 644 break; 645 case GPIO_MONID ... GPIO_MONID + 3: 646 /* FIXME What does Radeon have here? */ 647 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 648 /* Rage128p accesses DDC via MONID(1-2) with additional mask bit */ 649 ati_reg_write_offs(&s->regs.gpio_monid, 650 addr - GPIO_MONID, data, size); 651 if ((s->regs.gpio_monid & BIT(25)) && 652 ((addr <= GPIO_MONID + 2 && addr + size > GPIO_MONID + 2) || 653 (addr == GPIO_MONID && (s->regs.gpio_monid & 0x60000)))) { 654 s->regs.gpio_monid = ati_i2c(&s->bbi2c, s->regs.gpio_monid, 1); 655 } 656 } 657 break; 658 case PALETTE_INDEX ... PALETTE_INDEX + 3: 659 if (size == 4) { 660 vga_ioport_write(&s->vga, VGA_PEL_IR, (data >> 16) & 0xff); 661 vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff); 662 } else { 663 if (addr == PALETTE_INDEX) { 664 vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff); 665 } else { 666 vga_ioport_write(&s->vga, VGA_PEL_IR, data & 0xff); 667 } 668 } 669 break; 670 case PALETTE_DATA ... PALETTE_DATA + 3: 671 data <<= addr - PALETTE_DATA; 672 data = bswap32(data) >> 8; 673 vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); 674 data >>= 8; 675 vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); 676 data >>= 8; 677 vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); 678 break; 679 case PALETTE_30_DATA: 680 s->regs.palette[vga_ioport_read(&s->vga, VGA_PEL_IW)] = data; 681 vga_ioport_write(&s->vga, VGA_PEL_D, (data >> 22) & 0xff); 682 vga_ioport_write(&s->vga, VGA_PEL_D, (data >> 12) & 0xff); 683 vga_ioport_write(&s->vga, VGA_PEL_D, (data >> 2) & 0xff); 684 break; 685 case CNFG_CNTL: 686 s->regs.config_cntl = data; 687 break; 688 case CRTC_H_TOTAL_DISP: 689 s->regs.crtc_h_total_disp = data & 0x07ff07ff; 690 break; 691 case CRTC_H_SYNC_STRT_WID: 692 s->regs.crtc_h_sync_strt_wid = data & 0x17bf1fff; 693 break; 694 case CRTC_V_TOTAL_DISP: 695 s->regs.crtc_v_total_disp = data & 0x0fff0fff; 696 break; 697 case CRTC_V_SYNC_STRT_WID: 698 s->regs.crtc_v_sync_strt_wid = data & 0x9f0fff; 699 break; 700 case CRTC_OFFSET: 701 s->regs.crtc_offset = data & 0xc7ffffff; 702 break; 703 case CRTC_OFFSET_CNTL: 704 s->regs.crtc_offset_cntl = data; /* FIXME */ 705 break; 706 case CRTC_PITCH: 707 s->regs.crtc_pitch = data & 0x07ff07ff; 708 break; 709 case 0xf00 ... 0xfff: 710 /* read-only copy of PCI config space so ignore writes */ 711 break; 712 case CUR_OFFSET ... CUR_OFFSET + 3: 713 { 714 uint32_t t = s->regs.cur_offset; 715 716 ati_reg_write_offs(&t, addr - CUR_OFFSET, data, size); 717 t &= 0x87fffff0; 718 if (s->regs.cur_offset != t) { 719 s->regs.cur_offset = t; 720 ati_cursor_define(s); 721 } 722 break; 723 } 724 case CUR_HORZ_VERT_POSN ... CUR_HORZ_VERT_POSN + 3: 725 { 726 uint32_t t = s->regs.cur_hv_pos | (s->regs.cur_offset & BIT(31)); 727 728 ati_reg_write_offs(&t, addr - CUR_HORZ_VERT_POSN, data, size); 729 s->regs.cur_hv_pos = t & 0x3fff0fff; 730 if (t & BIT(31)) { 731 s->regs.cur_offset |= t & BIT(31); 732 } else if (s->regs.cur_offset & BIT(31)) { 733 s->regs.cur_offset &= ~BIT(31); 734 ati_cursor_define(s); 735 } 736 if (!s->cursor_guest_mode && 737 (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) && !(t & BIT(31))) { 738 dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16, 739 s->regs.cur_hv_pos & 0xffff, 1); 740 } 741 break; 742 } 743 case CUR_HORZ_VERT_OFF: 744 { 745 uint32_t t = s->regs.cur_hv_offs | (s->regs.cur_offset & BIT(31)); 746 747 ati_reg_write_offs(&t, addr - CUR_HORZ_VERT_OFF, data, size); 748 s->regs.cur_hv_offs = t & 0x3f003f; 749 if (t & BIT(31)) { 750 s->regs.cur_offset |= t & BIT(31); 751 } else if (s->regs.cur_offset & BIT(31)) { 752 s->regs.cur_offset &= ~BIT(31); 753 ati_cursor_define(s); 754 } 755 break; 756 } 757 case CUR_CLR0 ... CUR_CLR0 + 3: 758 { 759 uint32_t t = s->regs.cur_color0; 760 761 ati_reg_write_offs(&t, addr - CUR_CLR0, data, size); 762 t &= 0xffffff; 763 if (s->regs.cur_color0 != t) { 764 s->regs.cur_color0 = t; 765 ati_cursor_define(s); 766 } 767 break; 768 } 769 case CUR_CLR1 ... CUR_CLR1 + 3: 770 /* 771 * Update cursor unconditionally here because some clients set up 772 * other registers before actually writing cursor data to memory at 773 * offset so we would miss cursor change unless always updating here 774 */ 775 ati_reg_write_offs(&s->regs.cur_color1, addr - CUR_CLR1, data, size); 776 s->regs.cur_color1 &= 0xffffff; 777 ati_cursor_define(s); 778 break; 779 case DST_OFFSET: 780 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 781 s->regs.dst_offset = data & 0xfffffff0; 782 } else { 783 s->regs.dst_offset = data & 0xfffffc00; 784 } 785 break; 786 case DST_PITCH: 787 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 788 s->regs.dst_pitch = data & 0x3fff; 789 s->regs.dst_tile = (data >> 16) & 1; 790 } else { 791 s->regs.dst_pitch = data & 0x3ff0; 792 } 793 break; 794 case DST_TILE: 795 if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY) { 796 s->regs.dst_tile = data & 3; 797 } 798 break; 799 case DST_WIDTH: 800 s->regs.dst_width = data & 0x3fff; 801 ati_2d_blt(s); 802 break; 803 case DST_HEIGHT: 804 s->regs.dst_height = data & 0x3fff; 805 break; 806 case SRC_X: 807 s->regs.src_x = data & 0x3fff; 808 break; 809 case SRC_Y: 810 s->regs.src_y = data & 0x3fff; 811 break; 812 case DST_X: 813 s->regs.dst_x = data & 0x3fff; 814 break; 815 case DST_Y: 816 s->regs.dst_y = data & 0x3fff; 817 break; 818 case SRC_PITCH_OFFSET: 819 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 820 s->regs.src_offset = (data & 0x1fffff) << 5; 821 s->regs.src_pitch = (data & 0x7fe00000) >> 21; 822 s->regs.src_tile = data >> 31; 823 } else { 824 s->regs.src_offset = (data & 0x3fffff) << 10; 825 s->regs.src_pitch = (data & 0x3fc00000) >> 16; 826 s->regs.src_tile = (data >> 30) & 1; 827 } 828 break; 829 case DST_PITCH_OFFSET: 830 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 831 s->regs.dst_offset = (data & 0x1fffff) << 5; 832 s->regs.dst_pitch = (data & 0x7fe00000) >> 21; 833 s->regs.dst_tile = data >> 31; 834 } else { 835 s->regs.dst_offset = (data & 0x3fffff) << 10; 836 s->regs.dst_pitch = (data & 0x3fc00000) >> 16; 837 s->regs.dst_tile = data >> 30; 838 } 839 break; 840 case SRC_Y_X: 841 s->regs.src_x = data & 0x3fff; 842 s->regs.src_y = (data >> 16) & 0x3fff; 843 break; 844 case DST_Y_X: 845 s->regs.dst_x = data & 0x3fff; 846 s->regs.dst_y = (data >> 16) & 0x3fff; 847 break; 848 case DST_HEIGHT_WIDTH: 849 s->regs.dst_width = data & 0x3fff; 850 s->regs.dst_height = (data >> 16) & 0x3fff; 851 ati_2d_blt(s); 852 break; 853 case DP_GUI_MASTER_CNTL: 854 s->regs.dp_gui_master_cntl = data & 0xf800000f; 855 s->regs.dp_datatype = (data & 0x0f00) >> 8 | (data & 0x30f0) << 4 | 856 (data & 0x4000) << 16; 857 s->regs.dp_mix = (data & GMC_ROP3_MASK) | (data & 0x7000000) >> 16; 858 break; 859 case DST_WIDTH_X: 860 s->regs.dst_x = data & 0x3fff; 861 s->regs.dst_width = (data >> 16) & 0x3fff; 862 ati_2d_blt(s); 863 break; 864 case SRC_X_Y: 865 s->regs.src_y = data & 0x3fff; 866 s->regs.src_x = (data >> 16) & 0x3fff; 867 break; 868 case DST_X_Y: 869 s->regs.dst_y = data & 0x3fff; 870 s->regs.dst_x = (data >> 16) & 0x3fff; 871 break; 872 case DST_WIDTH_HEIGHT: 873 s->regs.dst_height = data & 0x3fff; 874 s->regs.dst_width = (data >> 16) & 0x3fff; 875 ati_2d_blt(s); 876 break; 877 case DST_HEIGHT_Y: 878 s->regs.dst_y = data & 0x3fff; 879 s->regs.dst_height = (data >> 16) & 0x3fff; 880 break; 881 case SRC_OFFSET: 882 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 883 s->regs.src_offset = data & 0xfffffff0; 884 } else { 885 s->regs.src_offset = data & 0xfffffc00; 886 } 887 break; 888 case SRC_PITCH: 889 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 890 s->regs.src_pitch = data & 0x3fff; 891 s->regs.src_tile = (data >> 16) & 1; 892 } else { 893 s->regs.src_pitch = data & 0x3ff0; 894 } 895 break; 896 case DP_BRUSH_BKGD_CLR: 897 s->regs.dp_brush_bkgd_clr = data; 898 break; 899 case DP_BRUSH_FRGD_CLR: 900 s->regs.dp_brush_frgd_clr = data; 901 break; 902 case DP_CNTL: 903 s->regs.dp_cntl = data; 904 break; 905 case DP_DATATYPE: 906 s->regs.dp_datatype = data & 0xe0070f0f; 907 break; 908 case DP_MIX: 909 s->regs.dp_mix = data & 0x00ff0700; 910 break; 911 case DP_WRITE_MASK: 912 s->regs.dp_write_mask = data; 913 break; 914 case DEFAULT_OFFSET: 915 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 916 s->regs.default_offset = data & 0xfffffff0; 917 } else { 918 /* Radeon has DEFAULT_PITCH_OFFSET here like DST_PITCH_OFFSET */ 919 s->regs.default_offset = (data & 0x3fffff) << 10; 920 s->regs.default_pitch = (data & 0x3fc00000) >> 16; 921 s->regs.default_tile = data >> 30; 922 } 923 break; 924 case DEFAULT_PITCH: 925 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 926 s->regs.default_pitch = data & 0x3fff; 927 s->regs.default_tile = (data >> 16) & 1; 928 } 929 break; 930 case DEFAULT_SC_BOTTOM_RIGHT: 931 s->regs.default_sc_bottom_right = data & 0x3fff3fff; 932 break; 933 default: 934 break; 935 } 936 } 937 938 static const MemoryRegionOps ati_mm_ops = { 939 .read = ati_mm_read, 940 .write = ati_mm_write, 941 .endianness = DEVICE_LITTLE_ENDIAN, 942 }; 943 944 static void ati_vga_realize(PCIDevice *dev, Error **errp) 945 { 946 ATIVGAState *s = ATI_VGA(dev); 947 VGACommonState *vga = &s->vga; 948 949 if (s->model) { 950 int i; 951 for (i = 0; i < ARRAY_SIZE(ati_model_aliases); i++) { 952 if (!strcmp(s->model, ati_model_aliases[i].name)) { 953 s->dev_id = ati_model_aliases[i].dev_id; 954 break; 955 } 956 } 957 if (i >= ARRAY_SIZE(ati_model_aliases)) { 958 warn_report("Unknown ATI VGA model name, " 959 "using default rage128p"); 960 } 961 } 962 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF && 963 s->dev_id != PCI_DEVICE_ID_ATI_RADEON_QY) { 964 error_setg(errp, "Unknown ATI VGA device id, " 965 "only 0x5046 and 0x5159 are supported"); 966 return; 967 } 968 pci_set_word(dev->config + PCI_DEVICE_ID, s->dev_id); 969 970 if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY && 971 s->vga.vram_size_mb < 16) { 972 warn_report("Too small video memory for device id"); 973 s->vga.vram_size_mb = 16; 974 } 975 976 /* init vga bits */ 977 if (!vga_common_init(vga, OBJECT(s), errp)) { 978 return; 979 } 980 vga_init(vga, OBJECT(s), pci_address_space(dev), 981 pci_address_space_io(dev), true); 982 vga->con = graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, &s->vga); 983 if (s->cursor_guest_mode) { 984 vga->cursor_invalidate = ati_cursor_invalidate; 985 vga->cursor_draw_line = ati_cursor_draw_line; 986 } 987 988 /* ddc, edid */ 989 I2CBus *i2cbus = i2c_init_bus(DEVICE(s), "ati-vga.ddc"); 990 bitbang_i2c_init(&s->bbi2c, i2cbus); 991 I2CSlave *i2cddc = I2C_SLAVE(qdev_new(TYPE_I2CDDC)); 992 i2c_slave_set_address(i2cddc, 0x50); 993 qdev_realize_and_unref(DEVICE(i2cddc), BUS(i2cbus), &error_abort); 994 995 /* mmio register space */ 996 memory_region_init_io(&s->mm, OBJECT(s), &ati_mm_ops, s, 997 "ati.mmregs", 0x4000); 998 /* io space is alias to beginning of mmregs */ 999 memory_region_init_alias(&s->io, OBJECT(s), "ati.io", &s->mm, 0, 0x100); 1000 1001 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram); 1002 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io); 1003 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mm); 1004 1005 /* most interrupts are not yet emulated but MacOS needs at least VBlank */ 1006 dev->config[PCI_INTERRUPT_PIN] = 1; 1007 timer_init_ns(&s->vblank_timer, QEMU_CLOCK_VIRTUAL, ati_vga_vblank_irq, s); 1008 } 1009 1010 static void ati_vga_reset(DeviceState *dev) 1011 { 1012 ATIVGAState *s = ATI_VGA(dev); 1013 1014 timer_del(&s->vblank_timer); 1015 ati_vga_update_irq(s); 1016 1017 /* reset vga */ 1018 vga_common_reset(&s->vga); 1019 s->mode = VGA_MODE; 1020 } 1021 1022 static void ati_vga_exit(PCIDevice *dev) 1023 { 1024 ATIVGAState *s = ATI_VGA(dev); 1025 1026 timer_del(&s->vblank_timer); 1027 graphic_console_close(s->vga.con); 1028 } 1029 1030 static Property ati_vga_properties[] = { 1031 DEFINE_PROP_UINT32("vgamem_mb", ATIVGAState, vga.vram_size_mb, 16), 1032 DEFINE_PROP_STRING("model", ATIVGAState, model), 1033 DEFINE_PROP_UINT16("x-device-id", ATIVGAState, dev_id, 1034 PCI_DEVICE_ID_ATI_RAGE128_PF), 1035 DEFINE_PROP_BOOL("guest_hwcursor", ATIVGAState, cursor_guest_mode, false), 1036 DEFINE_PROP_UINT8("x-pixman", ATIVGAState, use_pixman, 3), 1037 DEFINE_PROP_END_OF_LIST() 1038 }; 1039 1040 static void ati_vga_class_init(ObjectClass *klass, void *data) 1041 { 1042 DeviceClass *dc = DEVICE_CLASS(klass); 1043 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1044 1045 dc->reset = ati_vga_reset; 1046 device_class_set_props(dc, ati_vga_properties); 1047 dc->hotpluggable = false; 1048 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 1049 1050 k->class_id = PCI_CLASS_DISPLAY_VGA; 1051 k->vendor_id = PCI_VENDOR_ID_ATI; 1052 k->device_id = PCI_DEVICE_ID_ATI_RAGE128_PF; 1053 k->romfile = "vgabios-ati.bin"; 1054 k->realize = ati_vga_realize; 1055 k->exit = ati_vga_exit; 1056 } 1057 1058 static void ati_vga_init(Object *o) 1059 { 1060 object_property_set_description(o, "x-pixman", "Use pixman for: " 1061 "1: fill, 2: blit"); 1062 } 1063 1064 static const TypeInfo ati_vga_info = { 1065 .name = TYPE_ATI_VGA, 1066 .parent = TYPE_PCI_DEVICE, 1067 .instance_size = sizeof(ATIVGAState), 1068 .class_init = ati_vga_class_init, 1069 .instance_init = ati_vga_init, 1070 .interfaces = (InterfaceInfo[]) { 1071 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1072 { }, 1073 }, 1074 }; 1075 1076 static void ati_vga_register_types(void) 1077 { 1078 type_register_static(&ati_vga_info); 1079 } 1080 1081 type_init(ati_vga_register_types) 1082