xref: /openbmc/qemu/hw/display/ati.c (revision 6cdda0ff)
1 /*
2  * QEMU ATI SVGA emulation
3  *
4  * Copyright (c) 2019 BALATON Zoltan
5  *
6  * This work is licensed under the GNU GPL license version 2 or later.
7  */
8 
9 /*
10  * WARNING:
11  * This is very incomplete and only enough for Linux console and some
12  * unaccelerated X output at the moment.
13  * Currently it's little more than a frame buffer with minimal functions,
14  * other more advanced features of the hardware are yet to be implemented.
15  * We only aim for Rage 128 Pro (and some RV100) and 2D only at first,
16  * No 3D at all yet (maybe after 2D works, but feel free to improve it)
17  */
18 
19 #include "qemu/osdep.h"
20 #include "ati_int.h"
21 #include "ati_regs.h"
22 #include "vga-access.h"
23 #include "hw/qdev-properties.h"
24 #include "vga_regs.h"
25 #include "qemu/log.h"
26 #include "qemu/module.h"
27 #include "qemu/error-report.h"
28 #include "qapi/error.h"
29 #include "ui/console.h"
30 #include "hw/display/i2c-ddc.h"
31 #include "trace.h"
32 
33 #define ATI_DEBUG_HW_CURSOR 0
34 
35 static const struct {
36     const char *name;
37     uint16_t dev_id;
38 } ati_model_aliases[] = {
39     { "rage128p", PCI_DEVICE_ID_ATI_RAGE128_PF },
40     { "rv100", PCI_DEVICE_ID_ATI_RADEON_QY },
41 };
42 
43 enum { VGA_MODE, EXT_MODE };
44 
45 static void ati_vga_switch_mode(ATIVGAState *s)
46 {
47     DPRINTF("%d -> %d\n",
48             s->mode, !!(s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN));
49     if (s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN) {
50         /* Extended mode enabled */
51         s->mode = EXT_MODE;
52         if (s->regs.crtc_gen_cntl & CRTC2_EN) {
53             /* CRT controller enabled, use CRTC values */
54             /* FIXME Should these be the same as VGA CRTC regs? */
55             uint32_t offs = s->regs.crtc_offset & 0x07ffffff;
56             int stride = (s->regs.crtc_pitch & 0x7ff) * 8;
57             int bpp = 0;
58             int h, v;
59 
60             if (s->regs.crtc_h_total_disp == 0) {
61                 s->regs.crtc_h_total_disp = ((640 / 8) - 1) << 16;
62             }
63             if (s->regs.crtc_v_total_disp == 0) {
64                 s->regs.crtc_v_total_disp = (480 - 1) << 16;
65             }
66             h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8;
67             v = (s->regs.crtc_v_total_disp >> 16) + 1;
68             switch (s->regs.crtc_gen_cntl & CRTC_PIX_WIDTH_MASK) {
69             case CRTC_PIX_WIDTH_4BPP:
70                 bpp = 4;
71                 break;
72             case CRTC_PIX_WIDTH_8BPP:
73                 bpp = 8;
74                 break;
75             case CRTC_PIX_WIDTH_15BPP:
76                 bpp = 15;
77                 break;
78             case CRTC_PIX_WIDTH_16BPP:
79                 bpp = 16;
80                 break;
81             case CRTC_PIX_WIDTH_24BPP:
82                 bpp = 24;
83                 break;
84             case CRTC_PIX_WIDTH_32BPP:
85                 bpp = 32;
86                 break;
87             default:
88                 qemu_log_mask(LOG_UNIMP, "Unsupported bpp value\n");
89             }
90             assert(bpp != 0);
91             DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp, offs);
92             vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE);
93             vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED);
94             s->vga.big_endian_fb = (s->regs.config_cntl & APER_0_ENDIAN ||
95                                     s->regs.config_cntl & APER_1_ENDIAN ?
96                                     true : false);
97             /* reset VBE regs then set up mode */
98             s->vga.vbe_regs[VBE_DISPI_INDEX_XRES] = h;
99             s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] = v;
100             s->vga.vbe_regs[VBE_DISPI_INDEX_BPP] = bpp;
101             /* enable mode via ioport so it updates vga regs */
102             vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE);
103             vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_ENABLED |
104                 VBE_DISPI_LFB_ENABLED | VBE_DISPI_NOCLEARMEM |
105                 (s->regs.dac_cntl & DAC_8BIT_EN ? VBE_DISPI_8BIT_DAC : 0));
106             /* now set offset and stride after enable as that resets these */
107             if (stride) {
108                 int bypp = DIV_ROUND_UP(bpp, BITS_PER_BYTE);
109 
110                 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_VIRT_WIDTH);
111                 vbe_ioport_write_data(&s->vga, 0, stride);
112                 stride *= bypp;
113                 if (offs % stride) {
114                     DPRINTF("CRTC offset is not multiple of pitch\n");
115                     vbe_ioport_write_index(&s->vga, 0,
116                                            VBE_DISPI_INDEX_X_OFFSET);
117                     vbe_ioport_write_data(&s->vga, 0, offs % stride / bypp);
118                 }
119                 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_Y_OFFSET);
120                 vbe_ioport_write_data(&s->vga, 0, offs / stride);
121                 DPRINTF("VBE offset (%d,%d), vbe_start_addr=%x\n",
122                         s->vga.vbe_regs[VBE_DISPI_INDEX_X_OFFSET],
123                         s->vga.vbe_regs[VBE_DISPI_INDEX_Y_OFFSET],
124                         s->vga.vbe_start_addr);
125             }
126         }
127     } else {
128         /* VGA mode enabled */
129         s->mode = VGA_MODE;
130         vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE);
131         vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED);
132     }
133 }
134 
135 /* Used by host side hardware cursor */
136 static void ati_cursor_define(ATIVGAState *s)
137 {
138     uint8_t data[1024];
139     uint32_t srcoff;
140     int i, j, idx = 0;
141 
142     if ((s->regs.cur_offset & BIT(31)) || s->cursor_guest_mode) {
143         return; /* Do not update cursor if locked or rendered by guest */
144     }
145     /* FIXME handle cur_hv_offs correctly */
146     srcoff = s->regs.cur_offset -
147         (s->regs.cur_hv_offs >> 16) - (s->regs.cur_hv_offs & 0xffff) * 16;
148     for (i = 0; i < 64; i++) {
149         for (j = 0; j < 8; j++, idx++) {
150             data[idx] = vga_read_byte(&s->vga, srcoff + i * 16 + j);
151             data[512 + idx] = vga_read_byte(&s->vga, srcoff + i * 16 + j + 8);
152         }
153     }
154     if (!s->cursor) {
155         s->cursor = cursor_alloc(64, 64);
156     }
157     cursor_set_mono(s->cursor, s->regs.cur_color1, s->regs.cur_color0,
158                     &data[512], 1, &data[0]);
159     dpy_cursor_define(s->vga.con, s->cursor);
160 }
161 
162 /* Alternatively support guest rendered hardware cursor */
163 static void ati_cursor_invalidate(VGACommonState *vga)
164 {
165     ATIVGAState *s = container_of(vga, ATIVGAState, vga);
166     int size = (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) ? 64 : 0;
167 
168     if (s->regs.cur_offset & BIT(31)) {
169         return; /* Do not update cursor if locked */
170     }
171     if (s->cursor_size != size ||
172         vga->hw_cursor_x != s->regs.cur_hv_pos >> 16 ||
173         vga->hw_cursor_y != (s->regs.cur_hv_pos & 0xffff) ||
174         s->cursor_offset != s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) -
175         (s->regs.cur_hv_offs & 0xffff) * 16) {
176         /* Remove old cursor then update and show new one if needed */
177         vga_invalidate_scanlines(vga, vga->hw_cursor_y, vga->hw_cursor_y + 63);
178         vga->hw_cursor_x = s->regs.cur_hv_pos >> 16;
179         vga->hw_cursor_y = s->regs.cur_hv_pos & 0xffff;
180         s->cursor_offset = s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) -
181                            (s->regs.cur_hv_offs & 0xffff) * 16;
182         s->cursor_size = size;
183         if (size) {
184             vga_invalidate_scanlines(vga,
185                                      vga->hw_cursor_y, vga->hw_cursor_y + 63);
186         }
187     }
188 }
189 
190 static void ati_cursor_draw_line(VGACommonState *vga, uint8_t *d, int scr_y)
191 {
192     ATIVGAState *s = container_of(vga, ATIVGAState, vga);
193     uint32_t srcoff;
194     uint32_t *dp = (uint32_t *)d;
195     int i, j, h;
196 
197     if (!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN) ||
198         scr_y < vga->hw_cursor_y || scr_y >= vga->hw_cursor_y + 64 ||
199         scr_y > s->regs.crtc_v_total_disp >> 16) {
200         return;
201     }
202     /* FIXME handle cur_hv_offs correctly */
203     srcoff = s->cursor_offset + (scr_y - vga->hw_cursor_y) * 16;
204     dp = &dp[vga->hw_cursor_x];
205     h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8;
206     for (i = 0; i < 8; i++) {
207         uint32_t color;
208         uint8_t abits = vga_read_byte(vga, srcoff + i);
209         uint8_t xbits = vga_read_byte(vga, srcoff + i + 8);
210         for (j = 0; j < 8; j++, abits <<= 1, xbits <<= 1) {
211             if (abits & BIT(7)) {
212                 if (xbits & BIT(7)) {
213                     color = dp[i * 8 + j] ^ 0xffffffff; /* complement */
214                 } else {
215                     continue; /* transparent, no change */
216                 }
217             } else {
218                 color = (xbits & BIT(7) ? s->regs.cur_color1 :
219                                           s->regs.cur_color0) | 0xff000000;
220             }
221             if (vga->hw_cursor_x + i * 8 + j >= h) {
222                 return; /* end of screen, don't span to next line */
223             }
224             dp[i * 8 + j] = color;
225         }
226     }
227 }
228 
229 static uint64_t ati_i2c(bitbang_i2c_interface *i2c, uint64_t data, int base)
230 {
231     bool c = (data & BIT(base + 17) ? !!(data & BIT(base + 1)) : 1);
232     bool d = (data & BIT(base + 16) ? !!(data & BIT(base)) : 1);
233 
234     bitbang_i2c_set(i2c, BITBANG_I2C_SCL, c);
235     d = bitbang_i2c_set(i2c, BITBANG_I2C_SDA, d);
236 
237     data &= ~0xf00ULL;
238     if (c) {
239         data |= BIT(base + 9);
240     }
241     if (d) {
242         data |= BIT(base + 8);
243     }
244     return data;
245 }
246 
247 static void ati_vga_update_irq(ATIVGAState *s)
248 {
249     pci_set_irq(&s->dev, !!(s->regs.gen_int_status & s->regs.gen_int_cntl));
250 }
251 
252 static void ati_vga_vblank_irq(void *opaque)
253 {
254     ATIVGAState *s = opaque;
255 
256     timer_mod(&s->vblank_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
257               NANOSECONDS_PER_SECOND / 60);
258     s->regs.gen_int_status |= CRTC_VBLANK_INT;
259     ati_vga_update_irq(s);
260 }
261 
262 static inline uint64_t ati_reg_read_offs(uint32_t reg, int offs,
263                                          unsigned int size)
264 {
265     if (offs == 0 && size == 4) {
266         return reg;
267     } else {
268         return extract32(reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE);
269     }
270 }
271 
272 static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size)
273 {
274     ATIVGAState *s = opaque;
275     uint64_t val = 0;
276 
277     switch (addr) {
278     case MM_INDEX:
279         val = s->regs.mm_index;
280         break;
281     case MM_DATA ... MM_DATA + 3:
282         /* indexed access to regs or memory */
283         if (s->regs.mm_index & BIT(31)) {
284             uint32_t idx = s->regs.mm_index & ~BIT(31);
285             if (idx <= s->vga.vram_size - size) {
286                 val = ldn_le_p(s->vga.vram_ptr + idx, size);
287             }
288         } else {
289             val = ati_mm_read(s, s->regs.mm_index + addr - MM_DATA, size);
290         }
291         break;
292     case BIOS_0_SCRATCH ... BUS_CNTL - 1:
293     {
294         int i = (addr - BIOS_0_SCRATCH) / 4;
295         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) {
296             break;
297         }
298         val = ati_reg_read_offs(s->regs.bios_scratch[i],
299                                 addr - (BIOS_0_SCRATCH + i * 4), size);
300         break;
301     }
302     case GEN_INT_CNTL:
303         val = s->regs.gen_int_cntl;
304         break;
305     case GEN_INT_STATUS:
306         val = s->regs.gen_int_status;
307         break;
308     case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3:
309         val = ati_reg_read_offs(s->regs.crtc_gen_cntl,
310                                 addr - CRTC_GEN_CNTL, size);
311         break;
312     case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3:
313         val = ati_reg_read_offs(s->regs.crtc_ext_cntl,
314                                 addr - CRTC_EXT_CNTL, size);
315         break;
316     case DAC_CNTL:
317         val = s->regs.dac_cntl;
318         break;
319     case GPIO_VGA_DDC:
320         val = s->regs.gpio_vga_ddc;
321         break;
322     case GPIO_DVI_DDC:
323         val = s->regs.gpio_dvi_ddc;
324         break;
325     case GPIO_MONID ... GPIO_MONID + 3:
326         val = ati_reg_read_offs(s->regs.gpio_monid,
327                                 addr - GPIO_MONID, size);
328         break;
329     case PALETTE_INDEX:
330         /* FIXME unaligned access */
331         val = vga_ioport_read(&s->vga, VGA_PEL_IR) << 16;
332         val |= vga_ioport_read(&s->vga, VGA_PEL_IW) & 0xff;
333         break;
334     case PALETTE_DATA:
335         val = vga_ioport_read(&s->vga, VGA_PEL_D);
336         break;
337     case CNFG_CNTL:
338         val = s->regs.config_cntl;
339         break;
340     case CNFG_MEMSIZE:
341         val = s->vga.vram_size;
342         break;
343     case CONFIG_APER_0_BASE:
344     case CONFIG_APER_1_BASE:
345         val = pci_default_read_config(&s->dev,
346                                       PCI_BASE_ADDRESS_0, size) & 0xfffffff0;
347         break;
348     case CONFIG_APER_SIZE:
349         val = s->vga.vram_size;
350         break;
351     case CONFIG_REG_1_BASE:
352         val = pci_default_read_config(&s->dev,
353                                       PCI_BASE_ADDRESS_2, size) & 0xfffffff0;
354         break;
355     case CONFIG_REG_APER_SIZE:
356         val = memory_region_size(&s->mm);
357         break;
358     case MC_STATUS:
359         val = 5;
360         break;
361     case RBBM_STATUS:
362     case GUI_STAT:
363         val = 64; /* free CMDFIFO entries */
364         break;
365     case CRTC_H_TOTAL_DISP:
366         val = s->regs.crtc_h_total_disp;
367         break;
368     case CRTC_H_SYNC_STRT_WID:
369         val = s->regs.crtc_h_sync_strt_wid;
370         break;
371     case CRTC_V_TOTAL_DISP:
372         val = s->regs.crtc_v_total_disp;
373         break;
374     case CRTC_V_SYNC_STRT_WID:
375         val = s->regs.crtc_v_sync_strt_wid;
376         break;
377     case CRTC_OFFSET:
378         val = s->regs.crtc_offset;
379         break;
380     case CRTC_OFFSET_CNTL:
381         val = s->regs.crtc_offset_cntl;
382         break;
383     case CRTC_PITCH:
384         val = s->regs.crtc_pitch;
385         break;
386     case 0xf00 ... 0xfff:
387         val = pci_default_read_config(&s->dev, addr - 0xf00, size);
388         break;
389     case CUR_OFFSET:
390         val = s->regs.cur_offset;
391         break;
392     case CUR_HORZ_VERT_POSN:
393         val = s->regs.cur_hv_pos;
394         val |= s->regs.cur_offset & BIT(31);
395         break;
396     case CUR_HORZ_VERT_OFF:
397         val = s->regs.cur_hv_offs;
398         val |= s->regs.cur_offset & BIT(31);
399         break;
400     case CUR_CLR0:
401         val = s->regs.cur_color0;
402         break;
403     case CUR_CLR1:
404         val = s->regs.cur_color1;
405         break;
406     case DST_OFFSET:
407         val = s->regs.dst_offset;
408         break;
409     case DST_PITCH:
410         val = s->regs.dst_pitch;
411         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
412             val &= s->regs.dst_tile << 16;
413         }
414         break;
415     case DST_WIDTH:
416         val = s->regs.dst_width;
417         break;
418     case DST_HEIGHT:
419         val = s->regs.dst_height;
420         break;
421     case SRC_X:
422         val = s->regs.src_x;
423         break;
424     case SRC_Y:
425         val = s->regs.src_y;
426         break;
427     case DST_X:
428         val = s->regs.dst_x;
429         break;
430     case DST_Y:
431         val = s->regs.dst_y;
432         break;
433     case DP_GUI_MASTER_CNTL:
434         val = s->regs.dp_gui_master_cntl;
435         break;
436     case SRC_OFFSET:
437         val = s->regs.src_offset;
438         break;
439     case SRC_PITCH:
440         val = s->regs.src_pitch;
441         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
442             val &= s->regs.src_tile << 16;
443         }
444         break;
445     case DP_BRUSH_BKGD_CLR:
446         val = s->regs.dp_brush_bkgd_clr;
447         break;
448     case DP_BRUSH_FRGD_CLR:
449         val = s->regs.dp_brush_frgd_clr;
450         break;
451     case DP_SRC_FRGD_CLR:
452         val = s->regs.dp_src_frgd_clr;
453         break;
454     case DP_SRC_BKGD_CLR:
455         val = s->regs.dp_src_bkgd_clr;
456         break;
457     case DP_CNTL:
458         val = s->regs.dp_cntl;
459         break;
460     case DP_DATATYPE:
461         val = s->regs.dp_datatype;
462         break;
463     case DP_MIX:
464         val = s->regs.dp_mix;
465         break;
466     case DP_WRITE_MASK:
467         val = s->regs.dp_write_mask;
468         break;
469     case DEFAULT_OFFSET:
470         val = s->regs.default_offset;
471         if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) {
472             val >>= 10;
473             val |= s->regs.default_pitch << 16;
474             val |= s->regs.default_tile << 30;
475         }
476         break;
477     case DEFAULT_PITCH:
478         val = s->regs.default_pitch;
479         val |= s->regs.default_tile << 16;
480         break;
481     case DEFAULT_SC_BOTTOM_RIGHT:
482         val = s->regs.default_sc_bottom_right;
483         break;
484     default:
485         break;
486     }
487     if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) {
488         trace_ati_mm_read(size, addr, ati_reg_name(addr & ~3ULL), val);
489     }
490     return val;
491 }
492 
493 static inline void ati_reg_write_offs(uint32_t *reg, int offs,
494                                       uint64_t data, unsigned int size)
495 {
496     if (offs == 0 && size == 4) {
497         *reg = data;
498     } else {
499         *reg = deposit32(*reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE,
500                          data);
501     }
502 }
503 
504 static void ati_mm_write(void *opaque, hwaddr addr,
505                            uint64_t data, unsigned int size)
506 {
507     ATIVGAState *s = opaque;
508 
509     if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) {
510         trace_ati_mm_write(size, addr, ati_reg_name(addr & ~3ULL), data);
511     }
512     switch (addr) {
513     case MM_INDEX:
514         s->regs.mm_index = data;
515         break;
516     case MM_DATA ... MM_DATA + 3:
517         /* indexed access to regs or memory */
518         if (s->regs.mm_index & BIT(31)) {
519             uint32_t idx = s->regs.mm_index & ~BIT(31);
520             if (idx <= s->vga.vram_size - size) {
521                 stn_le_p(s->vga.vram_ptr + idx, size, data);
522             }
523         } else {
524             ati_mm_write(s, s->regs.mm_index + addr - MM_DATA, data, size);
525         }
526         break;
527     case BIOS_0_SCRATCH ... BUS_CNTL - 1:
528     {
529         int i = (addr - BIOS_0_SCRATCH) / 4;
530         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) {
531             break;
532         }
533         ati_reg_write_offs(&s->regs.bios_scratch[i],
534                            addr - (BIOS_0_SCRATCH + i * 4), data, size);
535         break;
536     }
537     case GEN_INT_CNTL:
538         s->regs.gen_int_cntl = data;
539         if (data & CRTC_VBLANK_INT) {
540             ati_vga_vblank_irq(s);
541         } else {
542             timer_del(&s->vblank_timer);
543             ati_vga_update_irq(s);
544         }
545         break;
546     case GEN_INT_STATUS:
547         data &= (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF ?
548                  0x000f040fUL : 0xfc080effUL);
549         s->regs.gen_int_status &= ~data;
550         ati_vga_update_irq(s);
551         break;
552     case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3:
553     {
554         uint32_t val = s->regs.crtc_gen_cntl;
555         ati_reg_write_offs(&s->regs.crtc_gen_cntl,
556                            addr - CRTC_GEN_CNTL, data, size);
557         if ((val & CRTC2_CUR_EN) != (s->regs.crtc_gen_cntl & CRTC2_CUR_EN)) {
558             if (s->cursor_guest_mode) {
559                 s->vga.force_shadow = !!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN);
560             } else {
561                 if (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) {
562                     ati_cursor_define(s);
563                 }
564                 dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16,
565                               s->regs.cur_hv_pos & 0xffff,
566                               (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) != 0);
567             }
568         }
569         if ((val & (CRTC2_EXT_DISP_EN | CRTC2_EN)) !=
570             (s->regs.crtc_gen_cntl & (CRTC2_EXT_DISP_EN | CRTC2_EN))) {
571             ati_vga_switch_mode(s);
572         }
573         break;
574     }
575     case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3:
576     {
577         uint32_t val = s->regs.crtc_ext_cntl;
578         ati_reg_write_offs(&s->regs.crtc_ext_cntl,
579                            addr - CRTC_EXT_CNTL, data, size);
580         if (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS) {
581             DPRINTF("Display disabled\n");
582             s->vga.ar_index &= ~BIT(5);
583         } else {
584             DPRINTF("Display enabled\n");
585             s->vga.ar_index |= BIT(5);
586             ati_vga_switch_mode(s);
587         }
588         if ((val & CRT_CRTC_DISPLAY_DIS) !=
589             (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS)) {
590             ati_vga_switch_mode(s);
591         }
592         break;
593     }
594     case DAC_CNTL:
595         s->regs.dac_cntl = data & 0xffffe3ff;
596         s->vga.dac_8bit = !!(data & DAC_8BIT_EN);
597         break;
598     case GPIO_VGA_DDC:
599         if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) {
600             /* FIXME: Maybe add a property to select VGA or DVI port? */
601         }
602         break;
603     case GPIO_DVI_DDC:
604         if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) {
605             s->regs.gpio_dvi_ddc = ati_i2c(&s->bbi2c, data, 0);
606         }
607         break;
608     case GPIO_MONID ... GPIO_MONID + 3:
609         /* FIXME What does Radeon have here? */
610         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
611             ati_reg_write_offs(&s->regs.gpio_monid,
612                                addr - GPIO_MONID, data, size);
613             /*
614              * Rage128p accesses DDC used to get EDID via these bits.
615              * Because some drivers access this via multiple byte writes
616              * we have to be careful when we send bits to avoid spurious
617              * changes in bitbang_i2c state. So only do it when mask is set
618              * and either the enable bits are changed or output bits changed
619              * while enabled.
620              */
621             if ((s->regs.gpio_monid & BIT(25)) &&
622                 ((addr <= GPIO_MONID + 2 && addr + size > GPIO_MONID + 2) ||
623                  (addr == GPIO_MONID && (s->regs.gpio_monid & 0x60000)))) {
624                 s->regs.gpio_monid = ati_i2c(&s->bbi2c, s->regs.gpio_monid, 1);
625             }
626         }
627         break;
628     case PALETTE_INDEX ... PALETTE_INDEX + 3:
629         if (size == 4) {
630             vga_ioport_write(&s->vga, VGA_PEL_IR, (data >> 16) & 0xff);
631             vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff);
632         } else {
633             if (addr == PALETTE_INDEX) {
634                 vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff);
635             } else {
636                 vga_ioport_write(&s->vga, VGA_PEL_IR, data & 0xff);
637             }
638         }
639         break;
640     case PALETTE_DATA ... PALETTE_DATA + 3:
641         data <<= addr - PALETTE_DATA;
642         data = bswap32(data) >> 8;
643         vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
644         data >>= 8;
645         vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
646         data >>= 8;
647         vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
648         break;
649     case CNFG_CNTL:
650         s->regs.config_cntl = data;
651         break;
652     case CRTC_H_TOTAL_DISP:
653         s->regs.crtc_h_total_disp = data & 0x07ff07ff;
654         break;
655     case CRTC_H_SYNC_STRT_WID:
656         s->regs.crtc_h_sync_strt_wid = data & 0x17bf1fff;
657         break;
658     case CRTC_V_TOTAL_DISP:
659         s->regs.crtc_v_total_disp = data & 0x0fff0fff;
660         break;
661     case CRTC_V_SYNC_STRT_WID:
662         s->regs.crtc_v_sync_strt_wid = data & 0x9f0fff;
663         break;
664     case CRTC_OFFSET:
665         s->regs.crtc_offset = data & 0xc7ffffff;
666         break;
667     case CRTC_OFFSET_CNTL:
668         s->regs.crtc_offset_cntl = data; /* FIXME */
669         break;
670     case CRTC_PITCH:
671         s->regs.crtc_pitch = data & 0x07ff07ff;
672         break;
673     case 0xf00 ... 0xfff:
674         /* read-only copy of PCI config space so ignore writes */
675         break;
676     case CUR_OFFSET:
677         if (s->regs.cur_offset != (data & 0x87fffff0)) {
678             s->regs.cur_offset = data & 0x87fffff0;
679             ati_cursor_define(s);
680         }
681         break;
682     case CUR_HORZ_VERT_POSN:
683         s->regs.cur_hv_pos = data & 0x3fff0fff;
684         if (data & BIT(31)) {
685             s->regs.cur_offset |= data & BIT(31);
686         } else if (s->regs.cur_offset & BIT(31)) {
687             s->regs.cur_offset &= ~BIT(31);
688             ati_cursor_define(s);
689         }
690         if (!s->cursor_guest_mode &&
691             (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) && !(data & BIT(31))) {
692             dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16,
693                           s->regs.cur_hv_pos & 0xffff, 1);
694         }
695         break;
696     case CUR_HORZ_VERT_OFF:
697         s->regs.cur_hv_offs = data & 0x3f003f;
698         if (data & BIT(31)) {
699             s->regs.cur_offset |= data & BIT(31);
700         } else if (s->regs.cur_offset & BIT(31)) {
701             s->regs.cur_offset &= ~BIT(31);
702             ati_cursor_define(s);
703         }
704         break;
705     case CUR_CLR0:
706         if (s->regs.cur_color0 != (data & 0xffffff)) {
707             s->regs.cur_color0 = data & 0xffffff;
708             ati_cursor_define(s);
709         }
710         break;
711     case CUR_CLR1:
712         /*
713          * Update cursor unconditionally here because some clients set up
714          * other registers before actually writing cursor data to memory at
715          * offset so we would miss cursor change unless always updating here
716          */
717         s->regs.cur_color1 = data & 0xffffff;
718         ati_cursor_define(s);
719         break;
720     case DST_OFFSET:
721         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
722             s->regs.dst_offset = data & 0xfffffff0;
723         } else {
724             s->regs.dst_offset = data & 0xfffffc00;
725         }
726         break;
727     case DST_PITCH:
728         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
729             s->regs.dst_pitch = data & 0x3fff;
730             s->regs.dst_tile = (data >> 16) & 1;
731         } else {
732             s->regs.dst_pitch = data & 0x3ff0;
733         }
734         break;
735     case DST_TILE:
736         if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY) {
737             s->regs.dst_tile = data & 3;
738         }
739         break;
740     case DST_WIDTH:
741         s->regs.dst_width = data & 0x3fff;
742         ati_2d_blt(s);
743         break;
744     case DST_HEIGHT:
745         s->regs.dst_height = data & 0x3fff;
746         break;
747     case SRC_X:
748         s->regs.src_x = data & 0x3fff;
749         break;
750     case SRC_Y:
751         s->regs.src_y = data & 0x3fff;
752         break;
753     case DST_X:
754         s->regs.dst_x = data & 0x3fff;
755         break;
756     case DST_Y:
757         s->regs.dst_y = data & 0x3fff;
758         break;
759     case SRC_PITCH_OFFSET:
760         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
761             s->regs.src_offset = (data & 0x1fffff) << 5;
762             s->regs.src_pitch = (data & 0x7fe00000) >> 21;
763             s->regs.src_tile = data >> 31;
764         } else {
765             s->regs.src_offset = (data & 0x3fffff) << 10;
766             s->regs.src_pitch = (data & 0x3fc00000) >> 16;
767             s->regs.src_tile = (data >> 30) & 1;
768         }
769         break;
770     case DST_PITCH_OFFSET:
771         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
772             s->regs.dst_offset = (data & 0x1fffff) << 5;
773             s->regs.dst_pitch = (data & 0x7fe00000) >> 21;
774             s->regs.dst_tile = data >> 31;
775         } else {
776             s->regs.dst_offset = (data & 0x3fffff) << 10;
777             s->regs.dst_pitch = (data & 0x3fc00000) >> 16;
778             s->regs.dst_tile = data >> 30;
779         }
780         break;
781     case SRC_Y_X:
782         s->regs.src_x = data & 0x3fff;
783         s->regs.src_y = (data >> 16) & 0x3fff;
784         break;
785     case DST_Y_X:
786         s->regs.dst_x = data & 0x3fff;
787         s->regs.dst_y = (data >> 16) & 0x3fff;
788         break;
789     case DST_HEIGHT_WIDTH:
790         s->regs.dst_width = data & 0x3fff;
791         s->regs.dst_height = (data >> 16) & 0x3fff;
792         ati_2d_blt(s);
793         break;
794     case DP_GUI_MASTER_CNTL:
795         s->regs.dp_gui_master_cntl = data & 0xf800000f;
796         s->regs.dp_datatype = (data & 0x0f00) >> 8 | (data & 0x30f0) << 4 |
797                               (data & 0x4000) << 16;
798         s->regs.dp_mix = (data & GMC_ROP3_MASK) | (data & 0x7000000) >> 16;
799         break;
800     case DST_WIDTH_X:
801         s->regs.dst_x = data & 0x3fff;
802         s->regs.dst_width = (data >> 16) & 0x3fff;
803         ati_2d_blt(s);
804         break;
805     case SRC_X_Y:
806         s->regs.src_y = data & 0x3fff;
807         s->regs.src_x = (data >> 16) & 0x3fff;
808         break;
809     case DST_X_Y:
810         s->regs.dst_y = data & 0x3fff;
811         s->regs.dst_x = (data >> 16) & 0x3fff;
812         break;
813     case DST_WIDTH_HEIGHT:
814         s->regs.dst_height = data & 0x3fff;
815         s->regs.dst_width = (data >> 16) & 0x3fff;
816         ati_2d_blt(s);
817         break;
818     case DST_HEIGHT_Y:
819         s->regs.dst_y = data & 0x3fff;
820         s->regs.dst_height = (data >> 16) & 0x3fff;
821         break;
822     case SRC_OFFSET:
823         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
824             s->regs.src_offset = data & 0xfffffff0;
825         } else {
826             s->regs.src_offset = data & 0xfffffc00;
827         }
828         break;
829     case SRC_PITCH:
830         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
831             s->regs.src_pitch = data & 0x3fff;
832             s->regs.src_tile = (data >> 16) & 1;
833         } else {
834             s->regs.src_pitch = data & 0x3ff0;
835         }
836         break;
837     case DP_BRUSH_BKGD_CLR:
838         s->regs.dp_brush_bkgd_clr = data;
839         break;
840     case DP_BRUSH_FRGD_CLR:
841         s->regs.dp_brush_frgd_clr = data;
842         break;
843     case DP_CNTL:
844         s->regs.dp_cntl = data;
845         break;
846     case DP_DATATYPE:
847         s->regs.dp_datatype = data & 0xe0070f0f;
848         break;
849     case DP_MIX:
850         s->regs.dp_mix = data & 0x00ff0700;
851         break;
852     case DP_WRITE_MASK:
853         s->regs.dp_write_mask = data;
854         break;
855     case DEFAULT_OFFSET:
856         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
857             s->regs.default_offset = data & 0xfffffff0;
858         } else {
859             /* Radeon has DEFAULT_PITCH_OFFSET here like DST_PITCH_OFFSET */
860             s->regs.default_offset = (data & 0x3fffff) << 10;
861             s->regs.default_pitch = (data & 0x3fc00000) >> 16;
862             s->regs.default_tile = data >> 30;
863         }
864         break;
865     case DEFAULT_PITCH:
866         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
867             s->regs.default_pitch = data & 0x3fff;
868             s->regs.default_tile = (data >> 16) & 1;
869         }
870         break;
871     case DEFAULT_SC_BOTTOM_RIGHT:
872         s->regs.default_sc_bottom_right = data & 0x3fff3fff;
873         break;
874     default:
875         break;
876     }
877 }
878 
879 static const MemoryRegionOps ati_mm_ops = {
880     .read = ati_mm_read,
881     .write = ati_mm_write,
882     .endianness = DEVICE_LITTLE_ENDIAN,
883 };
884 
885 static void ati_vga_realize(PCIDevice *dev, Error **errp)
886 {
887     ATIVGAState *s = ATI_VGA(dev);
888     VGACommonState *vga = &s->vga;
889 
890     if (s->model) {
891         int i;
892         for (i = 0; i < ARRAY_SIZE(ati_model_aliases); i++) {
893             if (!strcmp(s->model, ati_model_aliases[i].name)) {
894                 s->dev_id = ati_model_aliases[i].dev_id;
895                 break;
896             }
897         }
898         if (i >= ARRAY_SIZE(ati_model_aliases)) {
899             warn_report("Unknown ATI VGA model name, "
900                         "using default rage128p");
901         }
902     }
903     if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF &&
904         s->dev_id != PCI_DEVICE_ID_ATI_RADEON_QY) {
905         error_setg(errp, "Unknown ATI VGA device id, "
906                    "only 0x5046 and 0x5159 are supported");
907         return;
908     }
909     pci_set_word(dev->config + PCI_DEVICE_ID, s->dev_id);
910 
911     if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY &&
912         s->vga.vram_size_mb < 16) {
913         warn_report("Too small video memory for device id");
914         s->vga.vram_size_mb = 16;
915     }
916 
917     /* init vga bits */
918     vga_common_init(vga, OBJECT(s));
919     vga_init(vga, OBJECT(s), pci_address_space(dev),
920              pci_address_space_io(dev), true);
921     vga->con = graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, &s->vga);
922     if (s->cursor_guest_mode) {
923         vga->cursor_invalidate = ati_cursor_invalidate;
924         vga->cursor_draw_line = ati_cursor_draw_line;
925     }
926 
927     /* ddc, edid */
928     I2CBus *i2cbus = i2c_init_bus(DEVICE(s), "ati-vga.ddc");
929     bitbang_i2c_init(&s->bbi2c, i2cbus);
930     I2CSlave *i2cddc = I2C_SLAVE(qdev_create(BUS(i2cbus), TYPE_I2CDDC));
931     i2c_set_slave_address(i2cddc, 0x50);
932 
933     /* mmio register space */
934     memory_region_init_io(&s->mm, OBJECT(s), &ati_mm_ops, s,
935                           "ati.mmregs", 0x4000);
936     /* io space is alias to beginning of mmregs */
937     memory_region_init_alias(&s->io, OBJECT(s), "ati.io", &s->mm, 0, 0x100);
938 
939     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram);
940     pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
941     pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mm);
942 
943     /* most interrupts are not yet emulated but MacOS needs at least VBlank */
944     dev->config[PCI_INTERRUPT_PIN] = 1;
945     timer_init_ns(&s->vblank_timer, QEMU_CLOCK_VIRTUAL, ati_vga_vblank_irq, s);
946 }
947 
948 static void ati_vga_reset(DeviceState *dev)
949 {
950     ATIVGAState *s = ATI_VGA(dev);
951 
952     timer_del(&s->vblank_timer);
953     ati_vga_update_irq(s);
954 
955     /* reset vga */
956     vga_common_reset(&s->vga);
957     s->mode = VGA_MODE;
958 }
959 
960 static void ati_vga_exit(PCIDevice *dev)
961 {
962     ATIVGAState *s = ATI_VGA(dev);
963 
964     timer_del(&s->vblank_timer);
965     graphic_console_close(s->vga.con);
966 }
967 
968 static Property ati_vga_properties[] = {
969     DEFINE_PROP_UINT32("vgamem_mb", ATIVGAState, vga.vram_size_mb, 16),
970     DEFINE_PROP_STRING("model", ATIVGAState, model),
971     DEFINE_PROP_UINT16("x-device-id", ATIVGAState, dev_id,
972                        PCI_DEVICE_ID_ATI_RAGE128_PF),
973     DEFINE_PROP_BOOL("guest_hwcursor", ATIVGAState, cursor_guest_mode, false),
974     DEFINE_PROP_END_OF_LIST()
975 };
976 
977 static void ati_vga_class_init(ObjectClass *klass, void *data)
978 {
979     DeviceClass *dc = DEVICE_CLASS(klass);
980     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
981 
982     dc->reset = ati_vga_reset;
983     device_class_set_props(dc, ati_vga_properties);
984     dc->hotpluggable = false;
985     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
986 
987     k->class_id = PCI_CLASS_DISPLAY_VGA;
988     k->vendor_id = PCI_VENDOR_ID_ATI;
989     k->device_id = PCI_DEVICE_ID_ATI_RAGE128_PF;
990     k->romfile = "vgabios-ati.bin";
991     k->realize = ati_vga_realize;
992     k->exit = ati_vga_exit;
993 }
994 
995 static const TypeInfo ati_vga_info = {
996     .name = TYPE_ATI_VGA,
997     .parent = TYPE_PCI_DEVICE,
998     .instance_size = sizeof(ATIVGAState),
999     .class_init = ati_vga_class_init,
1000     .interfaces = (InterfaceInfo[]) {
1001           { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1002           { },
1003     },
1004 };
1005 
1006 static void ati_vga_register_types(void)
1007 {
1008     type_register_static(&ati_vga_info);
1009 }
1010 
1011 type_init(ati_vga_register_types)
1012