1 /*
2 * SPDX-License-Identifier: GPL-2.0-or-later
3 *
4 * Emulation of a CXL Switch Mailbox CCI PCIe function.
5 *
6 * Copyright (c) 2023 Huawei Technologies.
7 *
8 * From www.computeexpresslink.org
9 * Compute Express Link (CXL) Specification revision 3.0 Version 1.0
10 */
11 #include "qemu/osdep.h"
12 #include "hw/pci/pci.h"
13 #include "hw/pci-bridge/cxl_upstream_port.h"
14 #include "qapi/error.h"
15 #include "qemu/log.h"
16 #include "qemu/module.h"
17 #include "hw/qdev-properties.h"
18 #include "hw/cxl/cxl.h"
19
cswmbcci_reset(DeviceState * dev)20 static void cswmbcci_reset(DeviceState *dev)
21 {
22 CSWMBCCIDev *cswmb = CXL_SWITCH_MAILBOX_CCI(dev);
23 cxl_device_register_init_swcci(cswmb);
24 }
25
cswbcci_realize(PCIDevice * pci_dev,Error ** errp)26 static void cswbcci_realize(PCIDevice *pci_dev, Error **errp)
27 {
28 CSWMBCCIDev *cswmb = CXL_SWITCH_MAILBOX_CCI(pci_dev);
29 CXLComponentState *cxl_cstate = &cswmb->cxl_cstate;
30 CXLDeviceState *cxl_dstate = &cswmb->cxl_dstate;
31 CXLDVSECRegisterLocator *regloc_dvsec;
32 CXLUpstreamPort *usp;
33
34 if (!cswmb->target) {
35 error_setg(errp, "Target not set");
36 return;
37 }
38 usp = CXL_USP(cswmb->target);
39
40 pcie_endpoint_cap_init(pci_dev, 0x80);
41 cxl_cstate->dvsec_offset = 0x100;
42 cxl_cstate->pdev = pci_dev;
43 cswmb->cci = &usp->swcci;
44 cxl_device_register_block_init(OBJECT(pci_dev), cxl_dstate, cswmb->cci);
45 pci_register_bar(pci_dev, 0,
46 PCI_BASE_ADDRESS_SPACE_MEMORY |
47 PCI_BASE_ADDRESS_MEM_TYPE_64,
48 &cxl_dstate->device_registers);
49 regloc_dvsec = &(CXLDVSECRegisterLocator) {
50 .rsvd = 0,
51 .reg0_base_lo = RBI_CXL_DEVICE_REG | 0,
52 .reg0_base_hi = 0,
53 };
54 cxl_component_create_dvsec(cxl_cstate, CXL3_SWITCH_MAILBOX_CCI,
55 REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
56 REG_LOC_DVSEC_REVID, (uint8_t *)regloc_dvsec);
57
58 cxl_initialize_mailbox_swcci(cswmb->cci, DEVICE(pci_dev),
59 DEVICE(cswmb->target),
60 CXL_MAILBOX_MAX_PAYLOAD_SIZE);
61 }
62
cswmbcci_exit(PCIDevice * pci_dev)63 static void cswmbcci_exit(PCIDevice *pci_dev)
64 {
65 /* Nothing to do here yet */
66 }
67
68 static Property cxl_switch_cci_props[] = {
69 DEFINE_PROP_LINK("target", CSWMBCCIDev,
70 target, TYPE_CXL_USP, PCIDevice *),
71 DEFINE_PROP_END_OF_LIST(),
72 };
73
cswmbcci_class_init(ObjectClass * oc,void * data)74 static void cswmbcci_class_init(ObjectClass *oc, void *data)
75 {
76 DeviceClass *dc = DEVICE_CLASS(oc);
77 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
78
79 pc->realize = cswbcci_realize;
80 pc->exit = cswmbcci_exit;
81 /* Serial bus, CXL Switch CCI */
82 pc->class_id = 0x0c0b;
83 /*
84 * Huawei Technologies
85 * CXL Switch Mailbox CCI - DID assigned for emulation only.
86 * No real hardware will ever use this ID.
87 */
88 pc->vendor_id = 0x19e5;
89 pc->device_id = 0xa123;
90 pc->revision = 0;
91 dc->desc = "CXL Switch Mailbox CCI";
92 device_class_set_legacy_reset(dc, cswmbcci_reset);
93 device_class_set_props(dc, cxl_switch_cci_props);
94 }
95
96 static const TypeInfo cswmbcci_info = {
97 .name = TYPE_CXL_SWITCH_MAILBOX_CCI,
98 .parent = TYPE_PCI_DEVICE,
99 .class_init = cswmbcci_class_init,
100 .instance_size = sizeof(CSWMBCCIDev),
101 .interfaces = (InterfaceInfo[]) {
102 { INTERFACE_PCIE_DEVICE },
103 { }
104 },
105 };
106
cxl_switch_mailbox_cci_register(void)107 static void cxl_switch_mailbox_cci_register(void)
108 {
109 type_register_static(&cswmbcci_info);
110 }
111 type_init(cxl_switch_mailbox_cci_register);
112