1 /* 2 * CXL Utility library for mailbox interface 3 * 4 * Copyright(C) 2020 Intel Corporation. 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/cxl/cxl.h" 12 #include "hw/pci/pci.h" 13 #include "qemu/cutils.h" 14 #include "qemu/log.h" 15 #include "qemu/units.h" 16 #include "qemu/uuid.h" 17 18 #define CXL_CAPACITY_MULTIPLIER (256 * MiB) 19 20 /* 21 * How to add a new command, example. The command set FOO, with cmd BAR. 22 * 1. Add the command set and cmd to the enum. 23 * FOO = 0x7f, 24 * #define BAR 0 25 * 2. Implement the handler 26 * static CXLRetCode cmd_foo_bar(struct cxl_cmd *cmd, 27 * CXLDeviceState *cxl_dstate, uint16_t *len) 28 * 3. Add the command to the cxl_cmd_set[][] 29 * [FOO][BAR] = { "FOO_BAR", cmd_foo_bar, x, y }, 30 * 4. Implement your handler 31 * define_mailbox_handler(FOO_BAR) { ... return CXL_MBOX_SUCCESS; } 32 * 33 * 34 * Writing the handler: 35 * The handler will provide the &struct cxl_cmd, the &CXLDeviceState, and the 36 * in/out length of the payload. The handler is responsible for consuming the 37 * payload from cmd->payload and operating upon it as necessary. It must then 38 * fill the output data into cmd->payload (overwriting what was there), 39 * setting the length, and returning a valid return code. 40 * 41 * XXX: The handler need not worry about endianess. The payload is read out of 42 * a register interface that already deals with it. 43 */ 44 45 enum { 46 EVENTS = 0x01, 47 #define GET_RECORDS 0x0 48 #define CLEAR_RECORDS 0x1 49 #define GET_INTERRUPT_POLICY 0x2 50 #define SET_INTERRUPT_POLICY 0x3 51 FIRMWARE_UPDATE = 0x02, 52 #define GET_INFO 0x0 53 TIMESTAMP = 0x03, 54 #define GET 0x0 55 #define SET 0x1 56 LOGS = 0x04, 57 #define GET_SUPPORTED 0x0 58 #define GET_LOG 0x1 59 IDENTIFY = 0x40, 60 #define MEMORY_DEVICE 0x0 61 CCLS = 0x41, 62 #define GET_PARTITION_INFO 0x0 63 #define GET_LSA 0x2 64 #define SET_LSA 0x3 65 MEDIA_AND_POISON = 0x43, 66 #define GET_POISON_LIST 0x0 67 }; 68 69 /* 8.2.8.4.5.1 Command Return Codes */ 70 typedef enum { 71 CXL_MBOX_SUCCESS = 0x0, 72 CXL_MBOX_BG_STARTED = 0x1, 73 CXL_MBOX_INVALID_INPUT = 0x2, 74 CXL_MBOX_UNSUPPORTED = 0x3, 75 CXL_MBOX_INTERNAL_ERROR = 0x4, 76 CXL_MBOX_RETRY_REQUIRED = 0x5, 77 CXL_MBOX_BUSY = 0x6, 78 CXL_MBOX_MEDIA_DISABLED = 0x7, 79 CXL_MBOX_FW_XFER_IN_PROGRESS = 0x8, 80 CXL_MBOX_FW_XFER_OUT_OF_ORDER = 0x9, 81 CXL_MBOX_FW_AUTH_FAILED = 0xa, 82 CXL_MBOX_FW_INVALID_SLOT = 0xb, 83 CXL_MBOX_FW_ROLLEDBACK = 0xc, 84 CXL_MBOX_FW_REST_REQD = 0xd, 85 CXL_MBOX_INVALID_HANDLE = 0xe, 86 CXL_MBOX_INVALID_PA = 0xf, 87 CXL_MBOX_INJECT_POISON_LIMIT = 0x10, 88 CXL_MBOX_PERMANENT_MEDIA_FAILURE = 0x11, 89 CXL_MBOX_ABORTED = 0x12, 90 CXL_MBOX_INVALID_SECURITY_STATE = 0x13, 91 CXL_MBOX_INCORRECT_PASSPHRASE = 0x14, 92 CXL_MBOX_UNSUPPORTED_MAILBOX = 0x15, 93 CXL_MBOX_INVALID_PAYLOAD_LENGTH = 0x16, 94 CXL_MBOX_MAX = 0x17 95 } CXLRetCode; 96 97 struct cxl_cmd; 98 typedef CXLRetCode (*opcode_handler)(struct cxl_cmd *cmd, 99 CXLDeviceState *cxl_dstate, uint16_t *len); 100 struct cxl_cmd { 101 const char *name; 102 opcode_handler handler; 103 ssize_t in; 104 uint16_t effect; /* Reported in CEL */ 105 uint8_t *payload; 106 }; 107 108 #define DEFINE_MAILBOX_HANDLER_ZEROED(name, size) \ 109 uint16_t __zero##name = size; \ 110 static CXLRetCode cmd_##name(struct cxl_cmd *cmd, \ 111 CXLDeviceState *cxl_dstate, uint16_t *len) \ 112 { \ 113 *len = __zero##name; \ 114 memset(cmd->payload, 0, *len); \ 115 return CXL_MBOX_SUCCESS; \ 116 } 117 #define DEFINE_MAILBOX_HANDLER_NOP(name) \ 118 static CXLRetCode cmd_##name(struct cxl_cmd *cmd, \ 119 CXLDeviceState *cxl_dstate, uint16_t *len) \ 120 { \ 121 return CXL_MBOX_SUCCESS; \ 122 } 123 124 DEFINE_MAILBOX_HANDLER_ZEROED(events_get_records, 0x20); 125 DEFINE_MAILBOX_HANDLER_NOP(events_clear_records); 126 DEFINE_MAILBOX_HANDLER_ZEROED(events_get_interrupt_policy, 4); 127 DEFINE_MAILBOX_HANDLER_NOP(events_set_interrupt_policy); 128 129 /* 8.2.9.2.1 */ 130 static CXLRetCode cmd_firmware_update_get_info(struct cxl_cmd *cmd, 131 CXLDeviceState *cxl_dstate, 132 uint16_t *len) 133 { 134 struct { 135 uint8_t slots_supported; 136 uint8_t slot_info; 137 uint8_t caps; 138 uint8_t rsvd[0xd]; 139 char fw_rev1[0x10]; 140 char fw_rev2[0x10]; 141 char fw_rev3[0x10]; 142 char fw_rev4[0x10]; 143 } QEMU_PACKED *fw_info; 144 QEMU_BUILD_BUG_ON(sizeof(*fw_info) != 0x50); 145 146 if ((cxl_dstate->vmem_size < CXL_CAPACITY_MULTIPLIER) || 147 (cxl_dstate->pmem_size < CXL_CAPACITY_MULTIPLIER)) { 148 return CXL_MBOX_INTERNAL_ERROR; 149 } 150 151 fw_info = (void *)cmd->payload; 152 memset(fw_info, 0, sizeof(*fw_info)); 153 154 fw_info->slots_supported = 2; 155 fw_info->slot_info = BIT(0) | BIT(3); 156 fw_info->caps = 0; 157 pstrcpy(fw_info->fw_rev1, sizeof(fw_info->fw_rev1), "BWFW VERSION 0"); 158 159 *len = sizeof(*fw_info); 160 return CXL_MBOX_SUCCESS; 161 } 162 163 /* 8.2.9.3.1 */ 164 static CXLRetCode cmd_timestamp_get(struct cxl_cmd *cmd, 165 CXLDeviceState *cxl_dstate, 166 uint16_t *len) 167 { 168 uint64_t final_time = cxl_device_get_timestamp(cxl_dstate); 169 170 stq_le_p(cmd->payload, final_time); 171 *len = 8; 172 173 return CXL_MBOX_SUCCESS; 174 } 175 176 /* 8.2.9.3.2 */ 177 static CXLRetCode cmd_timestamp_set(struct cxl_cmd *cmd, 178 CXLDeviceState *cxl_dstate, 179 uint16_t *len) 180 { 181 cxl_dstate->timestamp.set = true; 182 cxl_dstate->timestamp.last_set = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 183 184 cxl_dstate->timestamp.host_set = le64_to_cpu(*(uint64_t *)cmd->payload); 185 186 *len = 0; 187 return CXL_MBOX_SUCCESS; 188 } 189 190 /* CXL 3.0 8.2.9.5.2.1 Command Effects Log (CEL) */ 191 static const QemuUUID cel_uuid = { 192 .data = UUID(0x0da9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 193 0x96, 0xb1, 0x62, 0x3b, 0x3f, 0x17) 194 }; 195 196 /* 8.2.9.4.1 */ 197 static CXLRetCode cmd_logs_get_supported(struct cxl_cmd *cmd, 198 CXLDeviceState *cxl_dstate, 199 uint16_t *len) 200 { 201 struct { 202 uint16_t entries; 203 uint8_t rsvd[6]; 204 struct { 205 QemuUUID uuid; 206 uint32_t size; 207 } log_entries[1]; 208 } QEMU_PACKED *supported_logs = (void *)cmd->payload; 209 QEMU_BUILD_BUG_ON(sizeof(*supported_logs) != 0x1c); 210 211 supported_logs->entries = 1; 212 supported_logs->log_entries[0].uuid = cel_uuid; 213 supported_logs->log_entries[0].size = 4 * cxl_dstate->cel_size; 214 215 *len = sizeof(*supported_logs); 216 return CXL_MBOX_SUCCESS; 217 } 218 219 /* 8.2.9.4.2 */ 220 static CXLRetCode cmd_logs_get_log(struct cxl_cmd *cmd, 221 CXLDeviceState *cxl_dstate, 222 uint16_t *len) 223 { 224 struct { 225 QemuUUID uuid; 226 uint32_t offset; 227 uint32_t length; 228 } QEMU_PACKED QEMU_ALIGNED(16) *get_log = (void *)cmd->payload; 229 230 /* 231 * 8.2.9.4.2 232 * The device shall return Invalid Parameter if the Offset or Length 233 * fields attempt to access beyond the size of the log as reported by Get 234 * Supported Logs. 235 * 236 * XXX: Spec is wrong, "Invalid Parameter" isn't a thing. 237 * XXX: Spec doesn't address incorrect UUID incorrectness. 238 * 239 * The CEL buffer is large enough to fit all commands in the emulation, so 240 * the only possible failure would be if the mailbox itself isn't big 241 * enough. 242 */ 243 if (get_log->offset + get_log->length > cxl_dstate->payload_size) { 244 return CXL_MBOX_INVALID_INPUT; 245 } 246 247 if (!qemu_uuid_is_equal(&get_log->uuid, &cel_uuid)) { 248 return CXL_MBOX_UNSUPPORTED; 249 } 250 251 /* Store off everything to local variables so we can wipe out the payload */ 252 *len = get_log->length; 253 254 memmove(cmd->payload, cxl_dstate->cel_log + get_log->offset, 255 get_log->length); 256 257 return CXL_MBOX_SUCCESS; 258 } 259 260 /* 8.2.9.5.1.1 */ 261 static CXLRetCode cmd_identify_memory_device(struct cxl_cmd *cmd, 262 CXLDeviceState *cxl_dstate, 263 uint16_t *len) 264 { 265 struct { 266 char fw_revision[0x10]; 267 uint64_t total_capacity; 268 uint64_t volatile_capacity; 269 uint64_t persistent_capacity; 270 uint64_t partition_align; 271 uint16_t info_event_log_size; 272 uint16_t warning_event_log_size; 273 uint16_t failure_event_log_size; 274 uint16_t fatal_event_log_size; 275 uint32_t lsa_size; 276 uint8_t poison_list_max_mer[3]; 277 uint16_t inject_poison_limit; 278 uint8_t poison_caps; 279 uint8_t qos_telemetry_caps; 280 } QEMU_PACKED *id; 281 QEMU_BUILD_BUG_ON(sizeof(*id) != 0x43); 282 283 CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate); 284 CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d); 285 286 if ((!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, CXL_CAPACITY_MULTIPLIER)) || 287 (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))) { 288 return CXL_MBOX_INTERNAL_ERROR; 289 } 290 291 id = (void *)cmd->payload; 292 memset(id, 0, sizeof(*id)); 293 294 snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0); 295 296 stq_le_p(&id->total_capacity, cxl_dstate->mem_size / CXL_CAPACITY_MULTIPLIER); 297 stq_le_p(&id->persistent_capacity, cxl_dstate->pmem_size / CXL_CAPACITY_MULTIPLIER); 298 stq_le_p(&id->volatile_capacity, cxl_dstate->vmem_size / CXL_CAPACITY_MULTIPLIER); 299 stl_le_p(&id->lsa_size, cvc->get_lsa_size(ct3d)); 300 /* 256 poison records */ 301 st24_le_p(id->poison_list_max_mer, 256); 302 /* No limit - so limited by main poison record limit */ 303 stw_le_p(&id->inject_poison_limit, 0); 304 305 *len = sizeof(*id); 306 return CXL_MBOX_SUCCESS; 307 } 308 309 static CXLRetCode cmd_ccls_get_partition_info(struct cxl_cmd *cmd, 310 CXLDeviceState *cxl_dstate, 311 uint16_t *len) 312 { 313 struct { 314 uint64_t active_vmem; 315 uint64_t active_pmem; 316 uint64_t next_vmem; 317 uint64_t next_pmem; 318 } QEMU_PACKED *part_info = (void *)cmd->payload; 319 QEMU_BUILD_BUG_ON(sizeof(*part_info) != 0x20); 320 321 if ((!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, CXL_CAPACITY_MULTIPLIER)) || 322 (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))) { 323 return CXL_MBOX_INTERNAL_ERROR; 324 } 325 326 stq_le_p(&part_info->active_vmem, cxl_dstate->vmem_size / CXL_CAPACITY_MULTIPLIER); 327 /* 328 * When both next_vmem and next_pmem are 0, there is no pending change to 329 * partitioning. 330 */ 331 stq_le_p(&part_info->next_vmem, 0); 332 stq_le_p(&part_info->active_pmem, cxl_dstate->pmem_size / CXL_CAPACITY_MULTIPLIER); 333 stq_le_p(&part_info->next_pmem, 0); 334 335 *len = sizeof(*part_info); 336 return CXL_MBOX_SUCCESS; 337 } 338 339 static CXLRetCode cmd_ccls_get_lsa(struct cxl_cmd *cmd, 340 CXLDeviceState *cxl_dstate, 341 uint16_t *len) 342 { 343 struct { 344 uint32_t offset; 345 uint32_t length; 346 } QEMU_PACKED *get_lsa; 347 CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate); 348 CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d); 349 uint32_t offset, length; 350 351 get_lsa = (void *)cmd->payload; 352 offset = get_lsa->offset; 353 length = get_lsa->length; 354 355 if (offset + length > cvc->get_lsa_size(ct3d)) { 356 *len = 0; 357 return CXL_MBOX_INVALID_INPUT; 358 } 359 360 *len = cvc->get_lsa(ct3d, get_lsa, length, offset); 361 return CXL_MBOX_SUCCESS; 362 } 363 364 static CXLRetCode cmd_ccls_set_lsa(struct cxl_cmd *cmd, 365 CXLDeviceState *cxl_dstate, 366 uint16_t *len) 367 { 368 struct set_lsa_pl { 369 uint32_t offset; 370 uint32_t rsvd; 371 uint8_t data[]; 372 } QEMU_PACKED; 373 struct set_lsa_pl *set_lsa_payload = (void *)cmd->payload; 374 CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate); 375 CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d); 376 const size_t hdr_len = offsetof(struct set_lsa_pl, data); 377 uint16_t plen = *len; 378 379 *len = 0; 380 if (!plen) { 381 return CXL_MBOX_SUCCESS; 382 } 383 384 if (set_lsa_payload->offset + plen > cvc->get_lsa_size(ct3d) + hdr_len) { 385 return CXL_MBOX_INVALID_INPUT; 386 } 387 plen -= hdr_len; 388 389 cvc->set_lsa(ct3d, set_lsa_payload->data, plen, set_lsa_payload->offset); 390 return CXL_MBOX_SUCCESS; 391 } 392 393 /* 394 * This is very inefficient, but good enough for now! 395 * Also the payload will always fit, so no need to handle the MORE flag and 396 * make this stateful. We may want to allow longer poison lists to aid 397 * testing that kernel functionality. 398 */ 399 static CXLRetCode cmd_media_get_poison_list(struct cxl_cmd *cmd, 400 CXLDeviceState *cxl_dstate, 401 uint16_t *len) 402 { 403 struct get_poison_list_pl { 404 uint64_t pa; 405 uint64_t length; 406 } QEMU_PACKED; 407 408 struct get_poison_list_out_pl { 409 uint8_t flags; 410 uint8_t rsvd1; 411 uint64_t overflow_timestamp; 412 uint16_t count; 413 uint8_t rsvd2[0x14]; 414 struct { 415 uint64_t addr; 416 uint32_t length; 417 uint32_t resv; 418 } QEMU_PACKED records[]; 419 } QEMU_PACKED; 420 421 struct get_poison_list_pl *in = (void *)cmd->payload; 422 struct get_poison_list_out_pl *out = (void *)cmd->payload; 423 CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate); 424 uint16_t record_count = 0, i = 0; 425 uint64_t query_start, query_length; 426 CXLPoisonList *poison_list = &ct3d->poison_list; 427 CXLPoison *ent; 428 uint16_t out_pl_len; 429 430 query_start = ldq_le_p(&in->pa); 431 /* 64 byte alignemnt required */ 432 if (query_start & 0x3f) { 433 return CXL_MBOX_INVALID_INPUT; 434 } 435 query_length = ldq_le_p(&in->length) * CXL_CACHE_LINE_SIZE; 436 437 QLIST_FOREACH(ent, poison_list, node) { 438 /* Check for no overlap */ 439 if (ent->start >= query_start + query_length || 440 ent->start + ent->length <= query_start) { 441 continue; 442 } 443 record_count++; 444 } 445 out_pl_len = sizeof(*out) + record_count * sizeof(out->records[0]); 446 assert(out_pl_len <= CXL_MAILBOX_MAX_PAYLOAD_SIZE); 447 448 memset(out, 0, out_pl_len); 449 QLIST_FOREACH(ent, poison_list, node) { 450 uint64_t start, stop; 451 452 /* Check for no overlap */ 453 if (ent->start >= query_start + query_length || 454 ent->start + ent->length <= query_start) { 455 continue; 456 } 457 458 /* Deal with overlap */ 459 start = MAX(ROUND_DOWN(ent->start, 64ull), query_start); 460 stop = MIN(ROUND_DOWN(ent->start, 64ull) + ent->length, 461 query_start + query_length); 462 stq_le_p(&out->records[i].addr, start | (ent->type & 0x7)); 463 stl_le_p(&out->records[i].length, (stop - start) / CXL_CACHE_LINE_SIZE); 464 i++; 465 } 466 if (ct3d->poison_list_overflowed) { 467 out->flags = (1 << 1); 468 stq_le_p(&out->overflow_timestamp, ct3d->poison_list_overflow_ts); 469 } 470 stw_le_p(&out->count, record_count); 471 *len = out_pl_len; 472 return CXL_MBOX_SUCCESS; 473 } 474 475 #define IMMEDIATE_CONFIG_CHANGE (1 << 1) 476 #define IMMEDIATE_DATA_CHANGE (1 << 2) 477 #define IMMEDIATE_POLICY_CHANGE (1 << 3) 478 #define IMMEDIATE_LOG_CHANGE (1 << 4) 479 480 static struct cxl_cmd cxl_cmd_set[256][256] = { 481 [EVENTS][GET_RECORDS] = { "EVENTS_GET_RECORDS", 482 cmd_events_get_records, 1, 0 }, 483 [EVENTS][CLEAR_RECORDS] = { "EVENTS_CLEAR_RECORDS", 484 cmd_events_clear_records, ~0, IMMEDIATE_LOG_CHANGE }, 485 [EVENTS][GET_INTERRUPT_POLICY] = { "EVENTS_GET_INTERRUPT_POLICY", 486 cmd_events_get_interrupt_policy, 0, 0 }, 487 [EVENTS][SET_INTERRUPT_POLICY] = { "EVENTS_SET_INTERRUPT_POLICY", 488 cmd_events_set_interrupt_policy, 4, IMMEDIATE_CONFIG_CHANGE }, 489 [FIRMWARE_UPDATE][GET_INFO] = { "FIRMWARE_UPDATE_GET_INFO", 490 cmd_firmware_update_get_info, 0, 0 }, 491 [TIMESTAMP][GET] = { "TIMESTAMP_GET", cmd_timestamp_get, 0, 0 }, 492 [TIMESTAMP][SET] = { "TIMESTAMP_SET", cmd_timestamp_set, 8, IMMEDIATE_POLICY_CHANGE }, 493 [LOGS][GET_SUPPORTED] = { "LOGS_GET_SUPPORTED", cmd_logs_get_supported, 0, 0 }, 494 [LOGS][GET_LOG] = { "LOGS_GET_LOG", cmd_logs_get_log, 0x18, 0 }, 495 [IDENTIFY][MEMORY_DEVICE] = { "IDENTIFY_MEMORY_DEVICE", 496 cmd_identify_memory_device, 0, 0 }, 497 [CCLS][GET_PARTITION_INFO] = { "CCLS_GET_PARTITION_INFO", 498 cmd_ccls_get_partition_info, 0, 0 }, 499 [CCLS][GET_LSA] = { "CCLS_GET_LSA", cmd_ccls_get_lsa, 8, 0 }, 500 [CCLS][SET_LSA] = { "CCLS_SET_LSA", cmd_ccls_set_lsa, 501 ~0, IMMEDIATE_CONFIG_CHANGE | IMMEDIATE_DATA_CHANGE }, 502 [MEDIA_AND_POISON][GET_POISON_LIST] = { "MEDIA_AND_POISON_GET_POISON_LIST", 503 cmd_media_get_poison_list, 16, 0 }, 504 }; 505 506 void cxl_process_mailbox(CXLDeviceState *cxl_dstate) 507 { 508 uint16_t ret = CXL_MBOX_SUCCESS; 509 struct cxl_cmd *cxl_cmd; 510 uint64_t status_reg; 511 opcode_handler h; 512 uint64_t command_reg = cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_CMD]; 513 514 uint8_t set = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_SET); 515 uint8_t cmd = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND); 516 uint16_t len = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH); 517 cxl_cmd = &cxl_cmd_set[set][cmd]; 518 h = cxl_cmd->handler; 519 if (h) { 520 if (len == cxl_cmd->in || cxl_cmd->in == ~0) { 521 cxl_cmd->payload = cxl_dstate->mbox_reg_state + 522 A_CXL_DEV_CMD_PAYLOAD; 523 ret = (*h)(cxl_cmd, cxl_dstate, &len); 524 assert(len <= cxl_dstate->payload_size); 525 } else { 526 ret = CXL_MBOX_INVALID_PAYLOAD_LENGTH; 527 } 528 } else { 529 qemu_log_mask(LOG_UNIMP, "Command %04xh not implemented\n", 530 set << 8 | cmd); 531 ret = CXL_MBOX_UNSUPPORTED; 532 } 533 534 /* Set the return code */ 535 status_reg = FIELD_DP64(0, CXL_DEV_MAILBOX_STS, ERRNO, ret); 536 537 /* Set the return length */ 538 command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_SET, 0); 539 command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND, 0); 540 command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH, len); 541 542 cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_CMD] = command_reg; 543 cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_STS] = status_reg; 544 545 /* Tell the host we're done */ 546 ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL, 547 DOORBELL, 0); 548 } 549 550 void cxl_initialize_mailbox(CXLDeviceState *cxl_dstate) 551 { 552 for (int set = 0; set < 256; set++) { 553 for (int cmd = 0; cmd < 256; cmd++) { 554 if (cxl_cmd_set[set][cmd].handler) { 555 struct cxl_cmd *c = &cxl_cmd_set[set][cmd]; 556 struct cel_log *log = 557 &cxl_dstate->cel_log[cxl_dstate->cel_size]; 558 559 log->opcode = (set << 8) | cmd; 560 log->effect = c->effect; 561 cxl_dstate->cel_size++; 562 } 563 } 564 } 565 } 566