xref: /openbmc/qemu/hw/cxl/cxl-mailbox-utils.c (revision 1141159c)
1 /*
2  * CXL Utility library for mailbox interface
3  *
4  * Copyright(C) 2020 Intel Corporation.
5  *
6  * This work is licensed under the terms of the GNU GPL, version 2. See the
7  * COPYING file in the top-level directory.
8  */
9 
10 #include "qemu/osdep.h"
11 #include "hw/cxl/cxl.h"
12 #include "hw/pci/pci.h"
13 #include "qemu/cutils.h"
14 #include "qemu/log.h"
15 #include "qemu/units.h"
16 #include "qemu/uuid.h"
17 
18 #define CXL_CAPACITY_MULTIPLIER   (256 * MiB)
19 
20 /*
21  * How to add a new command, example. The command set FOO, with cmd BAR.
22  *  1. Add the command set and cmd to the enum.
23  *     FOO    = 0x7f,
24  *          #define BAR 0
25  *  2. Implement the handler
26  *    static ret_code cmd_foo_bar(struct cxl_cmd *cmd,
27  *                                  CXLDeviceState *cxl_dstate, uint16_t *len)
28  *  3. Add the command to the cxl_cmd_set[][]
29  *    [FOO][BAR] = { "FOO_BAR", cmd_foo_bar, x, y },
30  *  4. Implement your handler
31  *     define_mailbox_handler(FOO_BAR) { ... return CXL_MBOX_SUCCESS; }
32  *
33  *
34  *  Writing the handler:
35  *    The handler will provide the &struct cxl_cmd, the &CXLDeviceState, and the
36  *    in/out length of the payload. The handler is responsible for consuming the
37  *    payload from cmd->payload and operating upon it as necessary. It must then
38  *    fill the output data into cmd->payload (overwriting what was there),
39  *    setting the length, and returning a valid return code.
40  *
41  *  XXX: The handler need not worry about endianess. The payload is read out of
42  *  a register interface that already deals with it.
43  */
44 
45 enum {
46     EVENTS      = 0x01,
47         #define GET_RECORDS   0x0
48         #define CLEAR_RECORDS   0x1
49         #define GET_INTERRUPT_POLICY   0x2
50         #define SET_INTERRUPT_POLICY   0x3
51     FIRMWARE_UPDATE = 0x02,
52         #define GET_INFO      0x0
53     TIMESTAMP   = 0x03,
54         #define GET           0x0
55         #define SET           0x1
56     LOGS        = 0x04,
57         #define GET_SUPPORTED 0x0
58         #define GET_LOG       0x1
59     IDENTIFY    = 0x40,
60         #define MEMORY_DEVICE 0x0
61     CCLS        = 0x41,
62         #define GET_PARTITION_INFO     0x0
63         #define GET_LSA       0x2
64         #define SET_LSA       0x3
65 };
66 
67 /* 8.2.8.4.5.1 Command Return Codes */
68 typedef enum {
69     CXL_MBOX_SUCCESS = 0x0,
70     CXL_MBOX_BG_STARTED = 0x1,
71     CXL_MBOX_INVALID_INPUT = 0x2,
72     CXL_MBOX_UNSUPPORTED = 0x3,
73     CXL_MBOX_INTERNAL_ERROR = 0x4,
74     CXL_MBOX_RETRY_REQUIRED = 0x5,
75     CXL_MBOX_BUSY = 0x6,
76     CXL_MBOX_MEDIA_DISABLED = 0x7,
77     CXL_MBOX_FW_XFER_IN_PROGRESS = 0x8,
78     CXL_MBOX_FW_XFER_OUT_OF_ORDER = 0x9,
79     CXL_MBOX_FW_AUTH_FAILED = 0xa,
80     CXL_MBOX_FW_INVALID_SLOT = 0xb,
81     CXL_MBOX_FW_ROLLEDBACK = 0xc,
82     CXL_MBOX_FW_REST_REQD = 0xd,
83     CXL_MBOX_INVALID_HANDLE = 0xe,
84     CXL_MBOX_INVALID_PA = 0xf,
85     CXL_MBOX_INJECT_POISON_LIMIT = 0x10,
86     CXL_MBOX_PERMANENT_MEDIA_FAILURE = 0x11,
87     CXL_MBOX_ABORTED = 0x12,
88     CXL_MBOX_INVALID_SECURITY_STATE = 0x13,
89     CXL_MBOX_INCORRECT_PASSPHRASE = 0x14,
90     CXL_MBOX_UNSUPPORTED_MAILBOX = 0x15,
91     CXL_MBOX_INVALID_PAYLOAD_LENGTH = 0x16,
92     CXL_MBOX_MAX = 0x17
93 } ret_code;
94 
95 struct cxl_cmd;
96 typedef ret_code (*opcode_handler)(struct cxl_cmd *cmd,
97                                    CXLDeviceState *cxl_dstate, uint16_t *len);
98 struct cxl_cmd {
99     const char *name;
100     opcode_handler handler;
101     ssize_t in;
102     uint16_t effect; /* Reported in CEL */
103     uint8_t *payload;
104 };
105 
106 #define DEFINE_MAILBOX_HANDLER_ZEROED(name, size)                         \
107     uint16_t __zero##name = size;                                         \
108     static ret_code cmd_##name(struct cxl_cmd *cmd,                       \
109                                CXLDeviceState *cxl_dstate, uint16_t *len) \
110     {                                                                     \
111         *len = __zero##name;                                              \
112         memset(cmd->payload, 0, *len);                                    \
113         return CXL_MBOX_SUCCESS;                                          \
114     }
115 #define DEFINE_MAILBOX_HANDLER_NOP(name)                                  \
116     static ret_code cmd_##name(struct cxl_cmd *cmd,                       \
117                                CXLDeviceState *cxl_dstate, uint16_t *len) \
118     {                                                                     \
119         return CXL_MBOX_SUCCESS;                                          \
120     }
121 
122 DEFINE_MAILBOX_HANDLER_ZEROED(events_get_records, 0x20);
123 DEFINE_MAILBOX_HANDLER_NOP(events_clear_records);
124 DEFINE_MAILBOX_HANDLER_ZEROED(events_get_interrupt_policy, 4);
125 DEFINE_MAILBOX_HANDLER_NOP(events_set_interrupt_policy);
126 
127 /* 8.2.9.2.1 */
128 static ret_code cmd_firmware_update_get_info(struct cxl_cmd *cmd,
129                                              CXLDeviceState *cxl_dstate,
130                                              uint16_t *len)
131 {
132     struct {
133         uint8_t slots_supported;
134         uint8_t slot_info;
135         uint8_t caps;
136         uint8_t rsvd[0xd];
137         char fw_rev1[0x10];
138         char fw_rev2[0x10];
139         char fw_rev3[0x10];
140         char fw_rev4[0x10];
141     } QEMU_PACKED *fw_info;
142     QEMU_BUILD_BUG_ON(sizeof(*fw_info) != 0x50);
143 
144     if ((cxl_dstate->vmem_size < CXL_CAPACITY_MULTIPLIER) ||
145         (cxl_dstate->pmem_size < CXL_CAPACITY_MULTIPLIER)) {
146         return CXL_MBOX_INTERNAL_ERROR;
147     }
148 
149     fw_info = (void *)cmd->payload;
150     memset(fw_info, 0, sizeof(*fw_info));
151 
152     fw_info->slots_supported = 2;
153     fw_info->slot_info = BIT(0) | BIT(3);
154     fw_info->caps = 0;
155     pstrcpy(fw_info->fw_rev1, sizeof(fw_info->fw_rev1), "BWFW VERSION 0");
156 
157     *len = sizeof(*fw_info);
158     return CXL_MBOX_SUCCESS;
159 }
160 
161 /* 8.2.9.3.1 */
162 static ret_code cmd_timestamp_get(struct cxl_cmd *cmd,
163                                   CXLDeviceState *cxl_dstate,
164                                   uint16_t *len)
165 {
166     uint64_t time, delta;
167     uint64_t final_time = 0;
168 
169     if (cxl_dstate->timestamp.set) {
170         /* First find the delta from the last time the host set the time. */
171         time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
172         delta = time - cxl_dstate->timestamp.last_set;
173         final_time = cxl_dstate->timestamp.host_set + delta;
174     }
175 
176     /* Then adjust the actual time */
177     stq_le_p(cmd->payload, final_time);
178     *len = 8;
179 
180     return CXL_MBOX_SUCCESS;
181 }
182 
183 /* 8.2.9.3.2 */
184 static ret_code cmd_timestamp_set(struct cxl_cmd *cmd,
185                                   CXLDeviceState *cxl_dstate,
186                                   uint16_t *len)
187 {
188     cxl_dstate->timestamp.set = true;
189     cxl_dstate->timestamp.last_set = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
190 
191     cxl_dstate->timestamp.host_set = le64_to_cpu(*(uint64_t *)cmd->payload);
192 
193     *len = 0;
194     return CXL_MBOX_SUCCESS;
195 }
196 
197 /* CXL 3.0 8.2.9.5.2.1 Command Effects Log (CEL) */
198 static const QemuUUID cel_uuid = {
199     .data = UUID(0x0da9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79,
200                  0x96, 0xb1, 0x62, 0x3b, 0x3f, 0x17)
201 };
202 
203 /* 8.2.9.4.1 */
204 static ret_code cmd_logs_get_supported(struct cxl_cmd *cmd,
205                                        CXLDeviceState *cxl_dstate,
206                                        uint16_t *len)
207 {
208     struct {
209         uint16_t entries;
210         uint8_t rsvd[6];
211         struct {
212             QemuUUID uuid;
213             uint32_t size;
214         } log_entries[1];
215     } QEMU_PACKED *supported_logs = (void *)cmd->payload;
216     QEMU_BUILD_BUG_ON(sizeof(*supported_logs) != 0x1c);
217 
218     supported_logs->entries = 1;
219     supported_logs->log_entries[0].uuid = cel_uuid;
220     supported_logs->log_entries[0].size = 4 * cxl_dstate->cel_size;
221 
222     *len = sizeof(*supported_logs);
223     return CXL_MBOX_SUCCESS;
224 }
225 
226 /* 8.2.9.4.2 */
227 static ret_code cmd_logs_get_log(struct cxl_cmd *cmd,
228                                  CXLDeviceState *cxl_dstate,
229                                  uint16_t *len)
230 {
231     struct {
232         QemuUUID uuid;
233         uint32_t offset;
234         uint32_t length;
235     } QEMU_PACKED QEMU_ALIGNED(16) *get_log = (void *)cmd->payload;
236 
237     /*
238      * 8.2.9.4.2
239      *   The device shall return Invalid Parameter if the Offset or Length
240      *   fields attempt to access beyond the size of the log as reported by Get
241      *   Supported Logs.
242      *
243      * XXX: Spec is wrong, "Invalid Parameter" isn't a thing.
244      * XXX: Spec doesn't address incorrect UUID incorrectness.
245      *
246      * The CEL buffer is large enough to fit all commands in the emulation, so
247      * the only possible failure would be if the mailbox itself isn't big
248      * enough.
249      */
250     if (get_log->offset + get_log->length > cxl_dstate->payload_size) {
251         return CXL_MBOX_INVALID_INPUT;
252     }
253 
254     if (!qemu_uuid_is_equal(&get_log->uuid, &cel_uuid)) {
255         return CXL_MBOX_UNSUPPORTED;
256     }
257 
258     /* Store off everything to local variables so we can wipe out the payload */
259     *len = get_log->length;
260 
261     memmove(cmd->payload, cxl_dstate->cel_log + get_log->offset,
262            get_log->length);
263 
264     return CXL_MBOX_SUCCESS;
265 }
266 
267 /* 8.2.9.5.1.1 */
268 static ret_code cmd_identify_memory_device(struct cxl_cmd *cmd,
269                                            CXLDeviceState *cxl_dstate,
270                                            uint16_t *len)
271 {
272     struct {
273         char fw_revision[0x10];
274         uint64_t total_capacity;
275         uint64_t volatile_capacity;
276         uint64_t persistent_capacity;
277         uint64_t partition_align;
278         uint16_t info_event_log_size;
279         uint16_t warning_event_log_size;
280         uint16_t failure_event_log_size;
281         uint16_t fatal_event_log_size;
282         uint32_t lsa_size;
283         uint8_t poison_list_max_mer[3];
284         uint16_t inject_poison_limit;
285         uint8_t poison_caps;
286         uint8_t qos_telemetry_caps;
287     } QEMU_PACKED *id;
288     QEMU_BUILD_BUG_ON(sizeof(*id) != 0x43);
289 
290     CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
291     CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d);
292 
293     if ((!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, CXL_CAPACITY_MULTIPLIER)) ||
294         (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))) {
295         return CXL_MBOX_INTERNAL_ERROR;
296     }
297 
298     id = (void *)cmd->payload;
299     memset(id, 0, sizeof(*id));
300 
301     snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0);
302 
303     stq_le_p(&id->total_capacity, cxl_dstate->mem_size / CXL_CAPACITY_MULTIPLIER);
304     stq_le_p(&id->persistent_capacity, cxl_dstate->pmem_size / CXL_CAPACITY_MULTIPLIER);
305     stq_le_p(&id->volatile_capacity, cxl_dstate->vmem_size / CXL_CAPACITY_MULTIPLIER);
306     stl_le_p(&id->lsa_size, cvc->get_lsa_size(ct3d));
307 
308     *len = sizeof(*id);
309     return CXL_MBOX_SUCCESS;
310 }
311 
312 static ret_code cmd_ccls_get_partition_info(struct cxl_cmd *cmd,
313                                            CXLDeviceState *cxl_dstate,
314                                            uint16_t *len)
315 {
316     struct {
317         uint64_t active_vmem;
318         uint64_t active_pmem;
319         uint64_t next_vmem;
320         uint64_t next_pmem;
321     } QEMU_PACKED *part_info = (void *)cmd->payload;
322     QEMU_BUILD_BUG_ON(sizeof(*part_info) != 0x20);
323 
324     if ((!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, CXL_CAPACITY_MULTIPLIER)) ||
325         (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))) {
326         return CXL_MBOX_INTERNAL_ERROR;
327     }
328 
329     stq_le_p(&part_info->active_vmem, cxl_dstate->vmem_size / CXL_CAPACITY_MULTIPLIER);
330     /*
331      * When both next_vmem and next_pmem are 0, there is no pending change to
332      * partitioning.
333      */
334     stq_le_p(&part_info->next_vmem, 0);
335     stq_le_p(&part_info->active_pmem, cxl_dstate->pmem_size / CXL_CAPACITY_MULTIPLIER);
336     stq_le_p(&part_info->next_pmem, 0);
337 
338     *len = sizeof(*part_info);
339     return CXL_MBOX_SUCCESS;
340 }
341 
342 static ret_code cmd_ccls_get_lsa(struct cxl_cmd *cmd,
343                                  CXLDeviceState *cxl_dstate,
344                                  uint16_t *len)
345 {
346     struct {
347         uint32_t offset;
348         uint32_t length;
349     } QEMU_PACKED *get_lsa;
350     CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
351     CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d);
352     uint32_t offset, length;
353 
354     get_lsa = (void *)cmd->payload;
355     offset = get_lsa->offset;
356     length = get_lsa->length;
357 
358     if (offset + length > cvc->get_lsa_size(ct3d)) {
359         *len = 0;
360         return CXL_MBOX_INVALID_INPUT;
361     }
362 
363     *len = cvc->get_lsa(ct3d, get_lsa, length, offset);
364     return CXL_MBOX_SUCCESS;
365 }
366 
367 static ret_code cmd_ccls_set_lsa(struct cxl_cmd *cmd,
368                                  CXLDeviceState *cxl_dstate,
369                                  uint16_t *len)
370 {
371     struct set_lsa_pl {
372         uint32_t offset;
373         uint32_t rsvd;
374         uint8_t data[];
375     } QEMU_PACKED;
376     struct set_lsa_pl *set_lsa_payload = (void *)cmd->payload;
377     CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
378     CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d);
379     const size_t hdr_len = offsetof(struct set_lsa_pl, data);
380     uint16_t plen = *len;
381 
382     *len = 0;
383     if (!plen) {
384         return CXL_MBOX_SUCCESS;
385     }
386 
387     if (set_lsa_payload->offset + plen > cvc->get_lsa_size(ct3d) + hdr_len) {
388         return CXL_MBOX_INVALID_INPUT;
389     }
390     plen -= hdr_len;
391 
392     cvc->set_lsa(ct3d, set_lsa_payload->data, plen, set_lsa_payload->offset);
393     return CXL_MBOX_SUCCESS;
394 }
395 
396 #define IMMEDIATE_CONFIG_CHANGE (1 << 1)
397 #define IMMEDIATE_DATA_CHANGE (1 << 2)
398 #define IMMEDIATE_POLICY_CHANGE (1 << 3)
399 #define IMMEDIATE_LOG_CHANGE (1 << 4)
400 
401 static struct cxl_cmd cxl_cmd_set[256][256] = {
402     [EVENTS][GET_RECORDS] = { "EVENTS_GET_RECORDS",
403         cmd_events_get_records, 1, 0 },
404     [EVENTS][CLEAR_RECORDS] = { "EVENTS_CLEAR_RECORDS",
405         cmd_events_clear_records, ~0, IMMEDIATE_LOG_CHANGE },
406     [EVENTS][GET_INTERRUPT_POLICY] = { "EVENTS_GET_INTERRUPT_POLICY",
407         cmd_events_get_interrupt_policy, 0, 0 },
408     [EVENTS][SET_INTERRUPT_POLICY] = { "EVENTS_SET_INTERRUPT_POLICY",
409         cmd_events_set_interrupt_policy, 4, IMMEDIATE_CONFIG_CHANGE },
410     [FIRMWARE_UPDATE][GET_INFO] = { "FIRMWARE_UPDATE_GET_INFO",
411         cmd_firmware_update_get_info, 0, 0 },
412     [TIMESTAMP][GET] = { "TIMESTAMP_GET", cmd_timestamp_get, 0, 0 },
413     [TIMESTAMP][SET] = { "TIMESTAMP_SET", cmd_timestamp_set, 8, IMMEDIATE_POLICY_CHANGE },
414     [LOGS][GET_SUPPORTED] = { "LOGS_GET_SUPPORTED", cmd_logs_get_supported, 0, 0 },
415     [LOGS][GET_LOG] = { "LOGS_GET_LOG", cmd_logs_get_log, 0x18, 0 },
416     [IDENTIFY][MEMORY_DEVICE] = { "IDENTIFY_MEMORY_DEVICE",
417         cmd_identify_memory_device, 0, 0 },
418     [CCLS][GET_PARTITION_INFO] = { "CCLS_GET_PARTITION_INFO",
419         cmd_ccls_get_partition_info, 0, 0 },
420     [CCLS][GET_LSA] = { "CCLS_GET_LSA", cmd_ccls_get_lsa, 8, 0 },
421     [CCLS][SET_LSA] = { "CCLS_SET_LSA", cmd_ccls_set_lsa,
422         ~0, IMMEDIATE_CONFIG_CHANGE | IMMEDIATE_DATA_CHANGE },
423 };
424 
425 void cxl_process_mailbox(CXLDeviceState *cxl_dstate)
426 {
427     uint16_t ret = CXL_MBOX_SUCCESS;
428     struct cxl_cmd *cxl_cmd;
429     uint64_t status_reg;
430     opcode_handler h;
431     uint64_t command_reg = cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_CMD];
432 
433     uint8_t set = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_SET);
434     uint8_t cmd = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND);
435     uint16_t len = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH);
436     cxl_cmd = &cxl_cmd_set[set][cmd];
437     h = cxl_cmd->handler;
438     if (h) {
439         if (len == cxl_cmd->in || cxl_cmd->in == ~0) {
440             cxl_cmd->payload = cxl_dstate->mbox_reg_state +
441                 A_CXL_DEV_CMD_PAYLOAD;
442             ret = (*h)(cxl_cmd, cxl_dstate, &len);
443             assert(len <= cxl_dstate->payload_size);
444         } else {
445             ret = CXL_MBOX_INVALID_PAYLOAD_LENGTH;
446         }
447     } else {
448         qemu_log_mask(LOG_UNIMP, "Command %04xh not implemented\n",
449                       set << 8 | cmd);
450         ret = CXL_MBOX_UNSUPPORTED;
451     }
452 
453     /* Set the return code */
454     status_reg = FIELD_DP64(0, CXL_DEV_MAILBOX_STS, ERRNO, ret);
455 
456     /* Set the return length */
457     command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_SET, 0);
458     command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND, 0);
459     command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH, len);
460 
461     cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_CMD] = command_reg;
462     cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_STS] = status_reg;
463 
464     /* Tell the host we're done */
465     ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL,
466                      DOORBELL, 0);
467 }
468 
469 void cxl_initialize_mailbox(CXLDeviceState *cxl_dstate)
470 {
471     for (int set = 0; set < 256; set++) {
472         for (int cmd = 0; cmd < 256; cmd++) {
473             if (cxl_cmd_set[set][cmd].handler) {
474                 struct cxl_cmd *c = &cxl_cmd_set[set][cmd];
475                 struct cel_log *log =
476                     &cxl_dstate->cel_log[cxl_dstate->cel_size];
477 
478                 log->opcode = (set << 8) | cmd;
479                 log->effect = c->effect;
480                 cxl_dstate->cel_size++;
481             }
482         }
483     }
484 }
485