1 /* 2 * CXL host parameter parsing routines 3 * 4 * Copyright (c) 2022 Huawei 5 * Modeled loosely on the NUMA options handling in hw/core/numa.c 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/units.h" 10 #include "qemu/bitmap.h" 11 #include "qemu/error-report.h" 12 #include "qapi/error.h" 13 #include "sysemu/qtest.h" 14 #include "hw/boards.h" 15 16 #include "qapi/qapi-visit-machine.h" 17 #include "hw/cxl/cxl.h" 18 #include "hw/cxl/cxl_host.h" 19 #include "hw/pci/pci_bus.h" 20 #include "hw/pci/pci_bridge.h" 21 #include "hw/pci/pci_host.h" 22 #include "hw/pci/pcie_port.h" 23 #include "hw/pci-bridge/pci_expander_bridge.h" 24 25 static void cxl_fixed_memory_window_config(CXLState *cxl_state, 26 CXLFixedMemoryWindowOptions *object, 27 Error **errp) 28 { 29 g_autofree CXLFixedWindow *fw = g_malloc0(sizeof(*fw)); 30 strList *target; 31 int i; 32 33 for (target = object->targets; target; target = target->next) { 34 fw->num_targets++; 35 } 36 37 fw->enc_int_ways = cxl_interleave_ways_enc(fw->num_targets, errp); 38 if (*errp) { 39 return; 40 } 41 42 if (object->size % (256 * MiB)) { 43 error_setg(errp, 44 "Size of a CXL fixed memory window must be a multiple of 256MiB"); 45 return; 46 } 47 fw->size = object->size; 48 49 if (object->has_interleave_granularity) { 50 fw->enc_int_gran = 51 cxl_interleave_granularity_enc(object->interleave_granularity, 52 errp); 53 if (*errp) { 54 return; 55 } 56 } else { 57 /* Default to 256 byte interleave */ 58 fw->enc_int_gran = 0; 59 } 60 61 fw->targets = g_malloc0_n(fw->num_targets, sizeof(*fw->targets)); 62 for (i = 0, target = object->targets; target; i++, target = target->next) { 63 /* This link cannot be resolved yet, so stash the name for now */ 64 fw->targets[i] = g_strdup(target->value); 65 } 66 67 cxl_state->fixed_windows = g_list_append(cxl_state->fixed_windows, 68 g_steal_pointer(&fw)); 69 70 return; 71 } 72 73 void cxl_fmws_link_targets(CXLState *cxl_state, Error **errp) 74 { 75 if (cxl_state && cxl_state->fixed_windows) { 76 GList *it; 77 78 for (it = cxl_state->fixed_windows; it; it = it->next) { 79 CXLFixedWindow *fw = it->data; 80 int i; 81 82 for (i = 0; i < fw->num_targets; i++) { 83 Object *o; 84 bool ambig; 85 86 o = object_resolve_path_type(fw->targets[i], 87 TYPE_PXB_CXL_DEV, 88 &ambig); 89 if (!o) { 90 error_setg(errp, "Could not resolve CXLFM target %s", 91 fw->targets[i]); 92 return; 93 } 94 fw->target_hbs[i] = PXB_CXL_DEV(o); 95 } 96 } 97 } 98 } 99 100 static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr, 101 uint8_t *target) 102 { 103 int hdm_inc = R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_LO; 104 unsigned int hdm_count; 105 bool found = false; 106 int i; 107 uint32_t cap; 108 109 cap = ldl_le_p(cache_mem + R_CXL_HDM_DECODER_CAPABILITY); 110 hdm_count = cxl_decoder_count_dec(FIELD_EX32(cap, 111 CXL_HDM_DECODER_CAPABILITY, 112 DECODER_COUNT)); 113 for (i = 0; i < hdm_count; i++) { 114 uint32_t ctrl, ig_enc, iw_enc, target_idx; 115 uint32_t low, high; 116 uint64_t base, size; 117 118 low = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_LO + i * hdm_inc); 119 high = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_HI + i * hdm_inc); 120 base = (low & 0xf0000000) | ((uint64_t)high << 32); 121 low = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_LO + i * hdm_inc); 122 high = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_HI + i * hdm_inc); 123 size = (low & 0xf0000000) | ((uint64_t)high << 32); 124 if (addr < base || addr >= base + size) { 125 continue; 126 } 127 128 ctrl = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + i * hdm_inc); 129 if (!FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED)) { 130 return false; 131 } 132 found = true; 133 ig_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IG); 134 iw_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW); 135 target_idx = (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc); 136 137 if (target_idx < 4) { 138 uint32_t val = ldl_le_p(cache_mem + 139 R_CXL_HDM_DECODER0_TARGET_LIST_LO + 140 i * hdm_inc); 141 *target = extract32(val, target_idx * 8, 8); 142 } else { 143 uint32_t val = ldl_le_p(cache_mem + 144 R_CXL_HDM_DECODER0_TARGET_LIST_HI + 145 i * hdm_inc); 146 *target = extract32(val, (target_idx - 4) * 8, 8); 147 } 148 break; 149 } 150 151 return found; 152 } 153 154 static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr) 155 { 156 CXLComponentState *hb_cstate, *usp_cstate; 157 PCIHostState *hb; 158 CXLUpstreamPort *usp; 159 int rb_index; 160 uint32_t *cache_mem; 161 uint8_t target; 162 bool target_found; 163 PCIDevice *rp, *d; 164 165 /* Address is relative to memory region. Convert to HPA */ 166 addr += fw->base; 167 168 rb_index = (addr / cxl_decode_ig(fw->enc_int_gran)) % fw->num_targets; 169 hb = PCI_HOST_BRIDGE(fw->target_hbs[rb_index]->cxl_host_bridge); 170 if (!hb || !hb->bus || !pci_bus_is_cxl(hb->bus)) { 171 return NULL; 172 } 173 174 if (cxl_get_hb_passthrough(hb)) { 175 rp = pcie_find_port_first(hb->bus); 176 if (!rp) { 177 return NULL; 178 } 179 } else { 180 hb_cstate = cxl_get_hb_cstate(hb); 181 if (!hb_cstate) { 182 return NULL; 183 } 184 185 cache_mem = hb_cstate->crb.cache_mem_registers; 186 187 target_found = cxl_hdm_find_target(cache_mem, addr, &target); 188 if (!target_found) { 189 return NULL; 190 } 191 192 rp = pcie_find_port_by_pn(hb->bus, target); 193 if (!rp) { 194 return NULL; 195 } 196 } 197 198 d = pci_bridge_get_sec_bus(PCI_BRIDGE(rp))->devices[0]; 199 if (!d) { 200 return NULL; 201 } 202 203 if (object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3)) { 204 return d; 205 } 206 207 /* 208 * Could also be a switch. Note only one level of switching currently 209 * supported. 210 */ 211 if (!object_dynamic_cast(OBJECT(d), TYPE_CXL_USP)) { 212 return NULL; 213 } 214 usp = CXL_USP(d); 215 216 usp_cstate = cxl_usp_to_cstate(usp); 217 if (!usp_cstate) { 218 return NULL; 219 } 220 221 cache_mem = usp_cstate->crb.cache_mem_registers; 222 223 target_found = cxl_hdm_find_target(cache_mem, addr, &target); 224 if (!target_found) { 225 return NULL; 226 } 227 228 d = pcie_find_port_by_pn(&PCI_BRIDGE(d)->sec_bus, target); 229 if (!d) { 230 return NULL; 231 } 232 233 d = pci_bridge_get_sec_bus(PCI_BRIDGE(d))->devices[0]; 234 if (!d) { 235 return NULL; 236 } 237 238 if (!object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3)) { 239 return NULL; 240 } 241 242 return d; 243 } 244 245 static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t *data, 246 unsigned size, MemTxAttrs attrs) 247 { 248 CXLFixedWindow *fw = opaque; 249 PCIDevice *d; 250 251 d = cxl_cfmws_find_device(fw, addr); 252 if (d == NULL) { 253 *data = 0; 254 /* Reads to invalid address return poison */ 255 return MEMTX_ERROR; 256 } 257 258 return cxl_type3_read(d, addr + fw->base, data, size, attrs); 259 } 260 261 static MemTxResult cxl_write_cfmws(void *opaque, hwaddr addr, 262 uint64_t data, unsigned size, 263 MemTxAttrs attrs) 264 { 265 CXLFixedWindow *fw = opaque; 266 PCIDevice *d; 267 268 d = cxl_cfmws_find_device(fw, addr); 269 if (d == NULL) { 270 /* Writes to invalid address are silent */ 271 return MEMTX_OK; 272 } 273 274 return cxl_type3_write(d, addr + fw->base, data, size, attrs); 275 } 276 277 const MemoryRegionOps cfmws_ops = { 278 .read_with_attrs = cxl_read_cfmws, 279 .write_with_attrs = cxl_write_cfmws, 280 .endianness = DEVICE_LITTLE_ENDIAN, 281 .valid = { 282 .min_access_size = 1, 283 .max_access_size = 8, 284 .unaligned = true, 285 }, 286 .impl = { 287 .min_access_size = 1, 288 .max_access_size = 8, 289 .unaligned = true, 290 }, 291 }; 292 293 static void machine_get_cxl(Object *obj, Visitor *v, const char *name, 294 void *opaque, Error **errp) 295 { 296 CXLState *cxl_state = opaque; 297 bool value = cxl_state->is_enabled; 298 299 visit_type_bool(v, name, &value, errp); 300 } 301 302 static void machine_set_cxl(Object *obj, Visitor *v, const char *name, 303 void *opaque, Error **errp) 304 { 305 CXLState *cxl_state = opaque; 306 bool value; 307 308 if (!visit_type_bool(v, name, &value, errp)) { 309 return; 310 } 311 cxl_state->is_enabled = value; 312 } 313 314 static void machine_get_cfmw(Object *obj, Visitor *v, const char *name, 315 void *opaque, Error **errp) 316 { 317 CXLFixedMemoryWindowOptionsList **list = opaque; 318 319 visit_type_CXLFixedMemoryWindowOptionsList(v, name, list, errp); 320 } 321 322 static void machine_set_cfmw(Object *obj, Visitor *v, const char *name, 323 void *opaque, Error **errp) 324 { 325 CXLState *state = opaque; 326 CXLFixedMemoryWindowOptionsList *cfmw_list = NULL; 327 CXLFixedMemoryWindowOptionsList *it; 328 329 visit_type_CXLFixedMemoryWindowOptionsList(v, name, &cfmw_list, errp); 330 if (!cfmw_list) { 331 return; 332 } 333 334 for (it = cfmw_list; it; it = it->next) { 335 cxl_fixed_memory_window_config(state, it->value, errp); 336 } 337 state->cfmw_list = cfmw_list; 338 } 339 340 void cxl_machine_init(Object *obj, CXLState *state) 341 { 342 object_property_add(obj, "cxl", "bool", machine_get_cxl, 343 machine_set_cxl, NULL, state); 344 object_property_set_description(obj, "cxl", 345 "Set on/off to enable/disable " 346 "CXL instantiation"); 347 348 object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow", 349 machine_get_cfmw, machine_set_cfmw, 350 NULL, state); 351 object_property_set_description(obj, "cxl-fmw", 352 "CXL Fixed Memory Windows (array)"); 353 } 354 355 void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp) 356 { 357 /* Walk the pci busses looking for pxb busses to hook up */ 358 if (bus) { 359 QLIST_FOREACH(bus, &bus->child, sibling) { 360 if (!pci_bus_is_root(bus)) { 361 continue; 362 } 363 if (pci_bus_is_cxl(bus)) { 364 if (!state->is_enabled) { 365 error_setg(errp, "CXL host bridges present, but cxl=off"); 366 return; 367 } 368 pxb_cxl_hook_up_registers(state, bus, errp); 369 } 370 } 371 } 372 } 373