1 /*
2 * CXL host parameter parsing routines
3 *
4 * Copyright (c) 2022 Huawei
5 * Modeled loosely on the NUMA options handling in hw/core/numa.c
6 */
7
8 #include "qemu/osdep.h"
9 #include "qemu/units.h"
10 #include "qemu/bitmap.h"
11 #include "qemu/error-report.h"
12 #include "qapi/error.h"
13 #include "sysemu/qtest.h"
14 #include "hw/boards.h"
15
16 #include "qapi/qapi-visit-machine.h"
17 #include "hw/cxl/cxl.h"
18 #include "hw/cxl/cxl_host.h"
19 #include "hw/pci/pci_bus.h"
20 #include "hw/pci/pci_bridge.h"
21 #include "hw/pci/pci_host.h"
22 #include "hw/pci/pcie_port.h"
23 #include "hw/pci-bridge/pci_expander_bridge.h"
24
cxl_fixed_memory_window_config(CXLState * cxl_state,CXLFixedMemoryWindowOptions * object,Error ** errp)25 static void cxl_fixed_memory_window_config(CXLState *cxl_state,
26 CXLFixedMemoryWindowOptions *object,
27 Error **errp)
28 {
29 ERRP_GUARD();
30 g_autofree CXLFixedWindow *fw = g_malloc0(sizeof(*fw));
31 strList *target;
32 int i;
33
34 for (target = object->targets; target; target = target->next) {
35 fw->num_targets++;
36 }
37
38 fw->enc_int_ways = cxl_interleave_ways_enc(fw->num_targets, errp);
39 if (*errp) {
40 return;
41 }
42
43 if (object->size % (256 * MiB)) {
44 error_setg(errp,
45 "Size of a CXL fixed memory window must be a multiple of 256MiB");
46 return;
47 }
48 fw->size = object->size;
49
50 if (object->has_interleave_granularity) {
51 fw->enc_int_gran =
52 cxl_interleave_granularity_enc(object->interleave_granularity,
53 errp);
54 if (*errp) {
55 return;
56 }
57 } else {
58 /* Default to 256 byte interleave */
59 fw->enc_int_gran = 0;
60 }
61
62 fw->targets = g_malloc0_n(fw->num_targets, sizeof(*fw->targets));
63 for (i = 0, target = object->targets; target; i++, target = target->next) {
64 /* This link cannot be resolved yet, so stash the name for now */
65 fw->targets[i] = g_strdup(target->value);
66 }
67
68 cxl_state->fixed_windows = g_list_append(cxl_state->fixed_windows,
69 g_steal_pointer(&fw));
70
71 return;
72 }
73
cxl_fmws_link_targets(CXLState * cxl_state,Error ** errp)74 void cxl_fmws_link_targets(CXLState *cxl_state, Error **errp)
75 {
76 if (cxl_state && cxl_state->fixed_windows) {
77 GList *it;
78
79 for (it = cxl_state->fixed_windows; it; it = it->next) {
80 CXLFixedWindow *fw = it->data;
81 int i;
82
83 for (i = 0; i < fw->num_targets; i++) {
84 Object *o;
85 bool ambig;
86
87 o = object_resolve_path_type(fw->targets[i],
88 TYPE_PXB_CXL_DEV,
89 &ambig);
90 if (!o) {
91 error_setg(errp, "Could not resolve CXLFM target %s",
92 fw->targets[i]);
93 return;
94 }
95 fw->target_hbs[i] = PXB_CXL_DEV(o);
96 }
97 }
98 }
99 }
100
cxl_hdm_find_target(uint32_t * cache_mem,hwaddr addr,uint8_t * target)101 static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
102 uint8_t *target)
103 {
104 int hdm_inc = R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_LO;
105 unsigned int hdm_count;
106 bool found = false;
107 int i;
108 uint32_t cap;
109
110 cap = ldl_le_p(cache_mem + R_CXL_HDM_DECODER_CAPABILITY);
111 hdm_count = cxl_decoder_count_dec(FIELD_EX32(cap,
112 CXL_HDM_DECODER_CAPABILITY,
113 DECODER_COUNT));
114 for (i = 0; i < hdm_count; i++) {
115 uint32_t ctrl, ig_enc, iw_enc, target_idx;
116 uint32_t low, high;
117 uint64_t base, size;
118
119 low = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_LO + i * hdm_inc);
120 high = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_HI + i * hdm_inc);
121 base = (low & 0xf0000000) | ((uint64_t)high << 32);
122 low = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_LO + i * hdm_inc);
123 high = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_HI + i * hdm_inc);
124 size = (low & 0xf0000000) | ((uint64_t)high << 32);
125 if (addr < base || addr >= base + size) {
126 continue;
127 }
128
129 ctrl = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + i * hdm_inc);
130 if (!FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED)) {
131 return false;
132 }
133 found = true;
134 ig_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IG);
135 iw_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW);
136 target_idx = (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc);
137
138 if (target_idx < 4) {
139 uint32_t val = ldl_le_p(cache_mem +
140 R_CXL_HDM_DECODER0_TARGET_LIST_LO +
141 i * hdm_inc);
142 *target = extract32(val, target_idx * 8, 8);
143 } else {
144 uint32_t val = ldl_le_p(cache_mem +
145 R_CXL_HDM_DECODER0_TARGET_LIST_HI +
146 i * hdm_inc);
147 *target = extract32(val, (target_idx - 4) * 8, 8);
148 }
149 break;
150 }
151
152 return found;
153 }
154
cxl_cfmws_find_device(CXLFixedWindow * fw,hwaddr addr)155 static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr)
156 {
157 CXLComponentState *hb_cstate, *usp_cstate;
158 PCIHostState *hb;
159 CXLUpstreamPort *usp;
160 int rb_index;
161 uint32_t *cache_mem;
162 uint8_t target;
163 bool target_found;
164 PCIDevice *rp, *d;
165
166 /* Address is relative to memory region. Convert to HPA */
167 addr += fw->base;
168
169 rb_index = (addr / cxl_decode_ig(fw->enc_int_gran)) % fw->num_targets;
170 hb = PCI_HOST_BRIDGE(fw->target_hbs[rb_index]->cxl_host_bridge);
171 if (!hb || !hb->bus || !pci_bus_is_cxl(hb->bus)) {
172 return NULL;
173 }
174
175 if (cxl_get_hb_passthrough(hb)) {
176 rp = pcie_find_port_first(hb->bus);
177 if (!rp) {
178 return NULL;
179 }
180 } else {
181 hb_cstate = cxl_get_hb_cstate(hb);
182 if (!hb_cstate) {
183 return NULL;
184 }
185
186 cache_mem = hb_cstate->crb.cache_mem_registers;
187
188 target_found = cxl_hdm_find_target(cache_mem, addr, &target);
189 if (!target_found) {
190 return NULL;
191 }
192
193 rp = pcie_find_port_by_pn(hb->bus, target);
194 if (!rp) {
195 return NULL;
196 }
197 }
198
199 d = pci_bridge_get_sec_bus(PCI_BRIDGE(rp))->devices[0];
200 if (!d) {
201 return NULL;
202 }
203
204 if (object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3)) {
205 return d;
206 }
207
208 /*
209 * Could also be a switch. Note only one level of switching currently
210 * supported.
211 */
212 if (!object_dynamic_cast(OBJECT(d), TYPE_CXL_USP)) {
213 return NULL;
214 }
215 usp = CXL_USP(d);
216
217 usp_cstate = cxl_usp_to_cstate(usp);
218 if (!usp_cstate) {
219 return NULL;
220 }
221
222 cache_mem = usp_cstate->crb.cache_mem_registers;
223
224 target_found = cxl_hdm_find_target(cache_mem, addr, &target);
225 if (!target_found) {
226 return NULL;
227 }
228
229 d = pcie_find_port_by_pn(&PCI_BRIDGE(d)->sec_bus, target);
230 if (!d) {
231 return NULL;
232 }
233
234 d = pci_bridge_get_sec_bus(PCI_BRIDGE(d))->devices[0];
235 if (!d) {
236 return NULL;
237 }
238
239 if (!object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3)) {
240 return NULL;
241 }
242
243 return d;
244 }
245
cxl_read_cfmws(void * opaque,hwaddr addr,uint64_t * data,unsigned size,MemTxAttrs attrs)246 static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t *data,
247 unsigned size, MemTxAttrs attrs)
248 {
249 CXLFixedWindow *fw = opaque;
250 PCIDevice *d;
251
252 d = cxl_cfmws_find_device(fw, addr);
253 if (d == NULL) {
254 *data = 0;
255 /* Reads to invalid address return poison */
256 return MEMTX_ERROR;
257 }
258
259 return cxl_type3_read(d, addr + fw->base, data, size, attrs);
260 }
261
cxl_write_cfmws(void * opaque,hwaddr addr,uint64_t data,unsigned size,MemTxAttrs attrs)262 static MemTxResult cxl_write_cfmws(void *opaque, hwaddr addr,
263 uint64_t data, unsigned size,
264 MemTxAttrs attrs)
265 {
266 CXLFixedWindow *fw = opaque;
267 PCIDevice *d;
268
269 d = cxl_cfmws_find_device(fw, addr);
270 if (d == NULL) {
271 /* Writes to invalid address are silent */
272 return MEMTX_OK;
273 }
274
275 return cxl_type3_write(d, addr + fw->base, data, size, attrs);
276 }
277
278 const MemoryRegionOps cfmws_ops = {
279 .read_with_attrs = cxl_read_cfmws,
280 .write_with_attrs = cxl_write_cfmws,
281 .endianness = DEVICE_LITTLE_ENDIAN,
282 .valid = {
283 .min_access_size = 1,
284 .max_access_size = 8,
285 .unaligned = true,
286 },
287 .impl = {
288 .min_access_size = 1,
289 .max_access_size = 8,
290 .unaligned = true,
291 },
292 };
293
machine_get_cxl(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)294 static void machine_get_cxl(Object *obj, Visitor *v, const char *name,
295 void *opaque, Error **errp)
296 {
297 CXLState *cxl_state = opaque;
298 bool value = cxl_state->is_enabled;
299
300 visit_type_bool(v, name, &value, errp);
301 }
302
machine_set_cxl(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)303 static void machine_set_cxl(Object *obj, Visitor *v, const char *name,
304 void *opaque, Error **errp)
305 {
306 CXLState *cxl_state = opaque;
307 bool value;
308
309 if (!visit_type_bool(v, name, &value, errp)) {
310 return;
311 }
312 cxl_state->is_enabled = value;
313 }
314
machine_get_cfmw(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)315 static void machine_get_cfmw(Object *obj, Visitor *v, const char *name,
316 void *opaque, Error **errp)
317 {
318 CXLState *state = opaque;
319 CXLFixedMemoryWindowOptionsList **list = &state->cfmw_list;
320
321 visit_type_CXLFixedMemoryWindowOptionsList(v, name, list, errp);
322 }
323
machine_set_cfmw(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)324 static void machine_set_cfmw(Object *obj, Visitor *v, const char *name,
325 void *opaque, Error **errp)
326 {
327 CXLState *state = opaque;
328 CXLFixedMemoryWindowOptionsList *cfmw_list = NULL;
329 CXLFixedMemoryWindowOptionsList *it;
330
331 visit_type_CXLFixedMemoryWindowOptionsList(v, name, &cfmw_list, errp);
332 if (!cfmw_list) {
333 return;
334 }
335
336 for (it = cfmw_list; it; it = it->next) {
337 cxl_fixed_memory_window_config(state, it->value, errp);
338 }
339 state->cfmw_list = cfmw_list;
340 }
341
cxl_machine_init(Object * obj,CXLState * state)342 void cxl_machine_init(Object *obj, CXLState *state)
343 {
344 object_property_add(obj, "cxl", "bool", machine_get_cxl,
345 machine_set_cxl, NULL, state);
346 object_property_set_description(obj, "cxl",
347 "Set on/off to enable/disable "
348 "CXL instantiation");
349
350 object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow",
351 machine_get_cfmw, machine_set_cfmw,
352 NULL, state);
353 object_property_set_description(obj, "cxl-fmw",
354 "CXL Fixed Memory Windows (array)");
355 }
356
cxl_hook_up_pxb_registers(PCIBus * bus,CXLState * state,Error ** errp)357 void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp)
358 {
359 /* Walk the pci busses looking for pxb busses to hook up */
360 if (bus) {
361 QLIST_FOREACH(bus, &bus->child, sibling) {
362 if (!pci_bus_is_root(bus)) {
363 continue;
364 }
365 if (pci_bus_is_cxl(bus)) {
366 if (!state->is_enabled) {
367 error_setg(errp, "CXL host bridges present, but cxl=off");
368 return;
369 }
370 pxb_cxl_hook_up_registers(state, bus, errp);
371 }
372 }
373 }
374 }
375