1 /* 2 * CXL Utility library for components 3 * 4 * Copyright(C) 2020 Intel Corporation. 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "hw/pci/pci.h" 14 #include "hw/cxl/cxl.h" 15 16 static uint64_t cxl_cache_mem_read_reg(void *opaque, hwaddr offset, 17 unsigned size) 18 { 19 CXLComponentState *cxl_cstate = opaque; 20 ComponentRegisters *cregs = &cxl_cstate->crb; 21 22 if (size == 8) { 23 qemu_log_mask(LOG_UNIMP, 24 "CXL 8 byte cache mem registers not implemented\n"); 25 return 0; 26 } 27 28 if (cregs->special_ops && cregs->special_ops->read) { 29 return cregs->special_ops->read(cxl_cstate, offset, size); 30 } else { 31 return cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)]; 32 } 33 } 34 35 static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset, 36 uint32_t value) 37 { 38 ComponentRegisters *cregs = &cxl_cstate->crb; 39 uint32_t *cache_mem = cregs->cache_mem_registers; 40 bool should_commit = false; 41 42 switch (offset) { 43 case A_CXL_HDM_DECODER0_CTRL: 44 should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT); 45 break; 46 default: 47 break; 48 } 49 50 memory_region_transaction_begin(); 51 stl_le_p((uint8_t *)cache_mem + offset, value); 52 if (should_commit) { 53 ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0); 54 ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0); 55 ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); 56 } 57 memory_region_transaction_commit(); 58 } 59 60 static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value, 61 unsigned size) 62 { 63 CXLComponentState *cxl_cstate = opaque; 64 ComponentRegisters *cregs = &cxl_cstate->crb; 65 uint32_t mask; 66 67 if (size == 8) { 68 qemu_log_mask(LOG_UNIMP, 69 "CXL 8 byte cache mem registers not implemented\n"); 70 return; 71 } 72 mask = cregs->cache_mem_regs_write_mask[offset / sizeof(*cregs->cache_mem_regs_write_mask)]; 73 value &= mask; 74 /* RO bits should remain constant. Done by reading existing value */ 75 value |= ~mask & cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)]; 76 if (cregs->special_ops && cregs->special_ops->write) { 77 cregs->special_ops->write(cxl_cstate, offset, value, size); 78 return; 79 } 80 81 if (offset >= A_CXL_HDM_DECODER_CAPABILITY && 82 offset <= A_CXL_HDM_DECODER0_TARGET_LIST_HI) { 83 dumb_hdm_handler(cxl_cstate, offset, value); 84 } else { 85 cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)] = value; 86 } 87 } 88 89 /* 90 * 8.2.3 91 * The access restrictions specified in Section 8.2.2 also apply to CXL 2.0 92 * Component Registers. 93 * 94 * 8.2.2 95 * • A 32 bit register shall be accessed as a 4 Bytes quantity. Partial 96 * reads are not permitted. 97 * • A 64 bit register shall be accessed as a 8 Bytes quantity. Partial 98 * reads are not permitted. 99 * 100 * As of the spec defined today, only 4 byte registers exist. 101 */ 102 static const MemoryRegionOps cache_mem_ops = { 103 .read = cxl_cache_mem_read_reg, 104 .write = cxl_cache_mem_write_reg, 105 .endianness = DEVICE_LITTLE_ENDIAN, 106 .valid = { 107 .min_access_size = 4, 108 .max_access_size = 8, 109 .unaligned = false, 110 }, 111 .impl = { 112 .min_access_size = 4, 113 .max_access_size = 8, 114 }, 115 }; 116 117 void cxl_component_register_block_init(Object *obj, 118 CXLComponentState *cxl_cstate, 119 const char *type) 120 { 121 ComponentRegisters *cregs = &cxl_cstate->crb; 122 123 memory_region_init(&cregs->component_registers, obj, type, 124 CXL2_COMPONENT_BLOCK_SIZE); 125 126 /* io registers controls link which we don't care about in QEMU */ 127 memory_region_init_io(&cregs->io, obj, NULL, cregs, ".io", 128 CXL2_COMPONENT_IO_REGION_SIZE); 129 memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs, 130 ".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE); 131 132 memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io); 133 memory_region_add_subregion(&cregs->component_registers, 134 CXL2_COMPONENT_IO_REGION_SIZE, 135 &cregs->cache_mem); 136 } 137 138 static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk) 139 { 140 /* 141 * Error status is RW1C but given bits are not yet set, it can 142 * be handled as RO. 143 */ 144 reg_state[R_CXL_RAS_UNC_ERR_STATUS] = 0; 145 /* Bits 12-13 and 17-31 reserved in CXL 2.0 */ 146 reg_state[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff; 147 write_msk[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff; 148 reg_state[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff; 149 write_msk[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff; 150 reg_state[R_CXL_RAS_COR_ERR_STATUS] = 0; 151 reg_state[R_CXL_RAS_COR_ERR_MASK] = 0x7f; 152 write_msk[R_CXL_RAS_COR_ERR_MASK] = 0x7f; 153 /* CXL switches and devices must set */ 154 reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00; 155 } 156 157 static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, 158 enum reg_type type) 159 { 160 int decoder_count = 1; 161 int i; 162 163 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, 164 cxl_decoder_count_enc(decoder_count)); 165 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 1); 166 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 1); 167 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 1); 168 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 0); 169 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL, 170 HDM_DECODER_ENABLE, 0); 171 write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] = 0x3; 172 for (i = 0; i < decoder_count; i++) { 173 write_msk[R_CXL_HDM_DECODER0_BASE_LO + i * 0x20] = 0xf0000000; 174 write_msk[R_CXL_HDM_DECODER0_BASE_HI + i * 0x20] = 0xffffffff; 175 write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000; 176 write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff; 177 write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff; 178 if (type == CXL2_DEVICE || 179 type == CXL2_TYPE3_DEVICE || 180 type == CXL2_LOGICAL_DEVICE) { 181 write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xf0000000; 182 } else { 183 write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xffffffff; 184 } 185 write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff; 186 } 187 } 188 189 void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk, 190 enum reg_type type) 191 { 192 int caps = 0; 193 194 /* 195 * In CXL 2.0 the capabilities required for each CXL component are such that, 196 * with the ordering chosen here, a single number can be used to define 197 * which capabilities should be provided. 198 */ 199 switch (type) { 200 case CXL2_DOWNSTREAM_PORT: 201 case CXL2_DEVICE: 202 /* RAS, Link */ 203 caps = 2; 204 break; 205 case CXL2_UPSTREAM_PORT: 206 case CXL2_TYPE3_DEVICE: 207 case CXL2_LOGICAL_DEVICE: 208 /* + HDM */ 209 caps = 3; 210 break; 211 case CXL2_ROOT_PORT: 212 /* + Extended Security, + Snoop */ 213 caps = 5; 214 break; 215 default: 216 abort(); 217 } 218 219 memset(reg_state, 0, CXL2_COMPONENT_CM_REGION_SIZE); 220 221 /* CXL Capability Header Register */ 222 ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ID, 1); 223 ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, VERSION, 1); 224 ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 1); 225 ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps); 226 227 #define init_cap_reg(reg, id, version) \ 228 QEMU_BUILD_BUG_ON(CXL_##reg##_REGISTERS_OFFSET == 0); \ 229 do { \ 230 int which = R_CXL_##reg##_CAPABILITY_HEADER; \ 231 reg_state[which] = FIELD_DP32(reg_state[which], \ 232 CXL_##reg##_CAPABILITY_HEADER, ID, id); \ 233 reg_state[which] = \ 234 FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, \ 235 VERSION, version); \ 236 reg_state[which] = \ 237 FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, PTR, \ 238 CXL_##reg##_REGISTERS_OFFSET); \ 239 } while (0) 240 241 init_cap_reg(RAS, 2, 2); 242 ras_init_common(reg_state, write_msk); 243 244 init_cap_reg(LINK, 4, 2); 245 246 if (caps < 3) { 247 return; 248 } 249 250 init_cap_reg(HDM, 5, 1); 251 hdm_init_common(reg_state, write_msk, type); 252 253 if (caps < 5) { 254 return; 255 } 256 257 init_cap_reg(EXTSEC, 6, 1); 258 init_cap_reg(SNOOP, 8, 1); 259 260 #undef init_cap_reg 261 } 262 263 /* 264 * Helper to creates a DVSEC header for a CXL entity. The caller is responsible 265 * for tracking the valid offset. 266 * 267 * This function will build the DVSEC header on behalf of the caller and then 268 * copy in the remaining data for the vendor specific bits. 269 * It will also set up appropriate write masks. 270 */ 271 void cxl_component_create_dvsec(CXLComponentState *cxl, 272 enum reg_type cxl_dev_type, uint16_t length, 273 uint16_t type, uint8_t rev, uint8_t *body) 274 { 275 PCIDevice *pdev = cxl->pdev; 276 uint16_t offset = cxl->dvsec_offset; 277 uint8_t *wmask = pdev->wmask; 278 279 assert(offset >= PCI_CFG_SPACE_SIZE && 280 ((offset + length) < PCI_CFG_SPACE_EXP_SIZE)); 281 assert((length & 0xf000) == 0); 282 assert((rev & ~0xf) == 0); 283 284 /* Create the DVSEC in the MCFG space */ 285 pcie_add_capability(pdev, PCI_EXT_CAP_ID_DVSEC, 1, offset, length); 286 pci_set_long(pdev->config + offset + PCIE_DVSEC_HEADER1_OFFSET, 287 (length << 20) | (rev << 16) | CXL_VENDOR_ID); 288 pci_set_word(pdev->config + offset + PCIE_DVSEC_ID_OFFSET, type); 289 memcpy(pdev->config + offset + sizeof(DVSECHeader), 290 body + sizeof(DVSECHeader), 291 length - sizeof(DVSECHeader)); 292 293 /* Configure write masks */ 294 switch (type) { 295 case PCIE_CXL_DEVICE_DVSEC: 296 /* Cntrl RW Lock - so needs explicit blocking when lock is set */ 297 wmask[offset + offsetof(CXLDVSECDevice, ctrl)] = 0xFD; 298 wmask[offset + offsetof(CXLDVSECDevice, ctrl) + 1] = 0x4F; 299 /* Status is RW1CS */ 300 wmask[offset + offsetof(CXLDVSECDevice, ctrl2)] = 0x0F; 301 /* Lock is RW Once */ 302 wmask[offset + offsetof(CXLDVSECDevice, lock)] = 0x01; 303 /* range1/2_base_high/low is RW Lock */ 304 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi)] = 0xFF; 305 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 1] = 0xFF; 306 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 2] = 0xFF; 307 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 3] = 0xFF; 308 wmask[offset + offsetof(CXLDVSECDevice, range1_base_lo) + 3] = 0xF0; 309 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi)] = 0xFF; 310 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 1] = 0xFF; 311 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 2] = 0xFF; 312 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 3] = 0xFF; 313 wmask[offset + offsetof(CXLDVSECDevice, range2_base_lo) + 3] = 0xF0; 314 break; 315 case NON_CXL_FUNCTION_MAP_DVSEC: 316 break; /* Not yet implemented */ 317 case EXTENSIONS_PORT_DVSEC: 318 wmask[offset + offsetof(CXLDVSECPortExtensions, control)] = 0x0F; 319 wmask[offset + offsetof(CXLDVSECPortExtensions, control) + 1] = 0x40; 320 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_base)] = 0xFF; 321 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_limit)] = 0xFF; 322 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base)] = 0xF0; 323 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base) + 1] = 0xFF; 324 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit)] = 0xF0; 325 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit) + 1] = 0xFF; 326 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base)] = 0xF0; 327 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base) + 1] = 0xFF; 328 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit)] = 0xF0; 329 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit) + 1] = 0xFF; 330 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high)] = 0xFF; 331 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 1] = 0xFF; 332 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 2] = 0xFF; 333 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 3] = 0xFF; 334 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high)] = 0xFF; 335 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 1] = 0xFF; 336 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 2] = 0xFF; 337 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 3] = 0xFF; 338 break; 339 case GPF_PORT_DVSEC: 340 wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl)] = 0x0F; 341 wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl) + 1] = 0x0F; 342 wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl)] = 0x0F; 343 wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl) + 1] = 0x0F; 344 break; 345 case GPF_DEVICE_DVSEC: 346 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration)] = 0x0F; 347 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration) + 1] = 0x0F; 348 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power)] = 0xFF; 349 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 1] = 0xFF; 350 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 2] = 0xFF; 351 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 3] = 0xFF; 352 break; 353 case PCIE_FLEXBUS_PORT_DVSEC: 354 switch (cxl_dev_type) { 355 case CXL2_ROOT_PORT: 356 /* No MLD */ 357 wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xbd; 358 break; 359 case CXL2_DOWNSTREAM_PORT: 360 wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xfd; 361 break; 362 default: /* Registers are RO for other component types */ 363 break; 364 } 365 /* There are rw1cs bits in the status register but never set currently */ 366 break; 367 } 368 369 /* Update state for future DVSEC additions */ 370 range_init_nofail(&cxl->dvsecs[type], cxl->dvsec_offset, length); 371 cxl->dvsec_offset += length; 372 } 373 374 uint8_t cxl_interleave_ways_enc(int iw, Error **errp) 375 { 376 switch (iw) { 377 case 1: return 0x0; 378 case 2: return 0x1; 379 case 4: return 0x2; 380 case 8: return 0x3; 381 case 16: return 0x4; 382 case 3: return 0x8; 383 case 6: return 0x9; 384 case 12: return 0xa; 385 default: 386 error_setg(errp, "Interleave ways: %d not supported", iw); 387 return 0; 388 } 389 } 390 391 uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp) 392 { 393 switch (gran) { 394 case 256: return 0; 395 case 512: return 1; 396 case 1024: return 2; 397 case 2048: return 3; 398 case 4096: return 4; 399 case 8192: return 5; 400 case 16384: return 6; 401 default: 402 error_setg(errp, "Interleave granularity: %" PRIu64 " invalid", gran); 403 return 0; 404 } 405 } 406