xref: /openbmc/qemu/hw/cpu/realview_mpcore.c (revision 8fa3b702)
1 /*
2  * RealView ARM11MPCore internal peripheral emulation
3  *
4  * Copyright (c) 2006-2007 CodeSourcery.
5  * Copyright (c) 2013 SUSE LINUX Products GmbH
6  * Written by Paul Brook and Andreas Färber
7  *
8  * This code is licensed under the GPL.
9  */
10 
11 #include "qemu/osdep.h"
12 #include "qapi/error.h"
13 #include "qemu/module.h"
14 #include "hw/cpu/arm11mpcore.h"
15 #include "hw/intc/realview_gic.h"
16 #include "hw/irq.h"
17 #include "hw/qdev-properties.h"
18 #include "qom/object.h"
19 
20 #define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
21 typedef struct mpcore_rirq_state mpcore_rirq_state;
22 DECLARE_INSTANCE_CHECKER(mpcore_rirq_state, REALVIEW_MPCORE_RIRQ,
23                          TYPE_REALVIEW_MPCORE_RIRQ)
24 
25 /* Dummy PIC to route IRQ lines.  The baseboard has 4 independent IRQ
26    controllers.  The output of these, plus some of the raw input lines
27    are fed into a single SMP-aware interrupt controller on the CPU.  */
28 struct mpcore_rirq_state {
29     SysBusDevice parent_obj;
30 
31     qemu_irq cpuic[32];
32     qemu_irq rvic[4][64];
33     uint32_t num_cpu;
34 
35     ARM11MPCorePriveState priv;
36     RealViewGICState gic[4];
37 };
38 
39 /* Map baseboard IRQs onto CPU IRQ lines.  */
40 static const int mpcore_irq_map[32] = {
41     -1, -1, -1, -1,  1,  2, -1, -1,
42     -1, -1,  6, -1,  4,  5, -1, -1,
43     -1, 14, 15,  0,  7,  8, -1, -1,
44     -1, -1, -1, -1,  9,  3, -1, -1,
45 };
46 
47 static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
48 {
49     mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
50     int i;
51 
52     for (i = 0; i < 4; i++) {
53         qemu_set_irq(s->rvic[i][irq], level);
54     }
55     if (irq < 32) {
56         irq = mpcore_irq_map[irq];
57         if (irq >= 0) {
58             qemu_set_irq(s->cpuic[irq], level);
59         }
60     }
61 }
62 
63 static void realview_mpcore_realize(DeviceState *dev, Error **errp)
64 {
65     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
66     mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev);
67     DeviceState *priv = DEVICE(&s->priv);
68     DeviceState *gic;
69     SysBusDevice *gicbusdev;
70     int n;
71     int i;
72 
73     qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
74     if (!sysbus_realize(SYS_BUS_DEVICE(&s->priv), errp)) {
75         return;
76     }
77     sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->priv));
78     for (i = 0; i < 32; i++) {
79         s->cpuic[i] = qdev_get_gpio_in(priv, i);
80     }
81     /* ??? IRQ routing is hardcoded to "normal" mode.  */
82     for (n = 0; n < 4; n++) {
83         if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic[n]), errp)) {
84             return;
85         }
86         gic = DEVICE(&s->gic[n]);
87         gicbusdev = SYS_BUS_DEVICE(&s->gic[n]);
88         sysbus_mmio_map(gicbusdev, 0, 0x10040000 + n * 0x10000);
89         sysbus_connect_irq(gicbusdev, 0, s->cpuic[10 + n]);
90         for (i = 0; i < 64; i++) {
91             s->rvic[n][i] = qdev_get_gpio_in(gic, i);
92         }
93     }
94     qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64);
95 }
96 
97 static void mpcore_rirq_init(Object *obj)
98 {
99     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
100     mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(obj);
101     SysBusDevice *privbusdev;
102     int i;
103 
104     object_initialize_child(obj, "a11priv", &s->priv, TYPE_ARM11MPCORE_PRIV);
105     privbusdev = SYS_BUS_DEVICE(&s->priv);
106     sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0));
107 
108     for (i = 0; i < 4; i++) {
109         object_initialize_child(obj, "gic[*]", &s->gic[i], TYPE_REALVIEW_GIC);
110     }
111 }
112 
113 static Property mpcore_rirq_properties[] = {
114     DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
115     DEFINE_PROP_END_OF_LIST(),
116 };
117 
118 static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
119 {
120     DeviceClass *dc = DEVICE_CLASS(klass);
121 
122     dc->realize = realview_mpcore_realize;
123     device_class_set_props(dc, mpcore_rirq_properties);
124 }
125 
126 static const TypeInfo mpcore_rirq_info = {
127     .name          = TYPE_REALVIEW_MPCORE_RIRQ,
128     .parent        = TYPE_SYS_BUS_DEVICE,
129     .instance_size = sizeof(mpcore_rirq_state),
130     .instance_init = mpcore_rirq_init,
131     .class_init    = mpcore_rirq_class_init,
132 };
133 
134 static void realview_mpcore_register_types(void)
135 {
136     type_register_static(&mpcore_rirq_info);
137 }
138 
139 type_init(realview_mpcore_register_types)
140