1 /* 2 * RealView ARM11MPCore internal peripheral emulation 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Copyright (c) 2013 SUSE LINUX Products GmbH 6 * Written by Paul Brook and Andreas Färber 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qapi/error.h" 13 #include "qemu/module.h" 14 #include "hw/cpu/arm11mpcore.h" 15 #include "hw/intc/realview_gic.h" 16 #include "hw/irq.h" 17 18 #define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore" 19 #define REALVIEW_MPCORE_RIRQ(obj) \ 20 OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ) 21 22 /* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ 23 controllers. The output of these, plus some of the raw input lines 24 are fed into a single SMP-aware interrupt controller on the CPU. */ 25 typedef struct { 26 SysBusDevice parent_obj; 27 28 qemu_irq cpuic[32]; 29 qemu_irq rvic[4][64]; 30 uint32_t num_cpu; 31 32 ARM11MPCorePriveState priv; 33 RealViewGICState gic[4]; 34 } mpcore_rirq_state; 35 36 /* Map baseboard IRQs onto CPU IRQ lines. */ 37 static const int mpcore_irq_map[32] = { 38 -1, -1, -1, -1, 1, 2, -1, -1, 39 -1, -1, 6, -1, 4, 5, -1, -1, 40 -1, 14, 15, 0, 7, 8, -1, -1, 41 -1, -1, -1, -1, 9, 3, -1, -1, 42 }; 43 44 static void mpcore_rirq_set_irq(void *opaque, int irq, int level) 45 { 46 mpcore_rirq_state *s = (mpcore_rirq_state *)opaque; 47 int i; 48 49 for (i = 0; i < 4; i++) { 50 qemu_set_irq(s->rvic[i][irq], level); 51 } 52 if (irq < 32) { 53 irq = mpcore_irq_map[irq]; 54 if (irq >= 0) { 55 qemu_set_irq(s->cpuic[irq], level); 56 } 57 } 58 } 59 60 static void realview_mpcore_realize(DeviceState *dev, Error **errp) 61 { 62 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 63 mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev); 64 DeviceState *priv = DEVICE(&s->priv); 65 DeviceState *gic; 66 SysBusDevice *gicbusdev; 67 Error *err = NULL; 68 int n; 69 int i; 70 71 qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); 72 object_property_set_bool(OBJECT(&s->priv), true, "realized", &err); 73 if (err != NULL) { 74 error_propagate(errp, err); 75 return; 76 } 77 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->priv)); 78 for (i = 0; i < 32; i++) { 79 s->cpuic[i] = qdev_get_gpio_in(priv, i); 80 } 81 /* ??? IRQ routing is hardcoded to "normal" mode. */ 82 for (n = 0; n < 4; n++) { 83 object_property_set_bool(OBJECT(&s->gic[n]), true, "realized", &err); 84 if (err != NULL) { 85 error_propagate(errp, err); 86 return; 87 } 88 gic = DEVICE(&s->gic[n]); 89 gicbusdev = SYS_BUS_DEVICE(&s->gic[n]); 90 sysbus_mmio_map(gicbusdev, 0, 0x10040000 + n * 0x10000); 91 sysbus_connect_irq(gicbusdev, 0, s->cpuic[10 + n]); 92 for (i = 0; i < 64; i++) { 93 s->rvic[n][i] = qdev_get_gpio_in(gic, i); 94 } 95 } 96 qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64); 97 } 98 99 static void mpcore_rirq_init(Object *obj) 100 { 101 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 102 mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(obj); 103 SysBusDevice *privbusdev; 104 int i; 105 106 sysbus_init_child_obj(obj, "a11priv", &s->priv, sizeof(s->priv), 107 TYPE_ARM11MPCORE_PRIV); 108 privbusdev = SYS_BUS_DEVICE(&s->priv); 109 sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0)); 110 111 for (i = 0; i < 4; i++) { 112 sysbus_init_child_obj(obj, "gic[*]", &s->gic[i], sizeof(s->gic[i]), 113 TYPE_REALVIEW_GIC); 114 } 115 } 116 117 static Property mpcore_rirq_properties[] = { 118 DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), 119 DEFINE_PROP_END_OF_LIST(), 120 }; 121 122 static void mpcore_rirq_class_init(ObjectClass *klass, void *data) 123 { 124 DeviceClass *dc = DEVICE_CLASS(klass); 125 126 dc->realize = realview_mpcore_realize; 127 dc->props = mpcore_rirq_properties; 128 } 129 130 static const TypeInfo mpcore_rirq_info = { 131 .name = TYPE_REALVIEW_MPCORE_RIRQ, 132 .parent = TYPE_SYS_BUS_DEVICE, 133 .instance_size = sizeof(mpcore_rirq_state), 134 .instance_init = mpcore_rirq_init, 135 .class_init = mpcore_rirq_class_init, 136 }; 137 138 static void realview_mpcore_register_types(void) 139 { 140 type_register_static(&mpcore_rirq_info); 141 } 142 143 type_init(realview_mpcore_register_types) 144