xref: /openbmc/qemu/hw/cpu/realview_mpcore.c (revision 354908ce)
1 /*
2  * RealView ARM11MPCore internal peripheral emulation
3  *
4  * Copyright (c) 2006-2007 CodeSourcery.
5  * Copyright (c) 2013 SUSE LINUX Products GmbH
6  * Written by Paul Brook and Andreas Färber
7  *
8  * This code is licensed under the GPL.
9  */
10 
11 #include "qemu/osdep.h"
12 #include "qapi/error.h"
13 #include "qemu/module.h"
14 #include "hw/cpu/arm11mpcore.h"
15 #include "hw/intc/realview_gic.h"
16 #include "hw/irq.h"
17 #include "hw/qdev-properties.h"
18 
19 #define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
20 #define REALVIEW_MPCORE_RIRQ(obj) \
21     OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ)
22 
23 /* Dummy PIC to route IRQ lines.  The baseboard has 4 independent IRQ
24    controllers.  The output of these, plus some of the raw input lines
25    are fed into a single SMP-aware interrupt controller on the CPU.  */
26 typedef struct {
27     SysBusDevice parent_obj;
28 
29     qemu_irq cpuic[32];
30     qemu_irq rvic[4][64];
31     uint32_t num_cpu;
32 
33     ARM11MPCorePriveState priv;
34     RealViewGICState gic[4];
35 } mpcore_rirq_state;
36 
37 /* Map baseboard IRQs onto CPU IRQ lines.  */
38 static const int mpcore_irq_map[32] = {
39     -1, -1, -1, -1,  1,  2, -1, -1,
40     -1, -1,  6, -1,  4,  5, -1, -1,
41     -1, 14, 15,  0,  7,  8, -1, -1,
42     -1, -1, -1, -1,  9,  3, -1, -1,
43 };
44 
45 static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
46 {
47     mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
48     int i;
49 
50     for (i = 0; i < 4; i++) {
51         qemu_set_irq(s->rvic[i][irq], level);
52     }
53     if (irq < 32) {
54         irq = mpcore_irq_map[irq];
55         if (irq >= 0) {
56             qemu_set_irq(s->cpuic[irq], level);
57         }
58     }
59 }
60 
61 static void realview_mpcore_realize(DeviceState *dev, Error **errp)
62 {
63     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
64     mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev);
65     DeviceState *priv = DEVICE(&s->priv);
66     DeviceState *gic;
67     SysBusDevice *gicbusdev;
68     Error *err = NULL;
69     int n;
70     int i;
71 
72     qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
73     sysbus_realize(SYS_BUS_DEVICE(&s->priv), &err);
74     if (err != NULL) {
75         error_propagate(errp, err);
76         return;
77     }
78     sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->priv));
79     for (i = 0; i < 32; i++) {
80         s->cpuic[i] = qdev_get_gpio_in(priv, i);
81     }
82     /* ??? IRQ routing is hardcoded to "normal" mode.  */
83     for (n = 0; n < 4; n++) {
84         sysbus_realize(SYS_BUS_DEVICE(&s->gic[n]), &err);
85         if (err != NULL) {
86             error_propagate(errp, err);
87             return;
88         }
89         gic = DEVICE(&s->gic[n]);
90         gicbusdev = SYS_BUS_DEVICE(&s->gic[n]);
91         sysbus_mmio_map(gicbusdev, 0, 0x10040000 + n * 0x10000);
92         sysbus_connect_irq(gicbusdev, 0, s->cpuic[10 + n]);
93         for (i = 0; i < 64; i++) {
94             s->rvic[n][i] = qdev_get_gpio_in(gic, i);
95         }
96     }
97     qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64);
98 }
99 
100 static void mpcore_rirq_init(Object *obj)
101 {
102     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
103     mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(obj);
104     SysBusDevice *privbusdev;
105     int i;
106 
107     object_initialize_child(obj, "a11priv", &s->priv, TYPE_ARM11MPCORE_PRIV);
108     privbusdev = SYS_BUS_DEVICE(&s->priv);
109     sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0));
110 
111     for (i = 0; i < 4; i++) {
112         object_initialize_child(obj, "gic[*]", &s->gic[i], TYPE_REALVIEW_GIC);
113     }
114 }
115 
116 static Property mpcore_rirq_properties[] = {
117     DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
118     DEFINE_PROP_END_OF_LIST(),
119 };
120 
121 static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
122 {
123     DeviceClass *dc = DEVICE_CLASS(klass);
124 
125     dc->realize = realview_mpcore_realize;
126     device_class_set_props(dc, mpcore_rirq_properties);
127 }
128 
129 static const TypeInfo mpcore_rirq_info = {
130     .name          = TYPE_REALVIEW_MPCORE_RIRQ,
131     .parent        = TYPE_SYS_BUS_DEVICE,
132     .instance_size = sizeof(mpcore_rirq_state),
133     .instance_init = mpcore_rirq_init,
134     .class_init    = mpcore_rirq_class_init,
135 };
136 
137 static void realview_mpcore_register_types(void)
138 {
139     type_register_static(&mpcore_rirq_info);
140 }
141 
142 type_init(realview_mpcore_register_types)
143