1 /* 2 * ARM11MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/cpu/arm11mpcore.h" 12 #include "hw/intc/realview_gic.h" 13 14 15 static void mpcore_priv_set_irq(void *opaque, int irq, int level) 16 { 17 ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; 18 19 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 20 } 21 22 static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) 23 { 24 int i; 25 SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu); 26 DeviceState *gicdev = DEVICE(&s->gic); 27 SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic); 28 SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer); 29 SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer); 30 31 memory_region_add_subregion(&s->container, 0, 32 sysbus_mmio_get_region(scubusdev, 0)); 33 /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs 34 * at 0x200, 0x300... 35 */ 36 for (i = 0; i < (s->num_cpu + 1); i++) { 37 hwaddr offset = 0x100 + (i * 0x100); 38 memory_region_add_subregion(&s->container, offset, 39 sysbus_mmio_get_region(gicbusdev, i + 1)); 40 } 41 /* Add the regions for timer and watchdog for "current CPU" and 42 * for each specific CPU. 43 */ 44 for (i = 0; i < (s->num_cpu + 1); i++) { 45 /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ 46 hwaddr offset = 0x600 + i * 0x100; 47 memory_region_add_subregion(&s->container, offset, 48 sysbus_mmio_get_region(timerbusdev, i)); 49 memory_region_add_subregion(&s->container, offset + 0x20, 50 sysbus_mmio_get_region(wdtbusdev, i)); 51 } 52 memory_region_add_subregion(&s->container, 0x1000, 53 sysbus_mmio_get_region(gicbusdev, 0)); 54 /* Wire up the interrupt from each watchdog and timer. 55 * For each core the timer is PPI 29 and the watchdog PPI 30. 56 */ 57 for (i = 0; i < s->num_cpu; i++) { 58 int ppibase = (s->num_irq - 32) + i * 32; 59 sysbus_connect_irq(timerbusdev, i, 60 qdev_get_gpio_in(gicdev, ppibase + 29)); 61 sysbus_connect_irq(wdtbusdev, i, 62 qdev_get_gpio_in(gicdev, ppibase + 30)); 63 } 64 } 65 66 static void mpcore_priv_realize(DeviceState *dev, Error **errp) 67 { 68 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 69 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev); 70 DeviceState *scudev = DEVICE(&s->scu); 71 DeviceState *gicdev = DEVICE(&s->gic); 72 DeviceState *mptimerdev = DEVICE(&s->mptimer); 73 DeviceState *wdtimerdev = DEVICE(&s->wdtimer); 74 Error *err = NULL; 75 76 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); 77 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); 78 if (err != NULL) { 79 error_propagate(errp, err); 80 return; 81 } 82 83 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); 84 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); 85 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 86 if (err != NULL) { 87 error_propagate(errp, err); 88 return; 89 } 90 91 /* Pass through outbound IRQ lines from the GIC */ 92 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic)); 93 94 /* Pass through inbound GPIO lines to the GIC */ 95 qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32); 96 97 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); 98 object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err); 99 if (err != NULL) { 100 error_propagate(errp, err); 101 return; 102 } 103 104 qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu); 105 object_property_set_bool(OBJECT(&s->wdtimer), true, "realized", &err); 106 if (err != NULL) { 107 error_propagate(errp, err); 108 return; 109 } 110 111 mpcore_priv_map_setup(s); 112 } 113 114 static void mpcore_priv_initfn(Object *obj) 115 { 116 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 117 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj); 118 119 memory_region_init(&s->container, OBJECT(s), 120 "mpcore-priv-container", 0x2000); 121 sysbus_init_mmio(sbd, &s->container); 122 123 object_initialize(&s->scu, sizeof(s->scu), TYPE_ARM11_SCU); 124 qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); 125 126 object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); 127 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 128 /* Request the legacy 11MPCore GIC behaviour: */ 129 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0); 130 131 object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER); 132 qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default()); 133 134 object_initialize(&s->wdtimer, sizeof(s->wdtimer), TYPE_ARM_MPTIMER); 135 qdev_set_parent_bus(DEVICE(&s->wdtimer), sysbus_get_default()); 136 } 137 138 static Property mpcore_priv_properties[] = { 139 DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), 140 /* The ARM11 MPCORE TRM says the on-chip controller may have 141 * anything from 0 to 224 external interrupt IRQ lines (with another 142 * 32 internal). We default to 32+32, which is the number provided by 143 * the ARM11 MPCore test chip in the Realview Versatile Express 144 * coretile. Other boards may differ and should set this property 145 * appropriately. Some Linux kernels may not boot if the hardware 146 * has more IRQ lines than the kernel expects. 147 */ 148 DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64), 149 DEFINE_PROP_END_OF_LIST(), 150 }; 151 152 static void mpcore_priv_class_init(ObjectClass *klass, void *data) 153 { 154 DeviceClass *dc = DEVICE_CLASS(klass); 155 156 dc->realize = mpcore_priv_realize; 157 dc->props = mpcore_priv_properties; 158 } 159 160 static const TypeInfo mpcore_priv_info = { 161 .name = TYPE_ARM11MPCORE_PRIV, 162 .parent = TYPE_SYS_BUS_DEVICE, 163 .instance_size = sizeof(ARM11MPCorePriveState), 164 .instance_init = mpcore_priv_initfn, 165 .class_init = mpcore_priv_class_init, 166 }; 167 168 static void arm11mpcore_register_types(void) 169 { 170 type_register_static(&mpcore_priv_info); 171 } 172 173 type_init(arm11mpcore_register_types) 174