1 /* 2 * ARM11MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "qemu/module.h" 13 #include "hw/cpu/arm11mpcore.h" 14 #include "hw/intc/realview_gic.h" 15 #include "hw/irq.h" 16 17 18 static void mpcore_priv_set_irq(void *opaque, int irq, int level) 19 { 20 ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; 21 22 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 23 } 24 25 static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) 26 { 27 int i; 28 SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu); 29 DeviceState *gicdev = DEVICE(&s->gic); 30 SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic); 31 SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer); 32 SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer); 33 34 memory_region_add_subregion(&s->container, 0, 35 sysbus_mmio_get_region(scubusdev, 0)); 36 /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs 37 * at 0x200, 0x300... 38 */ 39 for (i = 0; i < (s->num_cpu + 1); i++) { 40 hwaddr offset = 0x100 + (i * 0x100); 41 memory_region_add_subregion(&s->container, offset, 42 sysbus_mmio_get_region(gicbusdev, i + 1)); 43 } 44 /* Add the regions for timer and watchdog for "current CPU" and 45 * for each specific CPU. 46 */ 47 for (i = 0; i < (s->num_cpu + 1); i++) { 48 /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ 49 hwaddr offset = 0x600 + i * 0x100; 50 memory_region_add_subregion(&s->container, offset, 51 sysbus_mmio_get_region(timerbusdev, i)); 52 memory_region_add_subregion(&s->container, offset + 0x20, 53 sysbus_mmio_get_region(wdtbusdev, i)); 54 } 55 memory_region_add_subregion(&s->container, 0x1000, 56 sysbus_mmio_get_region(gicbusdev, 0)); 57 /* Wire up the interrupt from each watchdog and timer. 58 * For each core the timer is PPI 29 and the watchdog PPI 30. 59 */ 60 for (i = 0; i < s->num_cpu; i++) { 61 int ppibase = (s->num_irq - 32) + i * 32; 62 sysbus_connect_irq(timerbusdev, i, 63 qdev_get_gpio_in(gicdev, ppibase + 29)); 64 sysbus_connect_irq(wdtbusdev, i, 65 qdev_get_gpio_in(gicdev, ppibase + 30)); 66 } 67 } 68 69 static void mpcore_priv_realize(DeviceState *dev, Error **errp) 70 { 71 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 72 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev); 73 DeviceState *scudev = DEVICE(&s->scu); 74 DeviceState *gicdev = DEVICE(&s->gic); 75 DeviceState *mptimerdev = DEVICE(&s->mptimer); 76 DeviceState *wdtimerdev = DEVICE(&s->wdtimer); 77 Error *err = NULL; 78 79 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); 80 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); 81 if (err != NULL) { 82 error_propagate(errp, err); 83 return; 84 } 85 86 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); 87 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); 88 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 89 if (err != NULL) { 90 error_propagate(errp, err); 91 return; 92 } 93 94 /* Pass through outbound IRQ lines from the GIC */ 95 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic)); 96 97 /* Pass through inbound GPIO lines to the GIC */ 98 qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32); 99 100 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); 101 object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err); 102 if (err != NULL) { 103 error_propagate(errp, err); 104 return; 105 } 106 107 qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu); 108 object_property_set_bool(OBJECT(&s->wdtimer), true, "realized", &err); 109 if (err != NULL) { 110 error_propagate(errp, err); 111 return; 112 } 113 114 mpcore_priv_map_setup(s); 115 } 116 117 static void mpcore_priv_initfn(Object *obj) 118 { 119 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 120 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj); 121 122 memory_region_init(&s->container, OBJECT(s), 123 "mpcore-priv-container", 0x2000); 124 sysbus_init_mmio(sbd, &s->container); 125 126 sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), TYPE_ARM11_SCU); 127 128 sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), TYPE_ARM_GIC); 129 /* Request the legacy 11MPCore GIC behaviour: */ 130 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0); 131 132 sysbus_init_child_obj(obj, "mptimer", &s->mptimer, sizeof(s->mptimer), 133 TYPE_ARM_MPTIMER); 134 135 sysbus_init_child_obj(obj, "wdtimer", &s->wdtimer, sizeof(s->wdtimer), 136 TYPE_ARM_MPTIMER); 137 } 138 139 static Property mpcore_priv_properties[] = { 140 DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), 141 /* The ARM11 MPCORE TRM says the on-chip controller may have 142 * anything from 0 to 224 external interrupt IRQ lines (with another 143 * 32 internal). We default to 32+32, which is the number provided by 144 * the ARM11 MPCore test chip in the Realview Versatile Express 145 * coretile. Other boards may differ and should set this property 146 * appropriately. Some Linux kernels may not boot if the hardware 147 * has more IRQ lines than the kernel expects. 148 */ 149 DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64), 150 DEFINE_PROP_END_OF_LIST(), 151 }; 152 153 static void mpcore_priv_class_init(ObjectClass *klass, void *data) 154 { 155 DeviceClass *dc = DEVICE_CLASS(klass); 156 157 dc->realize = mpcore_priv_realize; 158 dc->props = mpcore_priv_properties; 159 } 160 161 static const TypeInfo mpcore_priv_info = { 162 .name = TYPE_ARM11MPCORE_PRIV, 163 .parent = TYPE_SYS_BUS_DEVICE, 164 .instance_size = sizeof(ARM11MPCorePriveState), 165 .instance_init = mpcore_priv_initfn, 166 .class_init = mpcore_priv_class_init, 167 }; 168 169 static void arm11mpcore_register_types(void) 170 { 171 type_register_static(&mpcore_priv_info); 172 } 173 174 type_init(arm11mpcore_register_types) 175