1 /* 2 * ARM11MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/misc/arm11scu.h" 12 #include "hw/intc/arm_gic.h" 13 #include "hw/timer/arm_mptimer.h" 14 #include "qemu/timer.h" 15 16 /* MPCore private memory region. */ 17 18 #define TYPE_ARM11MPCORE_PRIV "arm11mpcore_priv" 19 #define ARM11MPCORE_PRIV(obj) \ 20 OBJECT_CHECK(ARM11MPCorePriveState, (obj), TYPE_ARM11MPCORE_PRIV) 21 22 typedef struct ARM11MPCorePriveState { 23 SysBusDevice parent_obj; 24 25 uint32_t num_cpu; 26 MemoryRegion container; 27 uint32_t num_irq; 28 29 ARM11SCUState scu; 30 GICState gic; 31 ARMMPTimerState mptimer; 32 ARMMPTimerState wdtimer; 33 } ARM11MPCorePriveState; 34 35 /* Per-CPU private memory mapped IO. */ 36 37 38 static void mpcore_priv_set_irq(void *opaque, int irq, int level) 39 { 40 ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; 41 42 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 43 } 44 45 static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) 46 { 47 int i; 48 SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu); 49 DeviceState *gicdev = DEVICE(&s->gic); 50 SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic); 51 SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer); 52 SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer); 53 54 memory_region_add_subregion(&s->container, 0, 55 sysbus_mmio_get_region(scubusdev, 0)); 56 /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs 57 * at 0x200, 0x300... 58 */ 59 for (i = 0; i < (s->num_cpu + 1); i++) { 60 hwaddr offset = 0x100 + (i * 0x100); 61 memory_region_add_subregion(&s->container, offset, 62 sysbus_mmio_get_region(gicbusdev, i + 1)); 63 } 64 /* Add the regions for timer and watchdog for "current CPU" and 65 * for each specific CPU. 66 */ 67 for (i = 0; i < (s->num_cpu + 1); i++) { 68 /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ 69 hwaddr offset = 0x600 + i * 0x100; 70 memory_region_add_subregion(&s->container, offset, 71 sysbus_mmio_get_region(timerbusdev, i)); 72 memory_region_add_subregion(&s->container, offset + 0x20, 73 sysbus_mmio_get_region(wdtbusdev, i)); 74 } 75 memory_region_add_subregion(&s->container, 0x1000, 76 sysbus_mmio_get_region(gicbusdev, 0)); 77 /* Wire up the interrupt from each watchdog and timer. 78 * For each core the timer is PPI 29 and the watchdog PPI 30. 79 */ 80 for (i = 0; i < s->num_cpu; i++) { 81 int ppibase = (s->num_irq - 32) + i * 32; 82 sysbus_connect_irq(timerbusdev, i, 83 qdev_get_gpio_in(gicdev, ppibase + 29)); 84 sysbus_connect_irq(wdtbusdev, i, 85 qdev_get_gpio_in(gicdev, ppibase + 30)); 86 } 87 } 88 89 static void mpcore_priv_realize(DeviceState *dev, Error **errp) 90 { 91 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 92 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev); 93 DeviceState *scudev = DEVICE(&s->scu); 94 DeviceState *gicdev = DEVICE(&s->gic); 95 DeviceState *mptimerdev = DEVICE(&s->mptimer); 96 DeviceState *wdtimerdev = DEVICE(&s->wdtimer); 97 Error *err = NULL; 98 99 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); 100 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); 101 if (err != NULL) { 102 error_propagate(errp, err); 103 return; 104 } 105 106 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); 107 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); 108 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 109 if (err != NULL) { 110 error_propagate(errp, err); 111 return; 112 } 113 114 /* Pass through outbound IRQ lines from the GIC */ 115 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic)); 116 117 /* Pass through inbound GPIO lines to the GIC */ 118 qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32); 119 120 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); 121 object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err); 122 if (err != NULL) { 123 error_propagate(errp, err); 124 return; 125 } 126 127 qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu); 128 object_property_set_bool(OBJECT(&s->wdtimer), true, "realized", &err); 129 if (err != NULL) { 130 error_propagate(errp, err); 131 return; 132 } 133 134 mpcore_priv_map_setup(s); 135 } 136 137 static void mpcore_priv_initfn(Object *obj) 138 { 139 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 140 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj); 141 142 memory_region_init(&s->container, OBJECT(s), 143 "mpcore-priv-container", 0x2000); 144 sysbus_init_mmio(sbd, &s->container); 145 146 object_initialize(&s->scu, sizeof(s->scu), TYPE_ARM11_SCU); 147 qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); 148 149 object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); 150 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 151 /* Request the legacy 11MPCore GIC behaviour: */ 152 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0); 153 154 object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER); 155 qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default()); 156 157 object_initialize(&s->wdtimer, sizeof(s->wdtimer), TYPE_ARM_MPTIMER); 158 qdev_set_parent_bus(DEVICE(&s->wdtimer), sysbus_get_default()); 159 } 160 161 #define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore" 162 #define REALVIEW_MPCORE_RIRQ(obj) \ 163 OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ) 164 165 /* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ 166 controllers. The output of these, plus some of the raw input lines 167 are fed into a single SMP-aware interrupt controller on the CPU. */ 168 typedef struct { 169 SysBusDevice parent_obj; 170 171 SysBusDevice *priv; 172 qemu_irq cpuic[32]; 173 qemu_irq rvic[4][64]; 174 uint32_t num_cpu; 175 } mpcore_rirq_state; 176 177 /* Map baseboard IRQs onto CPU IRQ lines. */ 178 static const int mpcore_irq_map[32] = { 179 -1, -1, -1, -1, 1, 2, -1, -1, 180 -1, -1, 6, -1, 4, 5, -1, -1, 181 -1, 14, 15, 0, 7, 8, -1, -1, 182 -1, -1, -1, -1, 9, 3, -1, -1, 183 }; 184 185 static void mpcore_rirq_set_irq(void *opaque, int irq, int level) 186 { 187 mpcore_rirq_state *s = (mpcore_rirq_state *)opaque; 188 int i; 189 190 for (i = 0; i < 4; i++) { 191 qemu_set_irq(s->rvic[i][irq], level); 192 } 193 if (irq < 32) { 194 irq = mpcore_irq_map[irq]; 195 if (irq >= 0) { 196 qemu_set_irq(s->cpuic[irq], level); 197 } 198 } 199 } 200 201 static int realview_mpcore_init(SysBusDevice *sbd) 202 { 203 DeviceState *dev = DEVICE(sbd); 204 mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev); 205 DeviceState *gic; 206 DeviceState *priv; 207 int n; 208 int i; 209 210 priv = qdev_create(NULL, TYPE_ARM11MPCORE_PRIV); 211 qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); 212 qdev_init_nofail(priv); 213 s->priv = SYS_BUS_DEVICE(priv); 214 sysbus_pass_irq(sbd, s->priv); 215 for (i = 0; i < 32; i++) { 216 s->cpuic[i] = qdev_get_gpio_in(priv, i); 217 } 218 /* ??? IRQ routing is hardcoded to "normal" mode. */ 219 for (n = 0; n < 4; n++) { 220 gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000, 221 s->cpuic[10 + n]); 222 for (i = 0; i < 64; i++) { 223 s->rvic[n][i] = qdev_get_gpio_in(gic, i); 224 } 225 } 226 qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64); 227 sysbus_init_mmio(sbd, sysbus_mmio_get_region(s->priv, 0)); 228 return 0; 229 } 230 231 static Property mpcore_rirq_properties[] = { 232 DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), 233 DEFINE_PROP_END_OF_LIST(), 234 }; 235 236 static void mpcore_rirq_class_init(ObjectClass *klass, void *data) 237 { 238 DeviceClass *dc = DEVICE_CLASS(klass); 239 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 240 241 k->init = realview_mpcore_init; 242 dc->props = mpcore_rirq_properties; 243 } 244 245 static const TypeInfo mpcore_rirq_info = { 246 .name = TYPE_REALVIEW_MPCORE_RIRQ, 247 .parent = TYPE_SYS_BUS_DEVICE, 248 .instance_size = sizeof(mpcore_rirq_state), 249 .class_init = mpcore_rirq_class_init, 250 }; 251 252 static Property mpcore_priv_properties[] = { 253 DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), 254 /* The ARM11 MPCORE TRM says the on-chip controller may have 255 * anything from 0 to 224 external interrupt IRQ lines (with another 256 * 32 internal). We default to 32+32, which is the number provided by 257 * the ARM11 MPCore test chip in the Realview Versatile Express 258 * coretile. Other boards may differ and should set this property 259 * appropriately. Some Linux kernels may not boot if the hardware 260 * has more IRQ lines than the kernel expects. 261 */ 262 DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64), 263 DEFINE_PROP_END_OF_LIST(), 264 }; 265 266 static void mpcore_priv_class_init(ObjectClass *klass, void *data) 267 { 268 DeviceClass *dc = DEVICE_CLASS(klass); 269 270 dc->realize = mpcore_priv_realize; 271 dc->props = mpcore_priv_properties; 272 } 273 274 static const TypeInfo mpcore_priv_info = { 275 .name = TYPE_ARM11MPCORE_PRIV, 276 .parent = TYPE_SYS_BUS_DEVICE, 277 .instance_size = sizeof(ARM11MPCorePriveState), 278 .instance_init = mpcore_priv_initfn, 279 .class_init = mpcore_priv_class_init, 280 }; 281 282 static void arm11mpcore_register_types(void) 283 { 284 type_register_static(&mpcore_rirq_info); 285 type_register_static(&mpcore_priv_info); 286 } 287 288 type_init(arm11mpcore_register_types) 289