1 /* 2 * ARM11MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "qemu/module.h" 13 #include "hw/cpu/arm11mpcore.h" 14 #include "hw/intc/realview_gic.h" 15 16 17 static void mpcore_priv_set_irq(void *opaque, int irq, int level) 18 { 19 ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; 20 21 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 22 } 23 24 static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) 25 { 26 int i; 27 SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu); 28 DeviceState *gicdev = DEVICE(&s->gic); 29 SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic); 30 SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer); 31 SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer); 32 33 memory_region_add_subregion(&s->container, 0, 34 sysbus_mmio_get_region(scubusdev, 0)); 35 /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs 36 * at 0x200, 0x300... 37 */ 38 for (i = 0; i < (s->num_cpu + 1); i++) { 39 hwaddr offset = 0x100 + (i * 0x100); 40 memory_region_add_subregion(&s->container, offset, 41 sysbus_mmio_get_region(gicbusdev, i + 1)); 42 } 43 /* Add the regions for timer and watchdog for "current CPU" and 44 * for each specific CPU. 45 */ 46 for (i = 0; i < (s->num_cpu + 1); i++) { 47 /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ 48 hwaddr offset = 0x600 + i * 0x100; 49 memory_region_add_subregion(&s->container, offset, 50 sysbus_mmio_get_region(timerbusdev, i)); 51 memory_region_add_subregion(&s->container, offset + 0x20, 52 sysbus_mmio_get_region(wdtbusdev, i)); 53 } 54 memory_region_add_subregion(&s->container, 0x1000, 55 sysbus_mmio_get_region(gicbusdev, 0)); 56 /* Wire up the interrupt from each watchdog and timer. 57 * For each core the timer is PPI 29 and the watchdog PPI 30. 58 */ 59 for (i = 0; i < s->num_cpu; i++) { 60 int ppibase = (s->num_irq - 32) + i * 32; 61 sysbus_connect_irq(timerbusdev, i, 62 qdev_get_gpio_in(gicdev, ppibase + 29)); 63 sysbus_connect_irq(wdtbusdev, i, 64 qdev_get_gpio_in(gicdev, ppibase + 30)); 65 } 66 } 67 68 static void mpcore_priv_realize(DeviceState *dev, Error **errp) 69 { 70 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 71 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev); 72 DeviceState *scudev = DEVICE(&s->scu); 73 DeviceState *gicdev = DEVICE(&s->gic); 74 DeviceState *mptimerdev = DEVICE(&s->mptimer); 75 DeviceState *wdtimerdev = DEVICE(&s->wdtimer); 76 Error *err = NULL; 77 78 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); 79 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); 80 if (err != NULL) { 81 error_propagate(errp, err); 82 return; 83 } 84 85 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); 86 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); 87 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 88 if (err != NULL) { 89 error_propagate(errp, err); 90 return; 91 } 92 93 /* Pass through outbound IRQ lines from the GIC */ 94 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic)); 95 96 /* Pass through inbound GPIO lines to the GIC */ 97 qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32); 98 99 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); 100 object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err); 101 if (err != NULL) { 102 error_propagate(errp, err); 103 return; 104 } 105 106 qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu); 107 object_property_set_bool(OBJECT(&s->wdtimer), true, "realized", &err); 108 if (err != NULL) { 109 error_propagate(errp, err); 110 return; 111 } 112 113 mpcore_priv_map_setup(s); 114 } 115 116 static void mpcore_priv_initfn(Object *obj) 117 { 118 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 119 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj); 120 121 memory_region_init(&s->container, OBJECT(s), 122 "mpcore-priv-container", 0x2000); 123 sysbus_init_mmio(sbd, &s->container); 124 125 sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), TYPE_ARM11_SCU); 126 127 sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), TYPE_ARM_GIC); 128 /* Request the legacy 11MPCore GIC behaviour: */ 129 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0); 130 131 sysbus_init_child_obj(obj, "mptimer", &s->mptimer, sizeof(s->mptimer), 132 TYPE_ARM_MPTIMER); 133 134 sysbus_init_child_obj(obj, "wdtimer", &s->wdtimer, sizeof(s->wdtimer), 135 TYPE_ARM_MPTIMER); 136 } 137 138 static Property mpcore_priv_properties[] = { 139 DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), 140 /* The ARM11 MPCORE TRM says the on-chip controller may have 141 * anything from 0 to 224 external interrupt IRQ lines (with another 142 * 32 internal). We default to 32+32, which is the number provided by 143 * the ARM11 MPCore test chip in the Realview Versatile Express 144 * coretile. Other boards may differ and should set this property 145 * appropriately. Some Linux kernels may not boot if the hardware 146 * has more IRQ lines than the kernel expects. 147 */ 148 DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64), 149 DEFINE_PROP_END_OF_LIST(), 150 }; 151 152 static void mpcore_priv_class_init(ObjectClass *klass, void *data) 153 { 154 DeviceClass *dc = DEVICE_CLASS(klass); 155 156 dc->realize = mpcore_priv_realize; 157 dc->props = mpcore_priv_properties; 158 } 159 160 static const TypeInfo mpcore_priv_info = { 161 .name = TYPE_ARM11MPCORE_PRIV, 162 .parent = TYPE_SYS_BUS_DEVICE, 163 .instance_size = sizeof(ARM11MPCorePriveState), 164 .instance_init = mpcore_priv_initfn, 165 .class_init = mpcore_priv_class_init, 166 }; 167 168 static void arm11mpcore_register_types(void) 169 { 170 type_register_static(&mpcore_priv_info); 171 } 172 173 type_init(arm11mpcore_register_types) 174