1 /* 2 * Cortex-A9MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2009 CodeSourcery. 5 * Copyright (c) 2011 Linaro Limited. 6 * Written by Paul Brook, Peter Maydell. 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qapi/error.h" 13 #include "qemu/module.h" 14 #include "hw/cpu/a9mpcore.h" 15 #include "hw/irq.h" 16 #include "hw/qdev-properties.h" 17 #include "hw/core/cpu.h" 18 19 #define A9_GIC_NUM_PRIORITY_BITS 5 20 21 static void a9mp_priv_set_irq(void *opaque, int irq, int level) 22 { 23 A9MPPrivState *s = (A9MPPrivState *)opaque; 24 25 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 26 } 27 28 static void a9mp_priv_initfn(Object *obj) 29 { 30 A9MPPrivState *s = A9MPCORE_PRIV(obj); 31 32 memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); 33 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); 34 35 sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), TYPE_A9_SCU); 36 37 sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), TYPE_ARM_GIC); 38 39 sysbus_init_child_obj(obj, "gtimer", &s->gtimer, sizeof(s->gtimer), 40 TYPE_A9_GTIMER); 41 42 sysbus_init_child_obj(obj, "mptimer", &s->mptimer, sizeof(s->mptimer), 43 TYPE_ARM_MPTIMER); 44 45 sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), 46 TYPE_ARM_MPTIMER); 47 } 48 49 static void a9mp_priv_realize(DeviceState *dev, Error **errp) 50 { 51 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 52 A9MPPrivState *s = A9MPCORE_PRIV(dev); 53 DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev; 54 SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev, 55 *wdtbusdev; 56 Error *err = NULL; 57 int i; 58 bool has_el3; 59 Object *cpuobj; 60 61 scudev = DEVICE(&s->scu); 62 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); 63 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); 64 if (err != NULL) { 65 error_propagate(errp, err); 66 return; 67 } 68 scubusdev = SYS_BUS_DEVICE(&s->scu); 69 70 gicdev = DEVICE(&s->gic); 71 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); 72 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); 73 qdev_prop_set_uint32(gicdev, "num-priority-bits", 74 A9_GIC_NUM_PRIORITY_BITS); 75 76 /* Make the GIC's TZ support match the CPUs. We assume that 77 * either all the CPUs have TZ, or none do. 78 */ 79 cpuobj = OBJECT(qemu_get_cpu(0)); 80 has_el3 = object_property_find(cpuobj, "has_el3", NULL) && 81 object_property_get_bool(cpuobj, "has_el3", &error_abort); 82 qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); 83 84 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 85 if (err != NULL) { 86 error_propagate(errp, err); 87 return; 88 } 89 gicbusdev = SYS_BUS_DEVICE(&s->gic); 90 91 /* Pass through outbound IRQ lines from the GIC */ 92 sysbus_pass_irq(sbd, gicbusdev); 93 94 /* Pass through inbound GPIO lines to the GIC */ 95 qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32); 96 97 gtimerdev = DEVICE(&s->gtimer); 98 qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); 99 object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err); 100 if (err != NULL) { 101 error_propagate(errp, err); 102 return; 103 } 104 gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer); 105 106 mptimerdev = DEVICE(&s->mptimer); 107 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); 108 object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err); 109 if (err != NULL) { 110 error_propagate(errp, err); 111 return; 112 } 113 mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer); 114 115 wdtdev = DEVICE(&s->wdt); 116 qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); 117 object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err); 118 if (err != NULL) { 119 error_propagate(errp, err); 120 return; 121 } 122 wdtbusdev = SYS_BUS_DEVICE(&s->wdt); 123 124 /* Memory map (addresses are offsets from PERIPHBASE): 125 * 0x0000-0x00ff -- Snoop Control Unit 126 * 0x0100-0x01ff -- GIC CPU interface 127 * 0x0200-0x02ff -- Global Timer 128 * 0x0300-0x05ff -- nothing 129 * 0x0600-0x06ff -- private timers and watchdogs 130 * 0x0700-0x0fff -- nothing 131 * 0x1000-0x1fff -- GIC Distributor 132 */ 133 memory_region_add_subregion(&s->container, 0, 134 sysbus_mmio_get_region(scubusdev, 0)); 135 /* GIC CPU interface */ 136 memory_region_add_subregion(&s->container, 0x100, 137 sysbus_mmio_get_region(gicbusdev, 1)); 138 memory_region_add_subregion(&s->container, 0x200, 139 sysbus_mmio_get_region(gtimerbusdev, 0)); 140 /* Note that the A9 exposes only the "timer/watchdog for this core" 141 * memory region, not the "timer/watchdog for core X" ones 11MPcore has. 142 */ 143 memory_region_add_subregion(&s->container, 0x600, 144 sysbus_mmio_get_region(mptimerbusdev, 0)); 145 memory_region_add_subregion(&s->container, 0x620, 146 sysbus_mmio_get_region(wdtbusdev, 0)); 147 memory_region_add_subregion(&s->container, 0x1000, 148 sysbus_mmio_get_region(gicbusdev, 0)); 149 150 /* Wire up the interrupt from each watchdog and timer. 151 * For each core the global timer is PPI 27, the private 152 * timer is PPI 29 and the watchdog PPI 30. 153 */ 154 for (i = 0; i < s->num_cpu; i++) { 155 int ppibase = (s->num_irq - 32) + i * 32; 156 sysbus_connect_irq(gtimerbusdev, i, 157 qdev_get_gpio_in(gicdev, ppibase + 27)); 158 sysbus_connect_irq(mptimerbusdev, i, 159 qdev_get_gpio_in(gicdev, ppibase + 29)); 160 sysbus_connect_irq(wdtbusdev, i, 161 qdev_get_gpio_in(gicdev, ppibase + 30)); 162 } 163 } 164 165 static Property a9mp_priv_properties[] = { 166 DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), 167 /* The Cortex-A9MP may have anything from 0 to 224 external interrupt 168 * IRQ lines (with another 32 internal). We default to 64+32, which 169 * is the number provided by the Cortex-A9MP test chip in the 170 * Realview PBX-A9 and Versatile Express A9 development boards. 171 * Other boards may differ and should set this property appropriately. 172 */ 173 DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), 174 DEFINE_PROP_END_OF_LIST(), 175 }; 176 177 static void a9mp_priv_class_init(ObjectClass *klass, void *data) 178 { 179 DeviceClass *dc = DEVICE_CLASS(klass); 180 181 dc->realize = a9mp_priv_realize; 182 device_class_set_props(dc, a9mp_priv_properties); 183 } 184 185 static const TypeInfo a9mp_priv_info = { 186 .name = TYPE_A9MPCORE_PRIV, 187 .parent = TYPE_SYS_BUS_DEVICE, 188 .instance_size = sizeof(A9MPPrivState), 189 .instance_init = a9mp_priv_initfn, 190 .class_init = a9mp_priv_class_init, 191 }; 192 193 static void a9mp_register_types(void) 194 { 195 type_register_static(&a9mp_priv_info); 196 } 197 198 type_init(a9mp_register_types) 199