1 /* 2 * Cortex-A9MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2009 CodeSourcery. 5 * Copyright (c) 2011 Linaro Limited. 6 * Written by Paul Brook, Peter Maydell. 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qapi/error.h" 13 #include "hw/cpu/a9mpcore.h" 14 #include "qom/cpu.h" 15 16 static void a9mp_priv_set_irq(void *opaque, int irq, int level) 17 { 18 A9MPPrivState *s = (A9MPPrivState *)opaque; 19 20 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 21 } 22 23 static void a9mp_priv_initfn(Object *obj) 24 { 25 A9MPPrivState *s = A9MPCORE_PRIV(obj); 26 27 memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); 28 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); 29 30 object_initialize(&s->scu, sizeof(s->scu), TYPE_A9_SCU); 31 qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); 32 33 object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); 34 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 35 36 object_initialize(&s->gtimer, sizeof(s->gtimer), TYPE_A9_GTIMER); 37 qdev_set_parent_bus(DEVICE(&s->gtimer), sysbus_get_default()); 38 39 object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER); 40 qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default()); 41 42 object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ARM_MPTIMER); 43 qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default()); 44 } 45 46 static void a9mp_priv_realize(DeviceState *dev, Error **errp) 47 { 48 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 49 A9MPPrivState *s = A9MPCORE_PRIV(dev); 50 DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev; 51 SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev, 52 *wdtbusdev; 53 Error *err = NULL; 54 int i; 55 bool has_el3; 56 Object *cpuobj; 57 58 scudev = DEVICE(&s->scu); 59 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); 60 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); 61 if (err != NULL) { 62 error_propagate(errp, err); 63 return; 64 } 65 scubusdev = SYS_BUS_DEVICE(&s->scu); 66 67 gicdev = DEVICE(&s->gic); 68 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); 69 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); 70 71 /* Make the GIC's TZ support match the CPUs. We assume that 72 * either all the CPUs have TZ, or none do. 73 */ 74 cpuobj = OBJECT(qemu_get_cpu(0)); 75 has_el3 = object_property_find(cpuobj, "has_el3", NULL) && 76 object_property_get_bool(cpuobj, "has_el3", &error_abort); 77 qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); 78 79 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 80 if (err != NULL) { 81 error_propagate(errp, err); 82 return; 83 } 84 gicbusdev = SYS_BUS_DEVICE(&s->gic); 85 86 /* Pass through outbound IRQ lines from the GIC */ 87 sysbus_pass_irq(sbd, gicbusdev); 88 89 /* Pass through inbound GPIO lines to the GIC */ 90 qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32); 91 92 gtimerdev = DEVICE(&s->gtimer); 93 qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); 94 object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err); 95 if (err != NULL) { 96 error_propagate(errp, err); 97 return; 98 } 99 gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer); 100 101 mptimerdev = DEVICE(&s->mptimer); 102 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); 103 object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err); 104 if (err != NULL) { 105 error_propagate(errp, err); 106 return; 107 } 108 mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer); 109 110 wdtdev = DEVICE(&s->wdt); 111 qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); 112 object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err); 113 if (err != NULL) { 114 error_propagate(errp, err); 115 return; 116 } 117 wdtbusdev = SYS_BUS_DEVICE(&s->wdt); 118 119 /* Memory map (addresses are offsets from PERIPHBASE): 120 * 0x0000-0x00ff -- Snoop Control Unit 121 * 0x0100-0x01ff -- GIC CPU interface 122 * 0x0200-0x02ff -- Global Timer 123 * 0x0300-0x05ff -- nothing 124 * 0x0600-0x06ff -- private timers and watchdogs 125 * 0x0700-0x0fff -- nothing 126 * 0x1000-0x1fff -- GIC Distributor 127 */ 128 memory_region_add_subregion(&s->container, 0, 129 sysbus_mmio_get_region(scubusdev, 0)); 130 /* GIC CPU interface */ 131 memory_region_add_subregion(&s->container, 0x100, 132 sysbus_mmio_get_region(gicbusdev, 1)); 133 memory_region_add_subregion(&s->container, 0x200, 134 sysbus_mmio_get_region(gtimerbusdev, 0)); 135 /* Note that the A9 exposes only the "timer/watchdog for this core" 136 * memory region, not the "timer/watchdog for core X" ones 11MPcore has. 137 */ 138 memory_region_add_subregion(&s->container, 0x600, 139 sysbus_mmio_get_region(mptimerbusdev, 0)); 140 memory_region_add_subregion(&s->container, 0x620, 141 sysbus_mmio_get_region(wdtbusdev, 0)); 142 memory_region_add_subregion(&s->container, 0x1000, 143 sysbus_mmio_get_region(gicbusdev, 0)); 144 145 /* Wire up the interrupt from each watchdog and timer. 146 * For each core the global timer is PPI 27, the private 147 * timer is PPI 29 and the watchdog PPI 30. 148 */ 149 for (i = 0; i < s->num_cpu; i++) { 150 int ppibase = (s->num_irq - 32) + i * 32; 151 sysbus_connect_irq(gtimerbusdev, i, 152 qdev_get_gpio_in(gicdev, ppibase + 27)); 153 sysbus_connect_irq(mptimerbusdev, i, 154 qdev_get_gpio_in(gicdev, ppibase + 29)); 155 sysbus_connect_irq(wdtbusdev, i, 156 qdev_get_gpio_in(gicdev, ppibase + 30)); 157 } 158 } 159 160 static Property a9mp_priv_properties[] = { 161 DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), 162 /* The Cortex-A9MP may have anything from 0 to 224 external interrupt 163 * IRQ lines (with another 32 internal). We default to 64+32, which 164 * is the number provided by the Cortex-A9MP test chip in the 165 * Realview PBX-A9 and Versatile Express A9 development boards. 166 * Other boards may differ and should set this property appropriately. 167 */ 168 DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), 169 DEFINE_PROP_END_OF_LIST(), 170 }; 171 172 static void a9mp_priv_class_init(ObjectClass *klass, void *data) 173 { 174 DeviceClass *dc = DEVICE_CLASS(klass); 175 176 dc->realize = a9mp_priv_realize; 177 dc->props = a9mp_priv_properties; 178 } 179 180 static const TypeInfo a9mp_priv_info = { 181 .name = TYPE_A9MPCORE_PRIV, 182 .parent = TYPE_SYS_BUS_DEVICE, 183 .instance_size = sizeof(A9MPPrivState), 184 .instance_init = a9mp_priv_initfn, 185 .class_init = a9mp_priv_class_init, 186 }; 187 188 static void a9mp_register_types(void) 189 { 190 type_register_static(&a9mp_priv_info); 191 } 192 193 type_init(a9mp_register_types) 194