1 /* 2 * Cortex-A9MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2009 CodeSourcery. 5 * Copyright (c) 2011 Linaro Limited. 6 * Written by Paul Brook, Peter Maydell. 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "hw/cpu/a9mpcore.h" 12 13 static void a9mp_priv_set_irq(void *opaque, int irq, int level) 14 { 15 A9MPPrivState *s = (A9MPPrivState *)opaque; 16 17 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 18 } 19 20 static void a9mp_priv_initfn(Object *obj) 21 { 22 A9MPPrivState *s = A9MPCORE_PRIV(obj); 23 24 memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); 25 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); 26 27 object_initialize(&s->scu, sizeof(s->scu), TYPE_A9_SCU); 28 qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); 29 30 object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); 31 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 32 33 object_initialize(&s->gtimer, sizeof(s->gtimer), TYPE_A9_GTIMER); 34 qdev_set_parent_bus(DEVICE(&s->gtimer), sysbus_get_default()); 35 36 object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER); 37 qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default()); 38 39 object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ARM_MPTIMER); 40 qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default()); 41 } 42 43 static void a9mp_priv_realize(DeviceState *dev, Error **errp) 44 { 45 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 46 A9MPPrivState *s = A9MPCORE_PRIV(dev); 47 DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev; 48 SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev, 49 *wdtbusdev; 50 Error *err = NULL; 51 int i; 52 53 scudev = DEVICE(&s->scu); 54 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); 55 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); 56 if (err != NULL) { 57 error_propagate(errp, err); 58 return; 59 } 60 scubusdev = SYS_BUS_DEVICE(&s->scu); 61 62 gicdev = DEVICE(&s->gic); 63 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); 64 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); 65 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 66 if (err != NULL) { 67 error_propagate(errp, err); 68 return; 69 } 70 gicbusdev = SYS_BUS_DEVICE(&s->gic); 71 72 /* Pass through outbound IRQ lines from the GIC */ 73 sysbus_pass_irq(sbd, gicbusdev); 74 75 /* Pass through inbound GPIO lines to the GIC */ 76 qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32); 77 78 gtimerdev = DEVICE(&s->gtimer); 79 qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); 80 object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err); 81 if (err != NULL) { 82 error_propagate(errp, err); 83 return; 84 } 85 gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer); 86 87 mptimerdev = DEVICE(&s->mptimer); 88 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); 89 object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err); 90 if (err != NULL) { 91 error_propagate(errp, err); 92 return; 93 } 94 mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer); 95 96 wdtdev = DEVICE(&s->wdt); 97 qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); 98 object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err); 99 if (err != NULL) { 100 error_propagate(errp, err); 101 return; 102 } 103 wdtbusdev = SYS_BUS_DEVICE(&s->wdt); 104 105 /* Memory map (addresses are offsets from PERIPHBASE): 106 * 0x0000-0x00ff -- Snoop Control Unit 107 * 0x0100-0x01ff -- GIC CPU interface 108 * 0x0200-0x02ff -- Global Timer 109 * 0x0300-0x05ff -- nothing 110 * 0x0600-0x06ff -- private timers and watchdogs 111 * 0x0700-0x0fff -- nothing 112 * 0x1000-0x1fff -- GIC Distributor 113 */ 114 memory_region_add_subregion(&s->container, 0, 115 sysbus_mmio_get_region(scubusdev, 0)); 116 /* GIC CPU interface */ 117 memory_region_add_subregion(&s->container, 0x100, 118 sysbus_mmio_get_region(gicbusdev, 1)); 119 memory_region_add_subregion(&s->container, 0x200, 120 sysbus_mmio_get_region(gtimerbusdev, 0)); 121 /* Note that the A9 exposes only the "timer/watchdog for this core" 122 * memory region, not the "timer/watchdog for core X" ones 11MPcore has. 123 */ 124 memory_region_add_subregion(&s->container, 0x600, 125 sysbus_mmio_get_region(mptimerbusdev, 0)); 126 memory_region_add_subregion(&s->container, 0x620, 127 sysbus_mmio_get_region(wdtbusdev, 0)); 128 memory_region_add_subregion(&s->container, 0x1000, 129 sysbus_mmio_get_region(gicbusdev, 0)); 130 131 /* Wire up the interrupt from each watchdog and timer. 132 * For each core the global timer is PPI 27, the private 133 * timer is PPI 29 and the watchdog PPI 30. 134 */ 135 for (i = 0; i < s->num_cpu; i++) { 136 int ppibase = (s->num_irq - 32) + i * 32; 137 sysbus_connect_irq(gtimerbusdev, i, 138 qdev_get_gpio_in(gicdev, ppibase + 27)); 139 sysbus_connect_irq(mptimerbusdev, i, 140 qdev_get_gpio_in(gicdev, ppibase + 29)); 141 sysbus_connect_irq(wdtbusdev, i, 142 qdev_get_gpio_in(gicdev, ppibase + 30)); 143 } 144 } 145 146 static Property a9mp_priv_properties[] = { 147 DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), 148 /* The Cortex-A9MP may have anything from 0 to 224 external interrupt 149 * IRQ lines (with another 32 internal). We default to 64+32, which 150 * is the number provided by the Cortex-A9MP test chip in the 151 * Realview PBX-A9 and Versatile Express A9 development boards. 152 * Other boards may differ and should set this property appropriately. 153 */ 154 DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), 155 DEFINE_PROP_END_OF_LIST(), 156 }; 157 158 static void a9mp_priv_class_init(ObjectClass *klass, void *data) 159 { 160 DeviceClass *dc = DEVICE_CLASS(klass); 161 162 dc->realize = a9mp_priv_realize; 163 dc->props = a9mp_priv_properties; 164 } 165 166 static const TypeInfo a9mp_priv_info = { 167 .name = TYPE_A9MPCORE_PRIV, 168 .parent = TYPE_SYS_BUS_DEVICE, 169 .instance_size = sizeof(A9MPPrivState), 170 .instance_init = a9mp_priv_initfn, 171 .class_init = a9mp_priv_class_init, 172 }; 173 174 static void a9mp_register_types(void) 175 { 176 type_register_static(&a9mp_priv_info); 177 } 178 179 type_init(a9mp_register_types) 180