1 /* 2 * Cortex-A9MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2009 CodeSourcery. 5 * Copyright (c) 2011 Linaro Limited. 6 * Written by Paul Brook, Peter Maydell. 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qapi/error.h" 13 #include "qemu/module.h" 14 #include "hw/cpu/a9mpcore.h" 15 #include "hw/irq.h" 16 #include "hw/qdev-properties.h" 17 #include "hw/core/cpu.h" 18 19 #define A9_GIC_NUM_PRIORITY_BITS 5 20 21 static void a9mp_priv_set_irq(void *opaque, int irq, int level) 22 { 23 A9MPPrivState *s = (A9MPPrivState *)opaque; 24 25 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 26 } 27 28 static void a9mp_priv_initfn(Object *obj) 29 { 30 A9MPPrivState *s = A9MPCORE_PRIV(obj); 31 32 memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); 33 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); 34 35 object_initialize_child(obj, "scu", &s->scu, TYPE_A9_SCU); 36 37 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); 38 39 object_initialize_child(obj, "gtimer", &s->gtimer, TYPE_A9_GTIMER); 40 41 object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER); 42 43 object_initialize_child(obj, "wdt", &s->wdt, TYPE_ARM_MPTIMER); 44 } 45 46 static void a9mp_priv_realize(DeviceState *dev, Error **errp) 47 { 48 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 49 A9MPPrivState *s = A9MPCORE_PRIV(dev); 50 DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev; 51 SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev, 52 *wdtbusdev; 53 Error *err = NULL; 54 int i; 55 bool has_el3; 56 Object *cpuobj; 57 58 scudev = DEVICE(&s->scu); 59 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); 60 sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err); 61 if (err != NULL) { 62 error_propagate(errp, err); 63 return; 64 } 65 scubusdev = SYS_BUS_DEVICE(&s->scu); 66 67 gicdev = DEVICE(&s->gic); 68 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); 69 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); 70 qdev_prop_set_uint32(gicdev, "num-priority-bits", 71 A9_GIC_NUM_PRIORITY_BITS); 72 73 /* Make the GIC's TZ support match the CPUs. We assume that 74 * either all the CPUs have TZ, or none do. 75 */ 76 cpuobj = OBJECT(qemu_get_cpu(0)); 77 has_el3 = object_property_find(cpuobj, "has_el3", NULL) && 78 object_property_get_bool(cpuobj, "has_el3", &error_abort); 79 qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); 80 81 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err); 82 if (err != NULL) { 83 error_propagate(errp, err); 84 return; 85 } 86 gicbusdev = SYS_BUS_DEVICE(&s->gic); 87 88 /* Pass through outbound IRQ lines from the GIC */ 89 sysbus_pass_irq(sbd, gicbusdev); 90 91 /* Pass through inbound GPIO lines to the GIC */ 92 qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32); 93 94 gtimerdev = DEVICE(&s->gtimer); 95 qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); 96 sysbus_realize(SYS_BUS_DEVICE(&s->gtimer), &err); 97 if (err != NULL) { 98 error_propagate(errp, err); 99 return; 100 } 101 gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer); 102 103 mptimerdev = DEVICE(&s->mptimer); 104 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); 105 sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), &err); 106 if (err != NULL) { 107 error_propagate(errp, err); 108 return; 109 } 110 mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer); 111 112 wdtdev = DEVICE(&s->wdt); 113 qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); 114 sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &err); 115 if (err != NULL) { 116 error_propagate(errp, err); 117 return; 118 } 119 wdtbusdev = SYS_BUS_DEVICE(&s->wdt); 120 121 /* Memory map (addresses are offsets from PERIPHBASE): 122 * 0x0000-0x00ff -- Snoop Control Unit 123 * 0x0100-0x01ff -- GIC CPU interface 124 * 0x0200-0x02ff -- Global Timer 125 * 0x0300-0x05ff -- nothing 126 * 0x0600-0x06ff -- private timers and watchdogs 127 * 0x0700-0x0fff -- nothing 128 * 0x1000-0x1fff -- GIC Distributor 129 */ 130 memory_region_add_subregion(&s->container, 0, 131 sysbus_mmio_get_region(scubusdev, 0)); 132 /* GIC CPU interface */ 133 memory_region_add_subregion(&s->container, 0x100, 134 sysbus_mmio_get_region(gicbusdev, 1)); 135 memory_region_add_subregion(&s->container, 0x200, 136 sysbus_mmio_get_region(gtimerbusdev, 0)); 137 /* Note that the A9 exposes only the "timer/watchdog for this core" 138 * memory region, not the "timer/watchdog for core X" ones 11MPcore has. 139 */ 140 memory_region_add_subregion(&s->container, 0x600, 141 sysbus_mmio_get_region(mptimerbusdev, 0)); 142 memory_region_add_subregion(&s->container, 0x620, 143 sysbus_mmio_get_region(wdtbusdev, 0)); 144 memory_region_add_subregion(&s->container, 0x1000, 145 sysbus_mmio_get_region(gicbusdev, 0)); 146 147 /* Wire up the interrupt from each watchdog and timer. 148 * For each core the global timer is PPI 27, the private 149 * timer is PPI 29 and the watchdog PPI 30. 150 */ 151 for (i = 0; i < s->num_cpu; i++) { 152 int ppibase = (s->num_irq - 32) + i * 32; 153 sysbus_connect_irq(gtimerbusdev, i, 154 qdev_get_gpio_in(gicdev, ppibase + 27)); 155 sysbus_connect_irq(mptimerbusdev, i, 156 qdev_get_gpio_in(gicdev, ppibase + 29)); 157 sysbus_connect_irq(wdtbusdev, i, 158 qdev_get_gpio_in(gicdev, ppibase + 30)); 159 } 160 } 161 162 static Property a9mp_priv_properties[] = { 163 DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), 164 /* The Cortex-A9MP may have anything from 0 to 224 external interrupt 165 * IRQ lines (with another 32 internal). We default to 64+32, which 166 * is the number provided by the Cortex-A9MP test chip in the 167 * Realview PBX-A9 and Versatile Express A9 development boards. 168 * Other boards may differ and should set this property appropriately. 169 */ 170 DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), 171 DEFINE_PROP_END_OF_LIST(), 172 }; 173 174 static void a9mp_priv_class_init(ObjectClass *klass, void *data) 175 { 176 DeviceClass *dc = DEVICE_CLASS(klass); 177 178 dc->realize = a9mp_priv_realize; 179 device_class_set_props(dc, a9mp_priv_properties); 180 } 181 182 static const TypeInfo a9mp_priv_info = { 183 .name = TYPE_A9MPCORE_PRIV, 184 .parent = TYPE_SYS_BUS_DEVICE, 185 .instance_size = sizeof(A9MPPrivState), 186 .instance_init = a9mp_priv_initfn, 187 .class_init = a9mp_priv_class_init, 188 }; 189 190 static void a9mp_register_types(void) 191 { 192 type_register_static(&a9mp_priv_info); 193 } 194 195 type_init(a9mp_register_types) 196