1 /* 2 * Cortex-A9MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2009 CodeSourcery. 5 * Copyright (c) 2011 Linaro Limited. 6 * Written by Paul Brook, Peter Maydell. 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "hw/sysbus.h" 12 13 #define TYPE_A9MPCORE_PRIV "a9mpcore_priv" 14 #define A9MPCORE_PRIV(obj) \ 15 OBJECT_CHECK(A9MPPrivState, (obj), TYPE_A9MPCORE_PRIV) 16 17 typedef struct A9MPPrivState { 18 /*< private >*/ 19 SysBusDevice parent_obj; 20 /*< public >*/ 21 22 uint32_t num_cpu; 23 MemoryRegion container; 24 DeviceState *mptimer; 25 DeviceState *wdt; 26 DeviceState *gic; 27 DeviceState *scu; 28 uint32_t num_irq; 29 } A9MPPrivState; 30 31 static void a9mp_priv_set_irq(void *opaque, int irq, int level) 32 { 33 A9MPPrivState *s = (A9MPPrivState *)opaque; 34 qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); 35 } 36 37 static void a9mp_priv_initfn(Object *obj) 38 { 39 A9MPPrivState *s = A9MPCORE_PRIV(obj); 40 41 memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); 42 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); 43 } 44 45 static int a9mp_priv_init(SysBusDevice *dev) 46 { 47 A9MPPrivState *s = A9MPCORE_PRIV(dev); 48 SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev; 49 int i; 50 51 s->gic = qdev_create(NULL, "arm_gic"); 52 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); 53 qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); 54 qdev_init_nofail(s->gic); 55 gicbusdev = SYS_BUS_DEVICE(s->gic); 56 57 /* Pass through outbound IRQ lines from the GIC */ 58 sysbus_pass_irq(dev, gicbusdev); 59 60 /* Pass through inbound GPIO lines to the GIC */ 61 qdev_init_gpio_in(DEVICE(dev), a9mp_priv_set_irq, s->num_irq - 32); 62 63 s->scu = qdev_create(NULL, "a9-scu"); 64 qdev_prop_set_uint32(s->scu, "num-cpu", s->num_cpu); 65 qdev_init_nofail(s->scu); 66 scubusdev = SYS_BUS_DEVICE(s->scu); 67 68 s->mptimer = qdev_create(NULL, "arm_mptimer"); 69 qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); 70 qdev_init_nofail(s->mptimer); 71 timerbusdev = SYS_BUS_DEVICE(s->mptimer); 72 73 s->wdt = qdev_create(NULL, "arm_mptimer"); 74 qdev_prop_set_uint32(s->wdt, "num-cpu", s->num_cpu); 75 qdev_init_nofail(s->wdt); 76 wdtbusdev = SYS_BUS_DEVICE(s->wdt); 77 78 /* Memory map (addresses are offsets from PERIPHBASE): 79 * 0x0000-0x00ff -- Snoop Control Unit 80 * 0x0100-0x01ff -- GIC CPU interface 81 * 0x0200-0x02ff -- Global Timer 82 * 0x0300-0x05ff -- nothing 83 * 0x0600-0x06ff -- private timers and watchdogs 84 * 0x0700-0x0fff -- nothing 85 * 0x1000-0x1fff -- GIC Distributor 86 * 87 * We should implement the global timer but don't currently do so. 88 */ 89 memory_region_add_subregion(&s->container, 0, 90 sysbus_mmio_get_region(scubusdev, 0)); 91 /* GIC CPU interface */ 92 memory_region_add_subregion(&s->container, 0x100, 93 sysbus_mmio_get_region(gicbusdev, 1)); 94 /* Note that the A9 exposes only the "timer/watchdog for this core" 95 * memory region, not the "timer/watchdog for core X" ones 11MPcore has. 96 */ 97 memory_region_add_subregion(&s->container, 0x600, 98 sysbus_mmio_get_region(timerbusdev, 0)); 99 memory_region_add_subregion(&s->container, 0x620, 100 sysbus_mmio_get_region(wdtbusdev, 0)); 101 memory_region_add_subregion(&s->container, 0x1000, 102 sysbus_mmio_get_region(gicbusdev, 0)); 103 104 /* Wire up the interrupt from each watchdog and timer. 105 * For each core the timer is PPI 29 and the watchdog PPI 30. 106 */ 107 for (i = 0; i < s->num_cpu; i++) { 108 int ppibase = (s->num_irq - 32) + i * 32; 109 sysbus_connect_irq(timerbusdev, i, 110 qdev_get_gpio_in(s->gic, ppibase + 29)); 111 sysbus_connect_irq(wdtbusdev, i, 112 qdev_get_gpio_in(s->gic, ppibase + 30)); 113 } 114 return 0; 115 } 116 117 static Property a9mp_priv_properties[] = { 118 DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), 119 /* The Cortex-A9MP may have anything from 0 to 224 external interrupt 120 * IRQ lines (with another 32 internal). We default to 64+32, which 121 * is the number provided by the Cortex-A9MP test chip in the 122 * Realview PBX-A9 and Versatile Express A9 development boards. 123 * Other boards may differ and should set this property appropriately. 124 */ 125 DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), 126 DEFINE_PROP_END_OF_LIST(), 127 }; 128 129 static void a9mp_priv_class_init(ObjectClass *klass, void *data) 130 { 131 DeviceClass *dc = DEVICE_CLASS(klass); 132 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 133 134 k->init = a9mp_priv_init; 135 dc->props = a9mp_priv_properties; 136 } 137 138 static const TypeInfo a9mp_priv_info = { 139 .name = TYPE_A9MPCORE_PRIV, 140 .parent = TYPE_SYS_BUS_DEVICE, 141 .instance_size = sizeof(A9MPPrivState), 142 .instance_init = a9mp_priv_initfn, 143 .class_init = a9mp_priv_class_init, 144 }; 145 146 static void a9mp_register_types(void) 147 { 148 type_register_static(&a9mp_priv_info); 149 } 150 151 type_init(a9mp_register_types) 152