1 /* 2 * Cortex-A9MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2009 CodeSourcery. 5 * Copyright (c) 2011 Linaro Limited. 6 * Written by Paul Brook, Peter Maydell. 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qapi/error.h" 13 #include "qemu/module.h" 14 #include "hw/cpu/a9mpcore.h" 15 #include "hw/irq.h" 16 #include "hw/qdev-properties.h" 17 #include "hw/core/cpu.h" 18 19 #define A9_GIC_NUM_PRIORITY_BITS 5 20 21 static void a9mp_priv_set_irq(void *opaque, int irq, int level) 22 { 23 A9MPPrivState *s = (A9MPPrivState *)opaque; 24 25 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 26 } 27 28 static void a9mp_priv_initfn(Object *obj) 29 { 30 A9MPPrivState *s = A9MPCORE_PRIV(obj); 31 32 memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); 33 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); 34 35 object_initialize_child(obj, "scu", &s->scu, TYPE_A9_SCU); 36 37 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); 38 39 object_initialize_child(obj, "gtimer", &s->gtimer, TYPE_A9_GTIMER); 40 41 object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER); 42 43 object_initialize_child(obj, "wdt", &s->wdt, TYPE_ARM_MPTIMER); 44 } 45 46 static void a9mp_priv_realize(DeviceState *dev, Error **errp) 47 { 48 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 49 A9MPPrivState *s = A9MPCORE_PRIV(dev); 50 DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev; 51 SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev, 52 *wdtbusdev; 53 int i; 54 bool has_el3; 55 Object *cpuobj; 56 57 scudev = DEVICE(&s->scu); 58 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); 59 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 60 return; 61 } 62 scubusdev = SYS_BUS_DEVICE(&s->scu); 63 64 gicdev = DEVICE(&s->gic); 65 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); 66 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); 67 qdev_prop_set_uint32(gicdev, "num-priority-bits", 68 A9_GIC_NUM_PRIORITY_BITS); 69 70 /* Make the GIC's TZ support match the CPUs. We assume that 71 * either all the CPUs have TZ, or none do. 72 */ 73 cpuobj = OBJECT(qemu_get_cpu(0)); 74 has_el3 = object_property_find(cpuobj, "has_el3", NULL) && 75 object_property_get_bool(cpuobj, "has_el3", &error_abort); 76 qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); 77 78 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { 79 return; 80 } 81 gicbusdev = SYS_BUS_DEVICE(&s->gic); 82 83 /* Pass through outbound IRQ lines from the GIC */ 84 sysbus_pass_irq(sbd, gicbusdev); 85 86 /* Pass through inbound GPIO lines to the GIC */ 87 qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32); 88 89 gtimerdev = DEVICE(&s->gtimer); 90 qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); 91 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gtimer), errp)) { 92 return; 93 } 94 gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer); 95 96 mptimerdev = DEVICE(&s->mptimer); 97 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); 98 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), errp)) { 99 return; 100 } 101 mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer); 102 103 wdtdev = DEVICE(&s->wdt); 104 qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); 105 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt), errp)) { 106 return; 107 } 108 wdtbusdev = SYS_BUS_DEVICE(&s->wdt); 109 110 /* Memory map (addresses are offsets from PERIPHBASE): 111 * 0x0000-0x00ff -- Snoop Control Unit 112 * 0x0100-0x01ff -- GIC CPU interface 113 * 0x0200-0x02ff -- Global Timer 114 * 0x0300-0x05ff -- nothing 115 * 0x0600-0x06ff -- private timers and watchdogs 116 * 0x0700-0x0fff -- nothing 117 * 0x1000-0x1fff -- GIC Distributor 118 */ 119 memory_region_add_subregion(&s->container, 0, 120 sysbus_mmio_get_region(scubusdev, 0)); 121 /* GIC CPU interface */ 122 memory_region_add_subregion(&s->container, 0x100, 123 sysbus_mmio_get_region(gicbusdev, 1)); 124 memory_region_add_subregion(&s->container, 0x200, 125 sysbus_mmio_get_region(gtimerbusdev, 0)); 126 /* Note that the A9 exposes only the "timer/watchdog for this core" 127 * memory region, not the "timer/watchdog for core X" ones 11MPcore has. 128 */ 129 memory_region_add_subregion(&s->container, 0x600, 130 sysbus_mmio_get_region(mptimerbusdev, 0)); 131 memory_region_add_subregion(&s->container, 0x620, 132 sysbus_mmio_get_region(wdtbusdev, 0)); 133 memory_region_add_subregion(&s->container, 0x1000, 134 sysbus_mmio_get_region(gicbusdev, 0)); 135 136 /* Wire up the interrupt from each watchdog and timer. 137 * For each core the global timer is PPI 27, the private 138 * timer is PPI 29 and the watchdog PPI 30. 139 */ 140 for (i = 0; i < s->num_cpu; i++) { 141 int ppibase = (s->num_irq - 32) + i * 32; 142 sysbus_connect_irq(gtimerbusdev, i, 143 qdev_get_gpio_in(gicdev, ppibase + 27)); 144 sysbus_connect_irq(mptimerbusdev, i, 145 qdev_get_gpio_in(gicdev, ppibase + 29)); 146 sysbus_connect_irq(wdtbusdev, i, 147 qdev_get_gpio_in(gicdev, ppibase + 30)); 148 } 149 } 150 151 static Property a9mp_priv_properties[] = { 152 DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), 153 /* The Cortex-A9MP may have anything from 0 to 224 external interrupt 154 * IRQ lines (with another 32 internal). We default to 64+32, which 155 * is the number provided by the Cortex-A9MP test chip in the 156 * Realview PBX-A9 and Versatile Express A9 development boards. 157 * Other boards may differ and should set this property appropriately. 158 */ 159 DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), 160 DEFINE_PROP_END_OF_LIST(), 161 }; 162 163 static void a9mp_priv_class_init(ObjectClass *klass, void *data) 164 { 165 DeviceClass *dc = DEVICE_CLASS(klass); 166 167 dc->realize = a9mp_priv_realize; 168 device_class_set_props(dc, a9mp_priv_properties); 169 } 170 171 static const TypeInfo a9mp_priv_info = { 172 .name = TYPE_A9MPCORE_PRIV, 173 .parent = TYPE_SYS_BUS_DEVICE, 174 .instance_size = sizeof(A9MPPrivState), 175 .instance_init = a9mp_priv_initfn, 176 .class_init = a9mp_priv_class_init, 177 }; 178 179 static void a9mp_register_types(void) 180 { 181 type_register_static(&a9mp_priv_info); 182 } 183 184 type_init(a9mp_register_types) 185