1 /* 2 * Cortex-A9MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2009 CodeSourcery. 5 * Copyright (c) 2011 Linaro Limited. 6 * Written by Paul Brook, Peter Maydell. 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "hw/sysbus.h" 12 13 typedef struct A9MPPrivState { 14 SysBusDevice busdev; 15 uint32_t num_cpu; 16 MemoryRegion container; 17 DeviceState *mptimer; 18 DeviceState *wdt; 19 DeviceState *gic; 20 DeviceState *scu; 21 uint32_t num_irq; 22 } A9MPPrivState; 23 24 static void a9mp_priv_set_irq(void *opaque, int irq, int level) 25 { 26 A9MPPrivState *s = (A9MPPrivState *)opaque; 27 qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); 28 } 29 30 static int a9mp_priv_init(SysBusDevice *dev) 31 { 32 A9MPPrivState *s = FROM_SYSBUS(A9MPPrivState, dev); 33 SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev; 34 int i; 35 36 s->gic = qdev_create(NULL, "arm_gic"); 37 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); 38 qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); 39 qdev_init_nofail(s->gic); 40 gicbusdev = SYS_BUS_DEVICE(s->gic); 41 42 /* Pass through outbound IRQ lines from the GIC */ 43 sysbus_pass_irq(dev, gicbusdev); 44 45 /* Pass through inbound GPIO lines to the GIC */ 46 qdev_init_gpio_in(&s->busdev.qdev, a9mp_priv_set_irq, s->num_irq - 32); 47 48 s->scu = qdev_create(NULL, "a9-scu"); 49 qdev_prop_set_uint32(s->scu, "num-cpu", s->num_cpu); 50 qdev_init_nofail(s->scu); 51 scubusdev = SYS_BUS_DEVICE(s->scu); 52 53 s->mptimer = qdev_create(NULL, "arm_mptimer"); 54 qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); 55 qdev_init_nofail(s->mptimer); 56 timerbusdev = SYS_BUS_DEVICE(s->mptimer); 57 58 s->wdt = qdev_create(NULL, "arm_mptimer"); 59 qdev_prop_set_uint32(s->wdt, "num-cpu", s->num_cpu); 60 qdev_init_nofail(s->wdt); 61 wdtbusdev = SYS_BUS_DEVICE(s->wdt); 62 63 /* Memory map (addresses are offsets from PERIPHBASE): 64 * 0x0000-0x00ff -- Snoop Control Unit 65 * 0x0100-0x01ff -- GIC CPU interface 66 * 0x0200-0x02ff -- Global Timer 67 * 0x0300-0x05ff -- nothing 68 * 0x0600-0x06ff -- private timers and watchdogs 69 * 0x0700-0x0fff -- nothing 70 * 0x1000-0x1fff -- GIC Distributor 71 * 72 * We should implement the global timer but don't currently do so. 73 */ 74 memory_region_init(&s->container, "a9mp-priv-container", 0x2000); 75 memory_region_add_subregion(&s->container, 0, 76 sysbus_mmio_get_region(scubusdev, 0)); 77 /* GIC CPU interface */ 78 memory_region_add_subregion(&s->container, 0x100, 79 sysbus_mmio_get_region(gicbusdev, 1)); 80 /* Note that the A9 exposes only the "timer/watchdog for this core" 81 * memory region, not the "timer/watchdog for core X" ones 11MPcore has. 82 */ 83 memory_region_add_subregion(&s->container, 0x600, 84 sysbus_mmio_get_region(timerbusdev, 0)); 85 memory_region_add_subregion(&s->container, 0x620, 86 sysbus_mmio_get_region(wdtbusdev, 0)); 87 memory_region_add_subregion(&s->container, 0x1000, 88 sysbus_mmio_get_region(gicbusdev, 0)); 89 90 sysbus_init_mmio(dev, &s->container); 91 92 /* Wire up the interrupt from each watchdog and timer. 93 * For each core the timer is PPI 29 and the watchdog PPI 30. 94 */ 95 for (i = 0; i < s->num_cpu; i++) { 96 int ppibase = (s->num_irq - 32) + i * 32; 97 sysbus_connect_irq(timerbusdev, i, 98 qdev_get_gpio_in(s->gic, ppibase + 29)); 99 sysbus_connect_irq(wdtbusdev, i, 100 qdev_get_gpio_in(s->gic, ppibase + 30)); 101 } 102 return 0; 103 } 104 105 static Property a9mp_priv_properties[] = { 106 DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), 107 /* The Cortex-A9MP may have anything from 0 to 224 external interrupt 108 * IRQ lines (with another 32 internal). We default to 64+32, which 109 * is the number provided by the Cortex-A9MP test chip in the 110 * Realview PBX-A9 and Versatile Express A9 development boards. 111 * Other boards may differ and should set this property appropriately. 112 */ 113 DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), 114 DEFINE_PROP_END_OF_LIST(), 115 }; 116 117 static void a9mp_priv_class_init(ObjectClass *klass, void *data) 118 { 119 DeviceClass *dc = DEVICE_CLASS(klass); 120 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 121 122 k->init = a9mp_priv_init; 123 dc->props = a9mp_priv_properties; 124 } 125 126 static const TypeInfo a9mp_priv_info = { 127 .name = "a9mpcore_priv", 128 .parent = TYPE_SYS_BUS_DEVICE, 129 .instance_size = sizeof(A9MPPrivState), 130 .class_init = a9mp_priv_class_init, 131 }; 132 133 static void a9mp_register_types(void) 134 { 135 type_register_static(&a9mp_priv_info); 136 } 137 138 type_init(a9mp_register_types) 139