10434e30aSPaolo Bonzini /* 20434e30aSPaolo Bonzini * Cortex-A9MPCore internal peripheral emulation. 30434e30aSPaolo Bonzini * 40434e30aSPaolo Bonzini * Copyright (c) 2009 CodeSourcery. 50434e30aSPaolo Bonzini * Copyright (c) 2011 Linaro Limited. 60434e30aSPaolo Bonzini * Written by Paul Brook, Peter Maydell. 70434e30aSPaolo Bonzini * 80434e30aSPaolo Bonzini * This code is licensed under the GPL. 90434e30aSPaolo Bonzini */ 100434e30aSPaolo Bonzini 1117b7f2dbSPeter Maydell #include "qemu/osdep.h" 12da34e65cSMarkus Armbruster #include "qapi/error.h" 130b8fa32fSMarkus Armbruster #include "qemu/module.h" 14de4c2dcfSAndreas Färber #include "hw/cpu/a9mpcore.h" 1564552b6bSMarkus Armbruster #include "hw/irq.h" 16a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 172e5b09fdSMarkus Armbruster #include "hw/core/cpu.h" 188cbd4616SPhilippe Mathieu-Daudé #include "cpu.h" 190434e30aSPaolo Bonzini 20b3df30adSSai Pavan Boddu #define A9_GIC_NUM_PRIORITY_BITS 5 21b3df30adSSai Pavan Boddu 220434e30aSPaolo Bonzini static void a9mp_priv_set_irq(void *opaque, int irq, int level) 230434e30aSPaolo Bonzini { 240434e30aSPaolo Bonzini A9MPPrivState *s = (A9MPPrivState *)opaque; 259b5f952bSAndreas Färber 269b5f952bSAndreas Färber qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 270434e30aSPaolo Bonzini } 280434e30aSPaolo Bonzini 29753bc6e9SAndreas Färber static void a9mp_priv_initfn(Object *obj) 30753bc6e9SAndreas Färber { 31753bc6e9SAndreas Färber A9MPPrivState *s = A9MPCORE_PRIV(obj); 32753bc6e9SAndreas Färber 33753bc6e9SAndreas Färber memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); 34753bc6e9SAndreas Färber sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); 359b5f952bSAndreas Färber 36db873cc5SMarkus Armbruster object_initialize_child(obj, "scu", &s->scu, TYPE_A9_SCU); 37eb110bd8SAndreas Färber 38db873cc5SMarkus Armbruster object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); 394c25f365SPeter Crosthwaite 40db873cc5SMarkus Armbruster object_initialize_child(obj, "gtimer", &s->gtimer, TYPE_A9_GTIMER); 4157e72f2aSFrançois LEGAL 42db873cc5SMarkus Armbruster object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER); 43eb110bd8SAndreas Färber 44db873cc5SMarkus Armbruster object_initialize_child(obj, "wdt", &s->wdt, TYPE_ARM_MPTIMER); 45753bc6e9SAndreas Färber } 46753bc6e9SAndreas Färber 47837cf101SAndreas Färber static void a9mp_priv_realize(DeviceState *dev, Error **errp) 480434e30aSPaolo Bonzini { 49837cf101SAndreas Färber SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 505126fec7SAndreas Färber A9MPPrivState *s = A9MPCORE_PRIV(dev); 5157e72f2aSFrançois LEGAL DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev; 5257e72f2aSFrançois LEGAL SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev, 5357e72f2aSFrançois LEGAL *wdtbusdev; 540434e30aSPaolo Bonzini int i; 554182bbb1SPeter Maydell bool has_el3; 568cbd4616SPhilippe Mathieu-Daudé CPUState *cpu0; 574182bbb1SPeter Maydell Object *cpuobj; 580434e30aSPaolo Bonzini 598cbd4616SPhilippe Mathieu-Daudé cpu0 = qemu_get_cpu(0); 608cbd4616SPhilippe Mathieu-Daudé cpuobj = OBJECT(cpu0); 618cbd4616SPhilippe Mathieu-Daudé if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9"))) { 628cbd4616SPhilippe Mathieu-Daudé /* We might allow Cortex-A5 once we model it */ 638cbd4616SPhilippe Mathieu-Daudé error_setg(errp, 648cbd4616SPhilippe Mathieu-Daudé "Cortex-A9MPCore peripheral can only use Cortex-A9 CPU"); 658cbd4616SPhilippe Mathieu-Daudé return; 668cbd4616SPhilippe Mathieu-Daudé } 678cbd4616SPhilippe Mathieu-Daudé 684c25f365SPeter Crosthwaite scudev = DEVICE(&s->scu); 694c25f365SPeter Crosthwaite qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); 70668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 714c25f365SPeter Crosthwaite return; 724c25f365SPeter Crosthwaite } 734c25f365SPeter Crosthwaite scubusdev = SYS_BUS_DEVICE(&s->scu); 744c25f365SPeter Crosthwaite 759b5f952bSAndreas Färber gicdev = DEVICE(&s->gic); 769b5f952bSAndreas Färber qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); 779b5f952bSAndreas Färber qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); 78b3df30adSSai Pavan Boddu qdev_prop_set_uint32(gicdev, "num-priority-bits", 79b3df30adSSai Pavan Boddu A9_GIC_NUM_PRIORITY_BITS); 804182bbb1SPeter Maydell 814182bbb1SPeter Maydell /* Make the GIC's TZ support match the CPUs. We assume that 824182bbb1SPeter Maydell * either all the CPUs have TZ, or none do. 834182bbb1SPeter Maydell */ 84*efba1595SDaniel P. Berrangé has_el3 = object_property_find(cpuobj, "has_el3") && 854182bbb1SPeter Maydell object_property_get_bool(cpuobj, "has_el3", &error_abort); 864182bbb1SPeter Maydell qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); 874182bbb1SPeter Maydell 88668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { 89837cf101SAndreas Färber return; 90837cf101SAndreas Färber } 919b5f952bSAndreas Färber gicbusdev = SYS_BUS_DEVICE(&s->gic); 920434e30aSPaolo Bonzini 930434e30aSPaolo Bonzini /* Pass through outbound IRQ lines from the GIC */ 94837cf101SAndreas Färber sysbus_pass_irq(sbd, gicbusdev); 950434e30aSPaolo Bonzini 960434e30aSPaolo Bonzini /* Pass through inbound GPIO lines to the GIC */ 97837cf101SAndreas Färber qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32); 980434e30aSPaolo Bonzini 9957e72f2aSFrançois LEGAL gtimerdev = DEVICE(&s->gtimer); 10057e72f2aSFrançois LEGAL qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); 101668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->gtimer), errp)) { 10257e72f2aSFrançois LEGAL return; 10357e72f2aSFrançois LEGAL } 10457e72f2aSFrançois LEGAL gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer); 10557e72f2aSFrançois LEGAL 106eb110bd8SAndreas Färber mptimerdev = DEVICE(&s->mptimer); 107eb110bd8SAndreas Färber qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); 108668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), errp)) { 109837cf101SAndreas Färber return; 110837cf101SAndreas Färber } 111d3053e6bSPeter Crosthwaite mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer); 1120434e30aSPaolo Bonzini 113eb110bd8SAndreas Färber wdtdev = DEVICE(&s->wdt); 114eb110bd8SAndreas Färber qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); 115668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt), errp)) { 116837cf101SAndreas Färber return; 117837cf101SAndreas Färber } 118eb110bd8SAndreas Färber wdtbusdev = SYS_BUS_DEVICE(&s->wdt); 1190434e30aSPaolo Bonzini 1200434e30aSPaolo Bonzini /* Memory map (addresses are offsets from PERIPHBASE): 1210434e30aSPaolo Bonzini * 0x0000-0x00ff -- Snoop Control Unit 1220434e30aSPaolo Bonzini * 0x0100-0x01ff -- GIC CPU interface 1230434e30aSPaolo Bonzini * 0x0200-0x02ff -- Global Timer 1240434e30aSPaolo Bonzini * 0x0300-0x05ff -- nothing 1250434e30aSPaolo Bonzini * 0x0600-0x06ff -- private timers and watchdogs 1260434e30aSPaolo Bonzini * 0x0700-0x0fff -- nothing 1270434e30aSPaolo Bonzini * 0x1000-0x1fff -- GIC Distributor 1280434e30aSPaolo Bonzini */ 1290434e30aSPaolo Bonzini memory_region_add_subregion(&s->container, 0, 1300434e30aSPaolo Bonzini sysbus_mmio_get_region(scubusdev, 0)); 1310434e30aSPaolo Bonzini /* GIC CPU interface */ 1320434e30aSPaolo Bonzini memory_region_add_subregion(&s->container, 0x100, 1330434e30aSPaolo Bonzini sysbus_mmio_get_region(gicbusdev, 1)); 13457e72f2aSFrançois LEGAL memory_region_add_subregion(&s->container, 0x200, 13557e72f2aSFrançois LEGAL sysbus_mmio_get_region(gtimerbusdev, 0)); 1360434e30aSPaolo Bonzini /* Note that the A9 exposes only the "timer/watchdog for this core" 1370434e30aSPaolo Bonzini * memory region, not the "timer/watchdog for core X" ones 11MPcore has. 1380434e30aSPaolo Bonzini */ 1390434e30aSPaolo Bonzini memory_region_add_subregion(&s->container, 0x600, 140d3053e6bSPeter Crosthwaite sysbus_mmio_get_region(mptimerbusdev, 0)); 1410434e30aSPaolo Bonzini memory_region_add_subregion(&s->container, 0x620, 1420434e30aSPaolo Bonzini sysbus_mmio_get_region(wdtbusdev, 0)); 1430434e30aSPaolo Bonzini memory_region_add_subregion(&s->container, 0x1000, 1440434e30aSPaolo Bonzini sysbus_mmio_get_region(gicbusdev, 0)); 1450434e30aSPaolo Bonzini 1460434e30aSPaolo Bonzini /* Wire up the interrupt from each watchdog and timer. 14757e72f2aSFrançois LEGAL * For each core the global timer is PPI 27, the private 14857e72f2aSFrançois LEGAL * timer is PPI 29 and the watchdog PPI 30. 1490434e30aSPaolo Bonzini */ 1500434e30aSPaolo Bonzini for (i = 0; i < s->num_cpu; i++) { 1510434e30aSPaolo Bonzini int ppibase = (s->num_irq - 32) + i * 32; 15257e72f2aSFrançois LEGAL sysbus_connect_irq(gtimerbusdev, i, 15357e72f2aSFrançois LEGAL qdev_get_gpio_in(gicdev, ppibase + 27)); 154d3053e6bSPeter Crosthwaite sysbus_connect_irq(mptimerbusdev, i, 1559b5f952bSAndreas Färber qdev_get_gpio_in(gicdev, ppibase + 29)); 1560434e30aSPaolo Bonzini sysbus_connect_irq(wdtbusdev, i, 1579b5f952bSAndreas Färber qdev_get_gpio_in(gicdev, ppibase + 30)); 1580434e30aSPaolo Bonzini } 1590434e30aSPaolo Bonzini } 1600434e30aSPaolo Bonzini 1610434e30aSPaolo Bonzini static Property a9mp_priv_properties[] = { 1620434e30aSPaolo Bonzini DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), 1630434e30aSPaolo Bonzini /* The Cortex-A9MP may have anything from 0 to 224 external interrupt 1640434e30aSPaolo Bonzini * IRQ lines (with another 32 internal). We default to 64+32, which 1650434e30aSPaolo Bonzini * is the number provided by the Cortex-A9MP test chip in the 1660434e30aSPaolo Bonzini * Realview PBX-A9 and Versatile Express A9 development boards. 1670434e30aSPaolo Bonzini * Other boards may differ and should set this property appropriately. 1680434e30aSPaolo Bonzini */ 1690434e30aSPaolo Bonzini DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), 1700434e30aSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 1710434e30aSPaolo Bonzini }; 1720434e30aSPaolo Bonzini 1730434e30aSPaolo Bonzini static void a9mp_priv_class_init(ObjectClass *klass, void *data) 1740434e30aSPaolo Bonzini { 1750434e30aSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 1760434e30aSPaolo Bonzini 177837cf101SAndreas Färber dc->realize = a9mp_priv_realize; 1784f67d30bSMarc-André Lureau device_class_set_props(dc, a9mp_priv_properties); 1790434e30aSPaolo Bonzini } 1800434e30aSPaolo Bonzini 1810434e30aSPaolo Bonzini static const TypeInfo a9mp_priv_info = { 1825126fec7SAndreas Färber .name = TYPE_A9MPCORE_PRIV, 1830434e30aSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 1840434e30aSPaolo Bonzini .instance_size = sizeof(A9MPPrivState), 185753bc6e9SAndreas Färber .instance_init = a9mp_priv_initfn, 1860434e30aSPaolo Bonzini .class_init = a9mp_priv_class_init, 1870434e30aSPaolo Bonzini }; 1880434e30aSPaolo Bonzini 1890434e30aSPaolo Bonzini static void a9mp_register_types(void) 1900434e30aSPaolo Bonzini { 1910434e30aSPaolo Bonzini type_register_static(&a9mp_priv_info); 1920434e30aSPaolo Bonzini } 1930434e30aSPaolo Bonzini 1940434e30aSPaolo Bonzini type_init(a9mp_register_types) 195