10434e30aSPaolo Bonzini /* 20434e30aSPaolo Bonzini * Cortex-A9MPCore internal peripheral emulation. 30434e30aSPaolo Bonzini * 40434e30aSPaolo Bonzini * Copyright (c) 2009 CodeSourcery. 50434e30aSPaolo Bonzini * Copyright (c) 2011 Linaro Limited. 60434e30aSPaolo Bonzini * Written by Paul Brook, Peter Maydell. 70434e30aSPaolo Bonzini * 80434e30aSPaolo Bonzini * This code is licensed under the GPL. 90434e30aSPaolo Bonzini */ 100434e30aSPaolo Bonzini 1117b7f2dbSPeter Maydell #include "qemu/osdep.h" 12da34e65cSMarkus Armbruster #include "qapi/error.h" 130b8fa32fSMarkus Armbruster #include "qemu/module.h" 14de4c2dcfSAndreas Färber #include "hw/cpu/a9mpcore.h" 1564552b6bSMarkus Armbruster #include "hw/irq.h" 16a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 172e5b09fdSMarkus Armbruster #include "hw/core/cpu.h" 180434e30aSPaolo Bonzini 19*b3df30adSSai Pavan Boddu #define A9_GIC_NUM_PRIORITY_BITS 5 20*b3df30adSSai Pavan Boddu 210434e30aSPaolo Bonzini static void a9mp_priv_set_irq(void *opaque, int irq, int level) 220434e30aSPaolo Bonzini { 230434e30aSPaolo Bonzini A9MPPrivState *s = (A9MPPrivState *)opaque; 249b5f952bSAndreas Färber 259b5f952bSAndreas Färber qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 260434e30aSPaolo Bonzini } 270434e30aSPaolo Bonzini 28753bc6e9SAndreas Färber static void a9mp_priv_initfn(Object *obj) 29753bc6e9SAndreas Färber { 30753bc6e9SAndreas Färber A9MPPrivState *s = A9MPCORE_PRIV(obj); 31753bc6e9SAndreas Färber 32753bc6e9SAndreas Färber memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); 33753bc6e9SAndreas Färber sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); 349b5f952bSAndreas Färber 352ba486e7SThomas Huth sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), TYPE_A9_SCU); 36eb110bd8SAndreas Färber 372ba486e7SThomas Huth sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), TYPE_ARM_GIC); 384c25f365SPeter Crosthwaite 392ba486e7SThomas Huth sysbus_init_child_obj(obj, "gtimer", &s->gtimer, sizeof(s->gtimer), 402ba486e7SThomas Huth TYPE_A9_GTIMER); 4157e72f2aSFrançois LEGAL 422ba486e7SThomas Huth sysbus_init_child_obj(obj, "mptimer", &s->mptimer, sizeof(s->mptimer), 432ba486e7SThomas Huth TYPE_ARM_MPTIMER); 44eb110bd8SAndreas Färber 452ba486e7SThomas Huth sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), 462ba486e7SThomas Huth TYPE_ARM_MPTIMER); 47753bc6e9SAndreas Färber } 48753bc6e9SAndreas Färber 49837cf101SAndreas Färber static void a9mp_priv_realize(DeviceState *dev, Error **errp) 500434e30aSPaolo Bonzini { 51837cf101SAndreas Färber SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 525126fec7SAndreas Färber A9MPPrivState *s = A9MPCORE_PRIV(dev); 5357e72f2aSFrançois LEGAL DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev; 5457e72f2aSFrançois LEGAL SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev, 5557e72f2aSFrançois LEGAL *wdtbusdev; 56837cf101SAndreas Färber Error *err = NULL; 570434e30aSPaolo Bonzini int i; 584182bbb1SPeter Maydell bool has_el3; 594182bbb1SPeter Maydell Object *cpuobj; 600434e30aSPaolo Bonzini 614c25f365SPeter Crosthwaite scudev = DEVICE(&s->scu); 624c25f365SPeter Crosthwaite qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); 634c25f365SPeter Crosthwaite object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); 644c25f365SPeter Crosthwaite if (err != NULL) { 654c25f365SPeter Crosthwaite error_propagate(errp, err); 664c25f365SPeter Crosthwaite return; 674c25f365SPeter Crosthwaite } 684c25f365SPeter Crosthwaite scubusdev = SYS_BUS_DEVICE(&s->scu); 694c25f365SPeter Crosthwaite 709b5f952bSAndreas Färber gicdev = DEVICE(&s->gic); 719b5f952bSAndreas Färber qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); 729b5f952bSAndreas Färber qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); 73*b3df30adSSai Pavan Boddu qdev_prop_set_uint32(gicdev, "num-priority-bits", 74*b3df30adSSai Pavan Boddu A9_GIC_NUM_PRIORITY_BITS); 754182bbb1SPeter Maydell 764182bbb1SPeter Maydell /* Make the GIC's TZ support match the CPUs. We assume that 774182bbb1SPeter Maydell * either all the CPUs have TZ, or none do. 784182bbb1SPeter Maydell */ 794182bbb1SPeter Maydell cpuobj = OBJECT(qemu_get_cpu(0)); 806533a1fcSEdgar E. Iglesias has_el3 = object_property_find(cpuobj, "has_el3", NULL) && 814182bbb1SPeter Maydell object_property_get_bool(cpuobj, "has_el3", &error_abort); 824182bbb1SPeter Maydell qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); 834182bbb1SPeter Maydell 84837cf101SAndreas Färber object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 85837cf101SAndreas Färber if (err != NULL) { 86837cf101SAndreas Färber error_propagate(errp, err); 87837cf101SAndreas Färber return; 88837cf101SAndreas Färber } 899b5f952bSAndreas Färber gicbusdev = SYS_BUS_DEVICE(&s->gic); 900434e30aSPaolo Bonzini 910434e30aSPaolo Bonzini /* Pass through outbound IRQ lines from the GIC */ 92837cf101SAndreas Färber sysbus_pass_irq(sbd, gicbusdev); 930434e30aSPaolo Bonzini 940434e30aSPaolo Bonzini /* Pass through inbound GPIO lines to the GIC */ 95837cf101SAndreas Färber qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32); 960434e30aSPaolo Bonzini 9757e72f2aSFrançois LEGAL gtimerdev = DEVICE(&s->gtimer); 9857e72f2aSFrançois LEGAL qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); 9957e72f2aSFrançois LEGAL object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err); 10057e72f2aSFrançois LEGAL if (err != NULL) { 10157e72f2aSFrançois LEGAL error_propagate(errp, err); 10257e72f2aSFrançois LEGAL return; 10357e72f2aSFrançois LEGAL } 10457e72f2aSFrançois LEGAL gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer); 10557e72f2aSFrançois LEGAL 106eb110bd8SAndreas Färber mptimerdev = DEVICE(&s->mptimer); 107eb110bd8SAndreas Färber qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); 108837cf101SAndreas Färber object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err); 109837cf101SAndreas Färber if (err != NULL) { 110837cf101SAndreas Färber error_propagate(errp, err); 111837cf101SAndreas Färber return; 112837cf101SAndreas Färber } 113d3053e6bSPeter Crosthwaite mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer); 1140434e30aSPaolo Bonzini 115eb110bd8SAndreas Färber wdtdev = DEVICE(&s->wdt); 116eb110bd8SAndreas Färber qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); 117837cf101SAndreas Färber object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err); 118837cf101SAndreas Färber if (err != NULL) { 119837cf101SAndreas Färber error_propagate(errp, err); 120837cf101SAndreas Färber return; 121837cf101SAndreas Färber } 122eb110bd8SAndreas Färber wdtbusdev = SYS_BUS_DEVICE(&s->wdt); 1230434e30aSPaolo Bonzini 1240434e30aSPaolo Bonzini /* Memory map (addresses are offsets from PERIPHBASE): 1250434e30aSPaolo Bonzini * 0x0000-0x00ff -- Snoop Control Unit 1260434e30aSPaolo Bonzini * 0x0100-0x01ff -- GIC CPU interface 1270434e30aSPaolo Bonzini * 0x0200-0x02ff -- Global Timer 1280434e30aSPaolo Bonzini * 0x0300-0x05ff -- nothing 1290434e30aSPaolo Bonzini * 0x0600-0x06ff -- private timers and watchdogs 1300434e30aSPaolo Bonzini * 0x0700-0x0fff -- nothing 1310434e30aSPaolo Bonzini * 0x1000-0x1fff -- GIC Distributor 1320434e30aSPaolo Bonzini */ 1330434e30aSPaolo Bonzini memory_region_add_subregion(&s->container, 0, 1340434e30aSPaolo Bonzini sysbus_mmio_get_region(scubusdev, 0)); 1350434e30aSPaolo Bonzini /* GIC CPU interface */ 1360434e30aSPaolo Bonzini memory_region_add_subregion(&s->container, 0x100, 1370434e30aSPaolo Bonzini sysbus_mmio_get_region(gicbusdev, 1)); 13857e72f2aSFrançois LEGAL memory_region_add_subregion(&s->container, 0x200, 13957e72f2aSFrançois LEGAL sysbus_mmio_get_region(gtimerbusdev, 0)); 1400434e30aSPaolo Bonzini /* Note that the A9 exposes only the "timer/watchdog for this core" 1410434e30aSPaolo Bonzini * memory region, not the "timer/watchdog for core X" ones 11MPcore has. 1420434e30aSPaolo Bonzini */ 1430434e30aSPaolo Bonzini memory_region_add_subregion(&s->container, 0x600, 144d3053e6bSPeter Crosthwaite sysbus_mmio_get_region(mptimerbusdev, 0)); 1450434e30aSPaolo Bonzini memory_region_add_subregion(&s->container, 0x620, 1460434e30aSPaolo Bonzini sysbus_mmio_get_region(wdtbusdev, 0)); 1470434e30aSPaolo Bonzini memory_region_add_subregion(&s->container, 0x1000, 1480434e30aSPaolo Bonzini sysbus_mmio_get_region(gicbusdev, 0)); 1490434e30aSPaolo Bonzini 1500434e30aSPaolo Bonzini /* Wire up the interrupt from each watchdog and timer. 15157e72f2aSFrançois LEGAL * For each core the global timer is PPI 27, the private 15257e72f2aSFrançois LEGAL * timer is PPI 29 and the watchdog PPI 30. 1530434e30aSPaolo Bonzini */ 1540434e30aSPaolo Bonzini for (i = 0; i < s->num_cpu; i++) { 1550434e30aSPaolo Bonzini int ppibase = (s->num_irq - 32) + i * 32; 15657e72f2aSFrançois LEGAL sysbus_connect_irq(gtimerbusdev, i, 15757e72f2aSFrançois LEGAL qdev_get_gpio_in(gicdev, ppibase + 27)); 158d3053e6bSPeter Crosthwaite sysbus_connect_irq(mptimerbusdev, i, 1599b5f952bSAndreas Färber qdev_get_gpio_in(gicdev, ppibase + 29)); 1600434e30aSPaolo Bonzini sysbus_connect_irq(wdtbusdev, i, 1619b5f952bSAndreas Färber qdev_get_gpio_in(gicdev, ppibase + 30)); 1620434e30aSPaolo Bonzini } 1630434e30aSPaolo Bonzini } 1640434e30aSPaolo Bonzini 1650434e30aSPaolo Bonzini static Property a9mp_priv_properties[] = { 1660434e30aSPaolo Bonzini DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), 1670434e30aSPaolo Bonzini /* The Cortex-A9MP may have anything from 0 to 224 external interrupt 1680434e30aSPaolo Bonzini * IRQ lines (with another 32 internal). We default to 64+32, which 1690434e30aSPaolo Bonzini * is the number provided by the Cortex-A9MP test chip in the 1700434e30aSPaolo Bonzini * Realview PBX-A9 and Versatile Express A9 development boards. 1710434e30aSPaolo Bonzini * Other boards may differ and should set this property appropriately. 1720434e30aSPaolo Bonzini */ 1730434e30aSPaolo Bonzini DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), 1740434e30aSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 1750434e30aSPaolo Bonzini }; 1760434e30aSPaolo Bonzini 1770434e30aSPaolo Bonzini static void a9mp_priv_class_init(ObjectClass *klass, void *data) 1780434e30aSPaolo Bonzini { 1790434e30aSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 1800434e30aSPaolo Bonzini 181837cf101SAndreas Färber dc->realize = a9mp_priv_realize; 1824f67d30bSMarc-André Lureau device_class_set_props(dc, a9mp_priv_properties); 1830434e30aSPaolo Bonzini } 1840434e30aSPaolo Bonzini 1850434e30aSPaolo Bonzini static const TypeInfo a9mp_priv_info = { 1865126fec7SAndreas Färber .name = TYPE_A9MPCORE_PRIV, 1870434e30aSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 1880434e30aSPaolo Bonzini .instance_size = sizeof(A9MPPrivState), 189753bc6e9SAndreas Färber .instance_init = a9mp_priv_initfn, 1900434e30aSPaolo Bonzini .class_init = a9mp_priv_class_init, 1910434e30aSPaolo Bonzini }; 1920434e30aSPaolo Bonzini 1930434e30aSPaolo Bonzini static void a9mp_register_types(void) 1940434e30aSPaolo Bonzini { 1950434e30aSPaolo Bonzini type_register_static(&a9mp_priv_info); 1960434e30aSPaolo Bonzini } 1970434e30aSPaolo Bonzini 1980434e30aSPaolo Bonzini type_init(a9mp_register_types) 199