1 /* 2 * Cortex-A15MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2012 Linaro Limited. 5 * Written by Peter Maydell. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/cpu/a15mpcore.h" 23 #include "sysemu/kvm.h" 24 #include "kvm_arm.h" 25 26 static void a15mp_priv_set_irq(void *opaque, int irq, int level) 27 { 28 A15MPPrivState *s = (A15MPPrivState *)opaque; 29 30 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 31 } 32 33 static void a15mp_priv_initfn(Object *obj) 34 { 35 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 36 A15MPPrivState *s = A15MPCORE_PRIV(obj); 37 DeviceState *gicdev; 38 39 memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000); 40 sysbus_init_mmio(sbd, &s->container); 41 42 object_initialize(&s->gic, sizeof(s->gic), gic_class_name()); 43 gicdev = DEVICE(&s->gic); 44 qdev_set_parent_bus(gicdev, sysbus_get_default()); 45 qdev_prop_set_uint32(gicdev, "revision", 2); 46 } 47 48 static void a15mp_priv_realize(DeviceState *dev, Error **errp) 49 { 50 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 51 A15MPPrivState *s = A15MPCORE_PRIV(dev); 52 DeviceState *gicdev; 53 SysBusDevice *busdev; 54 int i; 55 Error *err = NULL; 56 bool has_el3; 57 Object *cpuobj; 58 59 gicdev = DEVICE(&s->gic); 60 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); 61 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); 62 63 if (!kvm_irqchip_in_kernel()) { 64 /* Make the GIC's TZ support match the CPUs. We assume that 65 * either all the CPUs have TZ, or none do. 66 */ 67 cpuobj = OBJECT(qemu_get_cpu(0)); 68 has_el3 = object_property_find(cpuobj, "has_el3", NULL) && 69 object_property_get_bool(cpuobj, "has_el3", &error_abort); 70 qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); 71 } 72 73 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 74 if (err != NULL) { 75 error_propagate(errp, err); 76 return; 77 } 78 busdev = SYS_BUS_DEVICE(&s->gic); 79 80 /* Pass through outbound IRQ lines from the GIC */ 81 sysbus_pass_irq(sbd, busdev); 82 83 /* Pass through inbound GPIO lines to the GIC */ 84 qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32); 85 86 /* Wire the outputs from each CPU's generic timer to the 87 * appropriate GIC PPI inputs 88 */ 89 for (i = 0; i < s->num_cpu; i++) { 90 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 91 int ppibase = s->num_irq - 32 + i * 32; 92 int irq; 93 /* Mapping from the output timer irq lines from the CPU to the 94 * GIC PPI inputs used on the A15: 95 */ 96 const int timer_irq[] = { 97 [GTIMER_PHYS] = 30, 98 [GTIMER_VIRT] = 27, 99 [GTIMER_HYP] = 26, 100 [GTIMER_SEC] = 29, 101 }; 102 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 103 qdev_connect_gpio_out(cpudev, irq, 104 qdev_get_gpio_in(gicdev, 105 ppibase + timer_irq[irq])); 106 } 107 } 108 109 /* Memory map (addresses are offsets from PERIPHBASE): 110 * 0x0000-0x0fff -- reserved 111 * 0x1000-0x1fff -- GIC Distributor 112 * 0x2000-0x2fff -- GIC CPU interface 113 * 0x4000-0x4fff -- GIC virtual interface control (not modelled) 114 * 0x5000-0x5fff -- GIC virtual interface control (not modelled) 115 * 0x6000-0x7fff -- GIC virtual CPU interface (not modelled) 116 */ 117 memory_region_add_subregion(&s->container, 0x1000, 118 sysbus_mmio_get_region(busdev, 0)); 119 memory_region_add_subregion(&s->container, 0x2000, 120 sysbus_mmio_get_region(busdev, 1)); 121 } 122 123 static Property a15mp_priv_properties[] = { 124 DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), 125 /* The Cortex-A15MP may have anything from 0 to 224 external interrupt 126 * IRQ lines (with another 32 internal). We default to 128+32, which 127 * is the number provided by the Cortex-A15MP test chip in the 128 * Versatile Express A15 development board. 129 * Other boards may differ and should set this property appropriately. 130 */ 131 DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160), 132 DEFINE_PROP_END_OF_LIST(), 133 }; 134 135 static void a15mp_priv_class_init(ObjectClass *klass, void *data) 136 { 137 DeviceClass *dc = DEVICE_CLASS(klass); 138 139 dc->realize = a15mp_priv_realize; 140 dc->props = a15mp_priv_properties; 141 /* We currently have no savable state */ 142 } 143 144 static const TypeInfo a15mp_priv_info = { 145 .name = TYPE_A15MPCORE_PRIV, 146 .parent = TYPE_SYS_BUS_DEVICE, 147 .instance_size = sizeof(A15MPPrivState), 148 .instance_init = a15mp_priv_initfn, 149 .class_init = a15mp_priv_class_init, 150 }; 151 152 static void a15mp_register_types(void) 153 { 154 type_register_static(&a15mp_priv_info); 155 } 156 157 type_init(a15mp_register_types) 158