1 /* 2 * Cortex-A15MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2012 Linaro Limited. 5 * Written by Peter Maydell. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "hw/sysbus.h" 22 #include "sysemu/kvm.h" 23 24 /* A15MP private memory region. */ 25 26 typedef struct A15MPPrivState { 27 SysBusDevice busdev; 28 uint32_t num_cpu; 29 uint32_t num_irq; 30 MemoryRegion container; 31 DeviceState *gic; 32 } A15MPPrivState; 33 34 static void a15mp_priv_set_irq(void *opaque, int irq, int level) 35 { 36 A15MPPrivState *s = (A15MPPrivState *)opaque; 37 qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); 38 } 39 40 static int a15mp_priv_init(SysBusDevice *dev) 41 { 42 A15MPPrivState *s = FROM_SYSBUS(A15MPPrivState, dev); 43 SysBusDevice *busdev; 44 const char *gictype = "arm_gic"; 45 46 if (kvm_irqchip_in_kernel()) { 47 gictype = "kvm-arm-gic"; 48 } 49 50 s->gic = qdev_create(NULL, gictype); 51 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); 52 qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); 53 qdev_prop_set_uint32(s->gic, "revision", 2); 54 qdev_init_nofail(s->gic); 55 busdev = SYS_BUS_DEVICE(s->gic); 56 57 /* Pass through outbound IRQ lines from the GIC */ 58 sysbus_pass_irq(dev, busdev); 59 60 /* Pass through inbound GPIO lines to the GIC */ 61 qdev_init_gpio_in(&s->busdev.qdev, a15mp_priv_set_irq, s->num_irq - 32); 62 63 /* Memory map (addresses are offsets from PERIPHBASE): 64 * 0x0000-0x0fff -- reserved 65 * 0x1000-0x1fff -- GIC Distributor 66 * 0x2000-0x2fff -- GIC CPU interface 67 * 0x4000-0x4fff -- GIC virtual interface control (not modelled) 68 * 0x5000-0x5fff -- GIC virtual interface control (not modelled) 69 * 0x6000-0x7fff -- GIC virtual CPU interface (not modelled) 70 */ 71 memory_region_init(&s->container, "a15mp-priv-container", 0x8000); 72 memory_region_add_subregion(&s->container, 0x1000, 73 sysbus_mmio_get_region(busdev, 0)); 74 memory_region_add_subregion(&s->container, 0x2000, 75 sysbus_mmio_get_region(busdev, 1)); 76 77 sysbus_init_mmio(dev, &s->container); 78 return 0; 79 } 80 81 static Property a15mp_priv_properties[] = { 82 DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), 83 /* The Cortex-A15MP may have anything from 0 to 224 external interrupt 84 * IRQ lines (with another 32 internal). We default to 64+32, which 85 * is the number provided by the Cortex-A15MP test chip in the 86 * Versatile Express A15 development board. 87 * Other boards may differ and should set this property appropriately. 88 */ 89 DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 96), 90 DEFINE_PROP_END_OF_LIST(), 91 }; 92 93 static void a15mp_priv_class_init(ObjectClass *klass, void *data) 94 { 95 DeviceClass *dc = DEVICE_CLASS(klass); 96 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 97 k->init = a15mp_priv_init; 98 dc->props = a15mp_priv_properties; 99 /* We currently have no savable state */ 100 } 101 102 static const TypeInfo a15mp_priv_info = { 103 .name = "a15mpcore_priv", 104 .parent = TYPE_SYS_BUS_DEVICE, 105 .instance_size = sizeof(A15MPPrivState), 106 .class_init = a15mp_priv_class_init, 107 }; 108 109 static void a15mp_register_types(void) 110 { 111 type_register_static(&a15mp_priv_info); 112 } 113 114 type_init(a15mp_register_types) 115