1 /* 2 * Cortex-A15MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2012 Linaro Limited. 5 * Written by Peter Maydell. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/module.h" 24 #include "hw/cpu/a15mpcore.h" 25 #include "hw/irq.h" 26 #include "hw/qdev-properties.h" 27 #include "sysemu/kvm.h" 28 #include "kvm_arm.h" 29 30 static void a15mp_priv_set_irq(void *opaque, int irq, int level) 31 { 32 A15MPPrivState *s = (A15MPPrivState *)opaque; 33 34 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 35 } 36 37 static void a15mp_priv_initfn(Object *obj) 38 { 39 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 40 A15MPPrivState *s = A15MPCORE_PRIV(obj); 41 42 memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000); 43 sysbus_init_mmio(sbd, &s->container); 44 45 sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), 46 gic_class_name()); 47 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 48 } 49 50 static void a15mp_priv_realize(DeviceState *dev, Error **errp) 51 { 52 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 53 A15MPPrivState *s = A15MPCORE_PRIV(dev); 54 DeviceState *gicdev; 55 SysBusDevice *busdev; 56 int i; 57 Error *err = NULL; 58 bool has_el3; 59 bool has_el2 = false; 60 Object *cpuobj; 61 62 gicdev = DEVICE(&s->gic); 63 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); 64 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); 65 66 if (!kvm_irqchip_in_kernel()) { 67 /* Make the GIC's TZ support match the CPUs. We assume that 68 * either all the CPUs have TZ, or none do. 69 */ 70 cpuobj = OBJECT(qemu_get_cpu(0)); 71 has_el3 = object_property_find(cpuobj, "has_el3", NULL) && 72 object_property_get_bool(cpuobj, "has_el3", &error_abort); 73 qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); 74 /* Similarly for virtualization support */ 75 has_el2 = object_property_find(cpuobj, "has_el2", NULL) && 76 object_property_get_bool(cpuobj, "has_el2", &error_abort); 77 qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2); 78 } 79 80 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 81 if (err != NULL) { 82 error_propagate(errp, err); 83 return; 84 } 85 busdev = SYS_BUS_DEVICE(&s->gic); 86 87 /* Pass through outbound IRQ lines from the GIC */ 88 sysbus_pass_irq(sbd, busdev); 89 90 /* Pass through inbound GPIO lines to the GIC */ 91 qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32); 92 93 /* Wire the outputs from each CPU's generic timer to the 94 * appropriate GIC PPI inputs 95 */ 96 for (i = 0; i < s->num_cpu; i++) { 97 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 98 int ppibase = s->num_irq - 32 + i * 32; 99 int irq; 100 /* Mapping from the output timer irq lines from the CPU to the 101 * GIC PPI inputs used on the A15: 102 */ 103 const int timer_irq[] = { 104 [GTIMER_PHYS] = 30, 105 [GTIMER_VIRT] = 27, 106 [GTIMER_HYP] = 26, 107 [GTIMER_SEC] = 29, 108 }; 109 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 110 qdev_connect_gpio_out(cpudev, irq, 111 qdev_get_gpio_in(gicdev, 112 ppibase + timer_irq[irq])); 113 } 114 if (has_el2) { 115 /* Connect the GIC maintenance interrupt to PPI ID 25 */ 116 sysbus_connect_irq(SYS_BUS_DEVICE(gicdev), i + 4 * s->num_cpu, 117 qdev_get_gpio_in(gicdev, ppibase + 25)); 118 } 119 } 120 121 /* Memory map (addresses are offsets from PERIPHBASE): 122 * 0x0000-0x0fff -- reserved 123 * 0x1000-0x1fff -- GIC Distributor 124 * 0x2000-0x3fff -- GIC CPU interface 125 * 0x4000-0x4fff -- GIC virtual interface control for this CPU 126 * 0x5000-0x51ff -- GIC virtual interface control for CPU 0 127 * 0x5200-0x53ff -- GIC virtual interface control for CPU 1 128 * 0x5400-0x55ff -- GIC virtual interface control for CPU 2 129 * 0x5600-0x57ff -- GIC virtual interface control for CPU 3 130 * 0x6000-0x7fff -- GIC virtual CPU interface 131 */ 132 memory_region_add_subregion(&s->container, 0x1000, 133 sysbus_mmio_get_region(busdev, 0)); 134 memory_region_add_subregion(&s->container, 0x2000, 135 sysbus_mmio_get_region(busdev, 1)); 136 if (has_el2) { 137 memory_region_add_subregion(&s->container, 0x4000, 138 sysbus_mmio_get_region(busdev, 2)); 139 memory_region_add_subregion(&s->container, 0x6000, 140 sysbus_mmio_get_region(busdev, 3)); 141 for (i = 0; i < s->num_cpu; i++) { 142 hwaddr base = 0x5000 + i * 0x200; 143 MemoryRegion *mr = sysbus_mmio_get_region(busdev, 144 4 + s->num_cpu + i); 145 memory_region_add_subregion(&s->container, base, mr); 146 } 147 } 148 } 149 150 static Property a15mp_priv_properties[] = { 151 DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), 152 /* The Cortex-A15MP may have anything from 0 to 224 external interrupt 153 * IRQ lines (with another 32 internal). We default to 128+32, which 154 * is the number provided by the Cortex-A15MP test chip in the 155 * Versatile Express A15 development board. 156 * Other boards may differ and should set this property appropriately. 157 */ 158 DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160), 159 DEFINE_PROP_END_OF_LIST(), 160 }; 161 162 static void a15mp_priv_class_init(ObjectClass *klass, void *data) 163 { 164 DeviceClass *dc = DEVICE_CLASS(klass); 165 166 dc->realize = a15mp_priv_realize; 167 device_class_set_props(dc, a15mp_priv_properties); 168 /* We currently have no savable state */ 169 } 170 171 static const TypeInfo a15mp_priv_info = { 172 .name = TYPE_A15MPCORE_PRIV, 173 .parent = TYPE_SYS_BUS_DEVICE, 174 .instance_size = sizeof(A15MPPrivState), 175 .instance_init = a15mp_priv_initfn, 176 .class_init = a15mp_priv_class_init, 177 }; 178 179 static void a15mp_register_types(void) 180 { 181 type_register_static(&a15mp_priv_info); 182 } 183 184 type_init(a15mp_register_types) 185