1 /* 2 * Cortex-A15MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2012 Linaro Limited. 5 * Written by Peter Maydell. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "hw/sysbus.h" 22 #include "sysemu/kvm.h" 23 24 /* A15MP private memory region. */ 25 26 #define TYPE_A15MPCORE_PRIV "a15mpcore_priv" 27 #define A15MPCORE_PRIV(obj) \ 28 OBJECT_CHECK(A15MPPrivState, (obj), TYPE_A15MPCORE_PRIV) 29 30 typedef struct A15MPPrivState { 31 /*< private >*/ 32 SysBusDevice parent_obj; 33 /*< public >*/ 34 35 uint32_t num_cpu; 36 uint32_t num_irq; 37 MemoryRegion container; 38 DeviceState *gic; 39 } A15MPPrivState; 40 41 static void a15mp_priv_set_irq(void *opaque, int irq, int level) 42 { 43 A15MPPrivState *s = (A15MPPrivState *)opaque; 44 qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); 45 } 46 47 static int a15mp_priv_init(SysBusDevice *dev) 48 { 49 A15MPPrivState *s = A15MPCORE_PRIV(dev); 50 SysBusDevice *busdev; 51 const char *gictype = "arm_gic"; 52 53 if (kvm_irqchip_in_kernel()) { 54 gictype = "kvm-arm-gic"; 55 } 56 57 s->gic = qdev_create(NULL, gictype); 58 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); 59 qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); 60 qdev_prop_set_uint32(s->gic, "revision", 2); 61 qdev_init_nofail(s->gic); 62 busdev = SYS_BUS_DEVICE(s->gic); 63 64 /* Pass through outbound IRQ lines from the GIC */ 65 sysbus_pass_irq(dev, busdev); 66 67 /* Pass through inbound GPIO lines to the GIC */ 68 qdev_init_gpio_in(DEVICE(dev), a15mp_priv_set_irq, s->num_irq - 32); 69 70 /* Memory map (addresses are offsets from PERIPHBASE): 71 * 0x0000-0x0fff -- reserved 72 * 0x1000-0x1fff -- GIC Distributor 73 * 0x2000-0x2fff -- GIC CPU interface 74 * 0x4000-0x4fff -- GIC virtual interface control (not modelled) 75 * 0x5000-0x5fff -- GIC virtual interface control (not modelled) 76 * 0x6000-0x7fff -- GIC virtual CPU interface (not modelled) 77 */ 78 memory_region_init(&s->container, OBJECT(s), 79 "a15mp-priv-container", 0x8000); 80 memory_region_add_subregion(&s->container, 0x1000, 81 sysbus_mmio_get_region(busdev, 0)); 82 memory_region_add_subregion(&s->container, 0x2000, 83 sysbus_mmio_get_region(busdev, 1)); 84 85 sysbus_init_mmio(dev, &s->container); 86 return 0; 87 } 88 89 static Property a15mp_priv_properties[] = { 90 DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), 91 /* The Cortex-A15MP may have anything from 0 to 224 external interrupt 92 * IRQ lines (with another 32 internal). We default to 128+32, which 93 * is the number provided by the Cortex-A15MP test chip in the 94 * Versatile Express A15 development board. 95 * Other boards may differ and should set this property appropriately. 96 */ 97 DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160), 98 DEFINE_PROP_END_OF_LIST(), 99 }; 100 101 static void a15mp_priv_class_init(ObjectClass *klass, void *data) 102 { 103 DeviceClass *dc = DEVICE_CLASS(klass); 104 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 105 k->init = a15mp_priv_init; 106 dc->props = a15mp_priv_properties; 107 /* We currently have no savable state */ 108 } 109 110 static const TypeInfo a15mp_priv_info = { 111 .name = TYPE_A15MPCORE_PRIV, 112 .parent = TYPE_SYS_BUS_DEVICE, 113 .instance_size = sizeof(A15MPPrivState), 114 .class_init = a15mp_priv_class_init, 115 }; 116 117 static void a15mp_register_types(void) 118 { 119 type_register_static(&a15mp_priv_info); 120 } 121 122 type_init(a15mp_register_types) 123