1 /* 2 * Cortex-A15MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2012 Linaro Limited. 5 * Written by Peter Maydell. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/module.h" 24 #include "hw/cpu/a15mpcore.h" 25 #include "hw/irq.h" 26 #include "hw/qdev-properties.h" 27 #include "sysemu/kvm.h" 28 #include "kvm_arm.h" 29 #include "target/arm/gtimer.h" 30 31 static void a15mp_priv_set_irq(void *opaque, int irq, int level) 32 { 33 A15MPPrivState *s = (A15MPPrivState *)opaque; 34 35 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 36 } 37 38 static void a15mp_priv_initfn(Object *obj) 39 { 40 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 41 A15MPPrivState *s = A15MPCORE_PRIV(obj); 42 43 memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000); 44 sysbus_init_mmio(sbd, &s->container); 45 46 object_initialize_child(obj, "gic", &s->gic, gic_class_name()); 47 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 48 } 49 50 static void a15mp_priv_realize(DeviceState *dev, Error **errp) 51 { 52 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 53 A15MPPrivState *s = A15MPCORE_PRIV(dev); 54 DeviceState *gicdev; 55 SysBusDevice *busdev; 56 int i; 57 bool has_el3; 58 bool has_el2 = false; 59 Object *cpuobj; 60 61 gicdev = DEVICE(&s->gic); 62 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); 63 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); 64 65 if (!kvm_irqchip_in_kernel()) { 66 /* Make the GIC's TZ support match the CPUs. We assume that 67 * either all the CPUs have TZ, or none do. 68 */ 69 cpuobj = OBJECT(qemu_get_cpu(0)); 70 has_el3 = object_property_find(cpuobj, "has_el3") && 71 object_property_get_bool(cpuobj, "has_el3", &error_abort); 72 qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); 73 /* Similarly for virtualization support */ 74 has_el2 = object_property_find(cpuobj, "has_el2") && 75 object_property_get_bool(cpuobj, "has_el2", &error_abort); 76 qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2); 77 } 78 79 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { 80 return; 81 } 82 busdev = SYS_BUS_DEVICE(&s->gic); 83 84 /* Pass through outbound IRQ lines from the GIC */ 85 sysbus_pass_irq(sbd, busdev); 86 87 /* Pass through inbound GPIO lines to the GIC */ 88 qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32); 89 90 /* Wire the outputs from each CPU's generic timer to the 91 * appropriate GIC PPI inputs 92 */ 93 for (i = 0; i < s->num_cpu; i++) { 94 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 95 int ppibase = s->num_irq - 32 + i * 32; 96 int irq; 97 /* Mapping from the output timer irq lines from the CPU to the 98 * GIC PPI inputs used on the A15: 99 */ 100 const int timer_irq[] = { 101 [GTIMER_PHYS] = 30, 102 [GTIMER_VIRT] = 27, 103 [GTIMER_HYP] = 26, 104 [GTIMER_SEC] = 29, 105 }; 106 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 107 qdev_connect_gpio_out(cpudev, irq, 108 qdev_get_gpio_in(gicdev, 109 ppibase + timer_irq[irq])); 110 } 111 if (has_el2) { 112 /* Connect the GIC maintenance interrupt to PPI ID 25 */ 113 sysbus_connect_irq(SYS_BUS_DEVICE(gicdev), i + 4 * s->num_cpu, 114 qdev_get_gpio_in(gicdev, ppibase + 25)); 115 } 116 } 117 118 /* Memory map (addresses are offsets from PERIPHBASE): 119 * 0x0000-0x0fff -- reserved 120 * 0x1000-0x1fff -- GIC Distributor 121 * 0x2000-0x3fff -- GIC CPU interface 122 * 0x4000-0x4fff -- GIC virtual interface control for this CPU 123 * 0x5000-0x51ff -- GIC virtual interface control for CPU 0 124 * 0x5200-0x53ff -- GIC virtual interface control for CPU 1 125 * 0x5400-0x55ff -- GIC virtual interface control for CPU 2 126 * 0x5600-0x57ff -- GIC virtual interface control for CPU 3 127 * 0x6000-0x7fff -- GIC virtual CPU interface 128 */ 129 memory_region_add_subregion(&s->container, 0x1000, 130 sysbus_mmio_get_region(busdev, 0)); 131 memory_region_add_subregion(&s->container, 0x2000, 132 sysbus_mmio_get_region(busdev, 1)); 133 if (has_el2) { 134 memory_region_add_subregion(&s->container, 0x4000, 135 sysbus_mmio_get_region(busdev, 2)); 136 memory_region_add_subregion(&s->container, 0x6000, 137 sysbus_mmio_get_region(busdev, 3)); 138 for (i = 0; i < s->num_cpu; i++) { 139 hwaddr base = 0x5000 + i * 0x200; 140 MemoryRegion *mr = sysbus_mmio_get_region(busdev, 141 4 + s->num_cpu + i); 142 memory_region_add_subregion(&s->container, base, mr); 143 } 144 } 145 } 146 147 static Property a15mp_priv_properties[] = { 148 DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), 149 /* The Cortex-A15MP may have anything from 0 to 224 external interrupt 150 * IRQ lines (with another 32 internal). We default to 128+32, which 151 * is the number provided by the Cortex-A15MP test chip in the 152 * Versatile Express A15 development board. 153 * Other boards may differ and should set this property appropriately. 154 */ 155 DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160), 156 DEFINE_PROP_END_OF_LIST(), 157 }; 158 159 static void a15mp_priv_class_init(ObjectClass *klass, void *data) 160 { 161 DeviceClass *dc = DEVICE_CLASS(klass); 162 163 dc->realize = a15mp_priv_realize; 164 device_class_set_props(dc, a15mp_priv_properties); 165 /* We currently have no saveable state */ 166 } 167 168 static const TypeInfo a15mp_priv_info = { 169 .name = TYPE_A15MPCORE_PRIV, 170 .parent = TYPE_SYS_BUS_DEVICE, 171 .instance_size = sizeof(A15MPPrivState), 172 .instance_init = a15mp_priv_initfn, 173 .class_init = a15mp_priv_class_init, 174 }; 175 176 static void a15mp_register_types(void) 177 { 178 type_register_static(&a15mp_priv_info); 179 } 180 181 type_init(a15mp_register_types) 182