1 /* 2 * General purpose implementation of a simple periodic countdown timer. 3 * 4 * Copyright (c) 2007 CodeSourcery. 5 * 6 * This code is licensed under the GNU LGPL. 7 */ 8 #include "qemu/osdep.h" 9 #include "hw/hw.h" 10 #include "qemu/timer.h" 11 #include "hw/ptimer.h" 12 #include "qemu/host-utils.h" 13 #include "sysemu/replay.h" 14 #include "sysemu/qtest.h" 15 16 #define DELTA_ADJUST 1 17 18 struct ptimer_state 19 { 20 uint8_t enabled; /* 0 = disabled, 1 = periodic, 2 = oneshot. */ 21 uint64_t limit; 22 uint64_t delta; 23 uint32_t period_frac; 24 int64_t period; 25 int64_t last_event; 26 int64_t next_event; 27 uint8_t policy_mask; 28 QEMUBH *bh; 29 QEMUTimer *timer; 30 }; 31 32 /* Use a bottom-half routine to avoid reentrancy issues. */ 33 static void ptimer_trigger(ptimer_state *s) 34 { 35 if (s->bh) { 36 replay_bh_schedule_event(s->bh); 37 } 38 } 39 40 static void ptimer_reload(ptimer_state *s, int delta_adjust) 41 { 42 uint32_t period_frac = s->period_frac; 43 uint64_t period = s->period; 44 uint64_t delta = s->delta; 45 46 if (delta == 0) { 47 ptimer_trigger(s); 48 delta = s->delta = s->limit; 49 } 50 51 if (s->period == 0) { 52 if (!qtest_enabled()) { 53 fprintf(stderr, "Timer with period zero, disabling\n"); 54 } 55 timer_del(s->timer); 56 s->enabled = 0; 57 return; 58 } 59 60 if (s->policy_mask & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD) { 61 delta += delta_adjust; 62 } 63 64 if (delta == 0 && (s->policy_mask & PTIMER_POLICY_CONTINUOUS_TRIGGER)) { 65 if (s->enabled == 1 && s->limit == 0) { 66 delta = 1; 67 } 68 } 69 70 if (delta == 0) { 71 if (!qtest_enabled()) { 72 fprintf(stderr, "Timer with delta zero, disabling\n"); 73 } 74 timer_del(s->timer); 75 s->enabled = 0; 76 return; 77 } 78 79 /* 80 * Artificially limit timeout rate to something 81 * achievable under QEMU. Otherwise, QEMU spends all 82 * its time generating timer interrupts, and there 83 * is no forward progress. 84 * About ten microseconds is the fastest that really works 85 * on the current generation of host machines. 86 */ 87 88 if (s->enabled == 1 && (delta * period < 10000) && !use_icount) { 89 period = 10000 / delta; 90 period_frac = 0; 91 } 92 93 s->last_event = s->next_event; 94 s->next_event = s->last_event + delta * period; 95 if (period_frac) { 96 s->next_event += ((int64_t)period_frac * delta) >> 32; 97 } 98 timer_mod(s->timer, s->next_event); 99 } 100 101 static void ptimer_tick(void *opaque) 102 { 103 ptimer_state *s = (ptimer_state *)opaque; 104 ptimer_trigger(s); 105 s->delta = 0; 106 if (s->enabled == 2) { 107 s->enabled = 0; 108 } else { 109 int delta_adjust = DELTA_ADJUST; 110 111 if (s->limit == 0) { 112 /* If a "continuous trigger" policy is not used and limit == 0, 113 we should error out. */ 114 delta_adjust = 0; 115 } 116 117 ptimer_reload(s, delta_adjust); 118 } 119 } 120 121 uint64_t ptimer_get_count(ptimer_state *s) 122 { 123 uint64_t counter; 124 125 if (s->enabled && s->delta != 0) { 126 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 127 int64_t next = s->next_event; 128 int64_t last = s->last_event; 129 bool expired = (now - next >= 0); 130 bool oneshot = (s->enabled == 2); 131 132 /* Figure out the current counter value. */ 133 if (expired) { 134 /* Prevent timer underflowing if it should already have 135 triggered. */ 136 counter = 0; 137 } else { 138 uint64_t rem; 139 uint64_t div; 140 int clz1, clz2; 141 int shift; 142 uint32_t period_frac = s->period_frac; 143 uint64_t period = s->period; 144 145 if (!oneshot && (s->delta * period < 10000) && !use_icount) { 146 period = 10000 / s->delta; 147 period_frac = 0; 148 } 149 150 /* We need to divide time by period, where time is stored in 151 rem (64-bit integer) and period is stored in period/period_frac 152 (64.32 fixed point). 153 154 Doing full precision division is hard, so scale values and 155 do a 64-bit division. The result should be rounded down, 156 so that the rounding error never causes the timer to go 157 backwards. 158 */ 159 160 rem = next - now; 161 div = period; 162 163 clz1 = clz64(rem); 164 clz2 = clz64(div); 165 shift = clz1 < clz2 ? clz1 : clz2; 166 167 rem <<= shift; 168 div <<= shift; 169 if (shift >= 32) { 170 div |= ((uint64_t)period_frac << (shift - 32)); 171 } else { 172 if (shift != 0) 173 div |= (period_frac >> (32 - shift)); 174 /* Look at remaining bits of period_frac and round div up if 175 necessary. */ 176 if ((uint32_t)(period_frac << shift)) 177 div += 1; 178 } 179 counter = rem / div; 180 181 if (s->policy_mask & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD) { 182 /* Before wrapping around, timer should stay with counter = 0 183 for a one period. */ 184 if (!oneshot && s->delta == s->limit) { 185 if (now == last) { 186 /* Counter == delta here, check whether it was 187 adjusted and if it was, then right now it is 188 that "one period". */ 189 if (counter == s->limit + DELTA_ADJUST) { 190 return 0; 191 } 192 } else if (counter == s->limit) { 193 /* Since the counter is rounded down and now != last, 194 the counter == limit means that delta was adjusted 195 by +1 and right now it is that adjusted period. */ 196 return 0; 197 } 198 } 199 } 200 } 201 } else { 202 counter = s->delta; 203 } 204 return counter; 205 } 206 207 void ptimer_set_count(ptimer_state *s, uint64_t count) 208 { 209 s->delta = count; 210 if (s->enabled) { 211 s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 212 ptimer_reload(s, 0); 213 } 214 } 215 216 void ptimer_run(ptimer_state *s, int oneshot) 217 { 218 bool was_disabled = !s->enabled; 219 220 if (was_disabled && s->period == 0) { 221 if (!qtest_enabled()) { 222 fprintf(stderr, "Timer with period zero, disabling\n"); 223 } 224 return; 225 } 226 s->enabled = oneshot ? 2 : 1; 227 if (was_disabled) { 228 s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 229 ptimer_reload(s, 0); 230 } 231 } 232 233 /* Pause a timer. Note that this may cause it to "lose" time, even if it 234 is immediately restarted. */ 235 void ptimer_stop(ptimer_state *s) 236 { 237 if (!s->enabled) 238 return; 239 240 s->delta = ptimer_get_count(s); 241 timer_del(s->timer); 242 s->enabled = 0; 243 } 244 245 /* Set counter increment interval in nanoseconds. */ 246 void ptimer_set_period(ptimer_state *s, int64_t period) 247 { 248 s->delta = ptimer_get_count(s); 249 s->period = period; 250 s->period_frac = 0; 251 if (s->enabled) { 252 s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 253 ptimer_reload(s, 0); 254 } 255 } 256 257 /* Set counter frequency in Hz. */ 258 void ptimer_set_freq(ptimer_state *s, uint32_t freq) 259 { 260 s->delta = ptimer_get_count(s); 261 s->period = 1000000000ll / freq; 262 s->period_frac = (1000000000ll << 32) / freq; 263 if (s->enabled) { 264 s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 265 ptimer_reload(s, 0); 266 } 267 } 268 269 /* Set the initial countdown value. If reload is nonzero then also set 270 count = limit. */ 271 void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload) 272 { 273 s->limit = limit; 274 if (reload) 275 s->delta = limit; 276 if (s->enabled && reload) { 277 s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 278 ptimer_reload(s, 0); 279 } 280 } 281 282 uint64_t ptimer_get_limit(ptimer_state *s) 283 { 284 return s->limit; 285 } 286 287 const VMStateDescription vmstate_ptimer = { 288 .name = "ptimer", 289 .version_id = 1, 290 .minimum_version_id = 1, 291 .fields = (VMStateField[]) { 292 VMSTATE_UINT8(enabled, ptimer_state), 293 VMSTATE_UINT64(limit, ptimer_state), 294 VMSTATE_UINT64(delta, ptimer_state), 295 VMSTATE_UINT32(period_frac, ptimer_state), 296 VMSTATE_INT64(period, ptimer_state), 297 VMSTATE_INT64(last_event, ptimer_state), 298 VMSTATE_INT64(next_event, ptimer_state), 299 VMSTATE_TIMER_PTR(timer, ptimer_state), 300 VMSTATE_END_OF_LIST() 301 } 302 }; 303 304 ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask) 305 { 306 ptimer_state *s; 307 308 s = (ptimer_state *)g_malloc0(sizeof(ptimer_state)); 309 s->bh = bh; 310 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s); 311 s->policy_mask = policy_mask; 312 return s; 313 } 314