1 /* 2 * General purpose implementation of a simple periodic countdown timer. 3 * 4 * Copyright (c) 2007 CodeSourcery. 5 * 6 * This code is licensed under the GNU LGPL. 7 */ 8 #include "qemu/osdep.h" 9 #include "hw/hw.h" 10 #include "qemu/timer.h" 11 #include "hw/ptimer.h" 12 #include "qemu/host-utils.h" 13 #include "sysemu/replay.h" 14 15 struct ptimer_state 16 { 17 uint8_t enabled; /* 0 = disabled, 1 = periodic, 2 = oneshot. */ 18 uint64_t limit; 19 uint64_t delta; 20 uint32_t period_frac; 21 int64_t period; 22 int64_t last_event; 23 int64_t next_event; 24 QEMUBH *bh; 25 QEMUTimer *timer; 26 }; 27 28 /* Use a bottom-half routine to avoid reentrancy issues. */ 29 static void ptimer_trigger(ptimer_state *s) 30 { 31 if (s->bh) { 32 replay_bh_schedule_event(s->bh); 33 } 34 } 35 36 static void ptimer_reload(ptimer_state *s) 37 { 38 uint32_t period_frac = s->period_frac; 39 uint64_t period = s->period; 40 41 if (s->delta == 0) { 42 ptimer_trigger(s); 43 s->delta = s->limit; 44 } 45 if (s->delta == 0 || s->period == 0) { 46 fprintf(stderr, "Timer with period zero, disabling\n"); 47 s->enabled = 0; 48 return; 49 } 50 51 /* 52 * Artificially limit timeout rate to something 53 * achievable under QEMU. Otherwise, QEMU spends all 54 * its time generating timer interrupts, and there 55 * is no forward progress. 56 * About ten microseconds is the fastest that really works 57 * on the current generation of host machines. 58 */ 59 60 if (s->enabled == 1 && (s->delta * period < 10000) && !use_icount) { 61 period = 10000 / s->delta; 62 period_frac = 0; 63 } 64 65 s->last_event = s->next_event; 66 s->next_event = s->last_event + s->delta * period; 67 if (period_frac) { 68 s->next_event += ((int64_t)period_frac * s->delta) >> 32; 69 } 70 timer_mod(s->timer, s->next_event); 71 } 72 73 static void ptimer_tick(void *opaque) 74 { 75 ptimer_state *s = (ptimer_state *)opaque; 76 ptimer_trigger(s); 77 s->delta = 0; 78 if (s->enabled == 2) { 79 s->enabled = 0; 80 } else { 81 ptimer_reload(s); 82 } 83 } 84 85 uint64_t ptimer_get_count(ptimer_state *s) 86 { 87 int64_t now; 88 uint64_t counter; 89 90 if (s->enabled) { 91 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 92 /* Figure out the current counter value. */ 93 if (now - s->next_event > 0 94 || s->period == 0) { 95 /* Prevent timer underflowing if it should already have 96 triggered. */ 97 counter = 0; 98 } else { 99 uint64_t rem; 100 uint64_t div; 101 int clz1, clz2; 102 int shift; 103 uint32_t period_frac = s->period_frac; 104 uint64_t period = s->period; 105 106 if ((s->enabled == 1) && !use_icount && (s->delta * period < 10000)) { 107 period = 10000 / s->delta; 108 period_frac = 0; 109 } 110 111 /* We need to divide time by period, where time is stored in 112 rem (64-bit integer) and period is stored in period/period_frac 113 (64.32 fixed point). 114 115 Doing full precision division is hard, so scale values and 116 do a 64-bit division. The result should be rounded down, 117 so that the rounding error never causes the timer to go 118 backwards. 119 */ 120 121 rem = s->next_event - now; 122 div = period; 123 124 clz1 = clz64(rem); 125 clz2 = clz64(div); 126 shift = clz1 < clz2 ? clz1 : clz2; 127 128 rem <<= shift; 129 div <<= shift; 130 if (shift >= 32) { 131 div |= ((uint64_t)period_frac << (shift - 32)); 132 } else { 133 if (shift != 0) 134 div |= (period_frac >> (32 - shift)); 135 /* Look at remaining bits of period_frac and round div up if 136 necessary. */ 137 if ((uint32_t)(period_frac << shift)) 138 div += 1; 139 } 140 counter = rem / div; 141 } 142 } else { 143 counter = s->delta; 144 } 145 return counter; 146 } 147 148 void ptimer_set_count(ptimer_state *s, uint64_t count) 149 { 150 s->delta = count; 151 if (s->enabled) { 152 s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 153 ptimer_reload(s); 154 } 155 } 156 157 void ptimer_run(ptimer_state *s, int oneshot) 158 { 159 if (s->enabled) { 160 return; 161 } 162 if (s->period == 0) { 163 fprintf(stderr, "Timer with period zero, disabling\n"); 164 return; 165 } 166 s->enabled = oneshot ? 2 : 1; 167 s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 168 ptimer_reload(s); 169 } 170 171 /* Pause a timer. Note that this may cause it to "lose" time, even if it 172 is immediately restarted. */ 173 void ptimer_stop(ptimer_state *s) 174 { 175 if (!s->enabled) 176 return; 177 178 s->delta = ptimer_get_count(s); 179 timer_del(s->timer); 180 s->enabled = 0; 181 } 182 183 /* Set counter increment interval in nanoseconds. */ 184 void ptimer_set_period(ptimer_state *s, int64_t period) 185 { 186 s->period = period; 187 s->period_frac = 0; 188 if (s->enabled) { 189 s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 190 ptimer_reload(s); 191 } 192 } 193 194 /* Set counter frequency in Hz. */ 195 void ptimer_set_freq(ptimer_state *s, uint32_t freq) 196 { 197 s->period = 1000000000ll / freq; 198 s->period_frac = (1000000000ll << 32) / freq; 199 if (s->enabled) { 200 s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 201 ptimer_reload(s); 202 } 203 } 204 205 /* Set the initial countdown value. If reload is nonzero then also set 206 count = limit. */ 207 void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload) 208 { 209 s->limit = limit; 210 if (reload) 211 s->delta = limit; 212 if (s->enabled && reload) { 213 s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 214 ptimer_reload(s); 215 } 216 } 217 218 const VMStateDescription vmstate_ptimer = { 219 .name = "ptimer", 220 .version_id = 1, 221 .minimum_version_id = 1, 222 .fields = (VMStateField[]) { 223 VMSTATE_UINT8(enabled, ptimer_state), 224 VMSTATE_UINT64(limit, ptimer_state), 225 VMSTATE_UINT64(delta, ptimer_state), 226 VMSTATE_UINT32(period_frac, ptimer_state), 227 VMSTATE_INT64(period, ptimer_state), 228 VMSTATE_INT64(last_event, ptimer_state), 229 VMSTATE_INT64(next_event, ptimer_state), 230 VMSTATE_TIMER_PTR(timer, ptimer_state), 231 VMSTATE_END_OF_LIST() 232 } 233 }; 234 235 ptimer_state *ptimer_init(QEMUBH *bh) 236 { 237 ptimer_state *s; 238 239 s = (ptimer_state *)g_malloc0(sizeof(ptimer_state)); 240 s->bh = bh; 241 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s); 242 return s; 243 } 244