1 /* 2 * QEMU Machine 3 * 4 * Copyright (C) 2014 Red Hat Inc 5 * 6 * Authors: 7 * Marcel Apfelbaum <marcel.a@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/option.h" 15 #include "qemu/accel.h" 16 #include "sysemu/replay.h" 17 #include "qemu/units.h" 18 #include "hw/boards.h" 19 #include "hw/loader.h" 20 #include "qapi/error.h" 21 #include "qapi/qapi-visit-common.h" 22 #include "qapi/qapi-visit-machine.h" 23 #include "qapi/visitor.h" 24 #include "qom/object_interfaces.h" 25 #include "hw/sysbus.h" 26 #include "sysemu/cpus.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/numa.h" 31 #include "sysemu/xen.h" 32 #include "qemu/error-report.h" 33 #include "sysemu/qtest.h" 34 #include "hw/pci/pci.h" 35 #include "hw/mem/nvdimm.h" 36 #include "migration/global_state.h" 37 #include "migration/vmstate.h" 38 #include "exec/confidential-guest-support.h" 39 #include "hw/virtio/virtio.h" 40 #include "hw/virtio/virtio-pci.h" 41 42 GlobalProperty hw_compat_7_2[] = { 43 { "e1000e", "migrate-timadj", "off" }, 44 { "virtio-mem", "x-early-migration", "false" }, 45 }; 46 const size_t hw_compat_7_2_len = G_N_ELEMENTS(hw_compat_7_2); 47 48 GlobalProperty hw_compat_7_1[] = { 49 { "virtio-device", "queue_reset", "false" }, 50 { "virtio-rng-pci", "vectors", "0" }, 51 { "virtio-rng-pci-transitional", "vectors", "0" }, 52 { "virtio-rng-pci-non-transitional", "vectors", "0" }, 53 }; 54 const size_t hw_compat_7_1_len = G_N_ELEMENTS(hw_compat_7_1); 55 56 GlobalProperty hw_compat_7_0[] = { 57 { "arm-gicv3-common", "force-8-bit-prio", "on" }, 58 { "nvme-ns", "eui64-default", "on"}, 59 }; 60 const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0); 61 62 GlobalProperty hw_compat_6_2[] = { 63 { "PIIX4_PM", "x-not-migrate-acpi-index", "on"}, 64 }; 65 const size_t hw_compat_6_2_len = G_N_ELEMENTS(hw_compat_6_2); 66 67 GlobalProperty hw_compat_6_1[] = { 68 { "vhost-user-vsock-device", "seqpacket", "off" }, 69 { "nvme-ns", "shared", "off" }, 70 }; 71 const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1); 72 73 GlobalProperty hw_compat_6_0[] = { 74 { "gpex-pcihost", "allow-unmapped-accesses", "false" }, 75 { "i8042", "extended-state", "false"}, 76 { "nvme-ns", "eui64-default", "off"}, 77 { "e1000", "init-vet", "off" }, 78 { "e1000e", "init-vet", "off" }, 79 { "vhost-vsock-device", "seqpacket", "off" }, 80 }; 81 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0); 82 83 GlobalProperty hw_compat_5_2[] = { 84 { "ICH9-LPC", "smm-compat", "on"}, 85 { "PIIX4_PM", "smm-compat", "on"}, 86 { "virtio-blk-device", "report-discard-granularity", "off" }, 87 { "virtio-net-pci-base", "vectors", "3"}, 88 }; 89 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2); 90 91 GlobalProperty hw_compat_5_1[] = { 92 { "vhost-scsi", "num_queues", "1"}, 93 { "vhost-user-blk", "num-queues", "1"}, 94 { "vhost-user-scsi", "num_queues", "1"}, 95 { "virtio-blk-device", "num-queues", "1"}, 96 { "virtio-scsi-device", "num_queues", "1"}, 97 { "nvme", "use-intel-id", "on"}, 98 { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */ 99 { "pl011", "migrate-clk", "off" }, 100 { "virtio-pci", "x-ats-page-aligned", "off"}, 101 }; 102 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1); 103 104 GlobalProperty hw_compat_5_0[] = { 105 { "pci-host-bridge", "x-config-reg-migration-enabled", "off" }, 106 { "virtio-balloon-device", "page-poison", "false" }, 107 { "vmport", "x-read-set-eax", "off" }, 108 { "vmport", "x-signal-unsupported-cmd", "off" }, 109 { "vmport", "x-report-vmx-type", "off" }, 110 { "vmport", "x-cmds-v2", "off" }, 111 { "virtio-device", "x-disable-legacy-check", "true" }, 112 }; 113 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0); 114 115 GlobalProperty hw_compat_4_2[] = { 116 { "virtio-blk-device", "queue-size", "128"}, 117 { "virtio-scsi-device", "virtqueue_size", "128"}, 118 { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" }, 119 { "virtio-blk-device", "seg-max-adjust", "off"}, 120 { "virtio-scsi-device", "seg_max_adjust", "off"}, 121 { "vhost-blk-device", "seg_max_adjust", "off"}, 122 { "usb-host", "suppress-remote-wake", "off" }, 123 { "usb-redir", "suppress-remote-wake", "off" }, 124 { "qxl", "revision", "4" }, 125 { "qxl-vga", "revision", "4" }, 126 { "fw_cfg", "acpi-mr-restore", "false" }, 127 { "virtio-device", "use-disabled-flag", "false" }, 128 }; 129 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2); 130 131 GlobalProperty hw_compat_4_1[] = { 132 { "virtio-pci", "x-pcie-flr-init", "off" }, 133 }; 134 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1); 135 136 GlobalProperty hw_compat_4_0[] = { 137 { "VGA", "edid", "false" }, 138 { "secondary-vga", "edid", "false" }, 139 { "bochs-display", "edid", "false" }, 140 { "virtio-vga", "edid", "false" }, 141 { "virtio-gpu-device", "edid", "false" }, 142 { "virtio-device", "use-started", "false" }, 143 { "virtio-balloon-device", "qemu-4-0-config-size", "true" }, 144 { "pl031", "migrate-tick-offset", "false" }, 145 }; 146 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0); 147 148 GlobalProperty hw_compat_3_1[] = { 149 { "pcie-root-port", "x-speed", "2_5" }, 150 { "pcie-root-port", "x-width", "1" }, 151 { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" }, 152 { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" }, 153 { "tpm-crb", "ppi", "false" }, 154 { "tpm-tis", "ppi", "false" }, 155 { "usb-kbd", "serial", "42" }, 156 { "usb-mouse", "serial", "42" }, 157 { "usb-tablet", "serial", "42" }, 158 { "virtio-blk-device", "discard", "false" }, 159 { "virtio-blk-device", "write-zeroes", "false" }, 160 { "virtio-balloon-device", "qemu-4-0-config-size", "false" }, 161 { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */ 162 }; 163 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1); 164 165 GlobalProperty hw_compat_3_0[] = {}; 166 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0); 167 168 GlobalProperty hw_compat_2_12[] = { 169 { "migration", "decompress-error-check", "off" }, 170 { "hda-audio", "use-timer", "false" }, 171 { "cirrus-vga", "global-vmstate", "true" }, 172 { "VGA", "global-vmstate", "true" }, 173 { "vmware-svga", "global-vmstate", "true" }, 174 { "qxl-vga", "global-vmstate", "true" }, 175 }; 176 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12); 177 178 GlobalProperty hw_compat_2_11[] = { 179 { "hpet", "hpet-offset-saved", "false" }, 180 { "virtio-blk-pci", "vectors", "2" }, 181 { "vhost-user-blk-pci", "vectors", "2" }, 182 { "e1000", "migrate_tso_props", "off" }, 183 }; 184 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11); 185 186 GlobalProperty hw_compat_2_10[] = { 187 { "virtio-mouse-device", "wheel-axis", "false" }, 188 { "virtio-tablet-device", "wheel-axis", "false" }, 189 }; 190 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10); 191 192 GlobalProperty hw_compat_2_9[] = { 193 { "pci-bridge", "shpc", "off" }, 194 { "intel-iommu", "pt", "off" }, 195 { "virtio-net-device", "x-mtu-bypass-backend", "off" }, 196 { "pcie-root-port", "x-migrate-msix", "false" }, 197 }; 198 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9); 199 200 GlobalProperty hw_compat_2_8[] = { 201 { "fw_cfg_mem", "x-file-slots", "0x10" }, 202 { "fw_cfg_io", "x-file-slots", "0x10" }, 203 { "pflash_cfi01", "old-multiple-chip-handling", "on" }, 204 { "pci-bridge", "shpc", "on" }, 205 { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" }, 206 { "virtio-pci", "x-pcie-deverr-init", "off" }, 207 { "virtio-pci", "x-pcie-lnkctl-init", "off" }, 208 { "virtio-pci", "x-pcie-pm-init", "off" }, 209 { "cirrus-vga", "vgamem_mb", "8" }, 210 { "isa-cirrus-vga", "vgamem_mb", "8" }, 211 }; 212 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8); 213 214 GlobalProperty hw_compat_2_7[] = { 215 { "virtio-pci", "page-per-vq", "on" }, 216 { "virtio-serial-device", "emergency-write", "off" }, 217 { "ioapic", "version", "0x11" }, 218 { "intel-iommu", "x-buggy-eim", "true" }, 219 { "virtio-pci", "x-ignore-backend-features", "on" }, 220 }; 221 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); 222 223 GlobalProperty hw_compat_2_6[] = { 224 { "virtio-mmio", "format_transport_address", "off" }, 225 /* Optional because not all virtio-pci devices support legacy mode */ 226 { "virtio-pci", "disable-modern", "on", .optional = true }, 227 { "virtio-pci", "disable-legacy", "off", .optional = true }, 228 }; 229 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); 230 231 GlobalProperty hw_compat_2_5[] = { 232 { "isa-fdc", "fallback", "144" }, 233 { "pvscsi", "x-old-pci-configuration", "on" }, 234 { "pvscsi", "x-disable-pcie", "on" }, 235 { "vmxnet3", "x-old-msi-offsets", "on" }, 236 { "vmxnet3", "x-disable-pcie", "on" }, 237 }; 238 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5); 239 240 GlobalProperty hw_compat_2_4[] = { 241 /* Optional because the 'scsi' property is Linux-only */ 242 { "virtio-blk-device", "scsi", "true", .optional = true }, 243 { "e1000", "extra_mac_registers", "off" }, 244 { "virtio-pci", "x-disable-pcie", "on" }, 245 { "virtio-pci", "migrate-extra", "off" }, 246 { "fw_cfg_mem", "dma_enabled", "off" }, 247 { "fw_cfg_io", "dma_enabled", "off" } 248 }; 249 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4); 250 251 GlobalProperty hw_compat_2_3[] = { 252 { "virtio-blk-pci", "any_layout", "off" }, 253 { "virtio-balloon-pci", "any_layout", "off" }, 254 { "virtio-serial-pci", "any_layout", "off" }, 255 { "virtio-9p-pci", "any_layout", "off" }, 256 { "virtio-rng-pci", "any_layout", "off" }, 257 { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" }, 258 { "migration", "send-configuration", "off" }, 259 { "migration", "send-section-footer", "off" }, 260 { "migration", "store-global-state", "off" }, 261 }; 262 const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3); 263 264 GlobalProperty hw_compat_2_2[] = {}; 265 const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2); 266 267 GlobalProperty hw_compat_2_1[] = { 268 { "intel-hda", "old_msi_addr", "on" }, 269 { "VGA", "qemu-extended-regs", "off" }, 270 { "secondary-vga", "qemu-extended-regs", "off" }, 271 { "virtio-scsi-pci", "any_layout", "off" }, 272 { "usb-mouse", "usb_version", "1" }, 273 { "usb-kbd", "usb_version", "1" }, 274 { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" }, 275 }; 276 const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1); 277 278 MachineState *current_machine; 279 280 static char *machine_get_kernel(Object *obj, Error **errp) 281 { 282 MachineState *ms = MACHINE(obj); 283 284 return g_strdup(ms->kernel_filename); 285 } 286 287 static void machine_set_kernel(Object *obj, const char *value, Error **errp) 288 { 289 MachineState *ms = MACHINE(obj); 290 291 g_free(ms->kernel_filename); 292 ms->kernel_filename = g_strdup(value); 293 } 294 295 static char *machine_get_initrd(Object *obj, Error **errp) 296 { 297 MachineState *ms = MACHINE(obj); 298 299 return g_strdup(ms->initrd_filename); 300 } 301 302 static void machine_set_initrd(Object *obj, const char *value, Error **errp) 303 { 304 MachineState *ms = MACHINE(obj); 305 306 g_free(ms->initrd_filename); 307 ms->initrd_filename = g_strdup(value); 308 } 309 310 static char *machine_get_append(Object *obj, Error **errp) 311 { 312 MachineState *ms = MACHINE(obj); 313 314 return g_strdup(ms->kernel_cmdline); 315 } 316 317 static void machine_set_append(Object *obj, const char *value, Error **errp) 318 { 319 MachineState *ms = MACHINE(obj); 320 321 g_free(ms->kernel_cmdline); 322 ms->kernel_cmdline = g_strdup(value); 323 } 324 325 static char *machine_get_dtb(Object *obj, Error **errp) 326 { 327 MachineState *ms = MACHINE(obj); 328 329 return g_strdup(ms->dtb); 330 } 331 332 static void machine_set_dtb(Object *obj, const char *value, Error **errp) 333 { 334 MachineState *ms = MACHINE(obj); 335 336 g_free(ms->dtb); 337 ms->dtb = g_strdup(value); 338 } 339 340 static char *machine_get_dumpdtb(Object *obj, Error **errp) 341 { 342 MachineState *ms = MACHINE(obj); 343 344 return g_strdup(ms->dumpdtb); 345 } 346 347 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp) 348 { 349 MachineState *ms = MACHINE(obj); 350 351 g_free(ms->dumpdtb); 352 ms->dumpdtb = g_strdup(value); 353 } 354 355 static void machine_get_phandle_start(Object *obj, Visitor *v, 356 const char *name, void *opaque, 357 Error **errp) 358 { 359 MachineState *ms = MACHINE(obj); 360 int64_t value = ms->phandle_start; 361 362 visit_type_int(v, name, &value, errp); 363 } 364 365 static void machine_set_phandle_start(Object *obj, Visitor *v, 366 const char *name, void *opaque, 367 Error **errp) 368 { 369 MachineState *ms = MACHINE(obj); 370 int64_t value; 371 372 if (!visit_type_int(v, name, &value, errp)) { 373 return; 374 } 375 376 ms->phandle_start = value; 377 } 378 379 static char *machine_get_dt_compatible(Object *obj, Error **errp) 380 { 381 MachineState *ms = MACHINE(obj); 382 383 return g_strdup(ms->dt_compatible); 384 } 385 386 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp) 387 { 388 MachineState *ms = MACHINE(obj); 389 390 g_free(ms->dt_compatible); 391 ms->dt_compatible = g_strdup(value); 392 } 393 394 static bool machine_get_dump_guest_core(Object *obj, Error **errp) 395 { 396 MachineState *ms = MACHINE(obj); 397 398 return ms->dump_guest_core; 399 } 400 401 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp) 402 { 403 MachineState *ms = MACHINE(obj); 404 405 ms->dump_guest_core = value; 406 } 407 408 static bool machine_get_mem_merge(Object *obj, Error **errp) 409 { 410 MachineState *ms = MACHINE(obj); 411 412 return ms->mem_merge; 413 } 414 415 static void machine_set_mem_merge(Object *obj, bool value, Error **errp) 416 { 417 MachineState *ms = MACHINE(obj); 418 419 ms->mem_merge = value; 420 } 421 422 static bool machine_get_usb(Object *obj, Error **errp) 423 { 424 MachineState *ms = MACHINE(obj); 425 426 return ms->usb; 427 } 428 429 static void machine_set_usb(Object *obj, bool value, Error **errp) 430 { 431 MachineState *ms = MACHINE(obj); 432 433 ms->usb = value; 434 ms->usb_disabled = !value; 435 } 436 437 static bool machine_get_graphics(Object *obj, Error **errp) 438 { 439 MachineState *ms = MACHINE(obj); 440 441 return ms->enable_graphics; 442 } 443 444 static void machine_set_graphics(Object *obj, bool value, Error **errp) 445 { 446 MachineState *ms = MACHINE(obj); 447 448 ms->enable_graphics = value; 449 } 450 451 static char *machine_get_firmware(Object *obj, Error **errp) 452 { 453 MachineState *ms = MACHINE(obj); 454 455 return g_strdup(ms->firmware); 456 } 457 458 static void machine_set_firmware(Object *obj, const char *value, Error **errp) 459 { 460 MachineState *ms = MACHINE(obj); 461 462 g_free(ms->firmware); 463 ms->firmware = g_strdup(value); 464 } 465 466 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp) 467 { 468 MachineState *ms = MACHINE(obj); 469 470 ms->suppress_vmdesc = value; 471 } 472 473 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp) 474 { 475 MachineState *ms = MACHINE(obj); 476 477 return ms->suppress_vmdesc; 478 } 479 480 static char *machine_get_memory_encryption(Object *obj, Error **errp) 481 { 482 MachineState *ms = MACHINE(obj); 483 484 if (ms->cgs) { 485 return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs))); 486 } 487 488 return NULL; 489 } 490 491 static void machine_set_memory_encryption(Object *obj, const char *value, 492 Error **errp) 493 { 494 Object *cgs = 495 object_resolve_path_component(object_get_objects_root(), value); 496 497 if (!cgs) { 498 error_setg(errp, "No such memory encryption object '%s'", value); 499 return; 500 } 501 502 object_property_set_link(obj, "confidential-guest-support", cgs, errp); 503 } 504 505 static void machine_check_confidential_guest_support(const Object *obj, 506 const char *name, 507 Object *new_target, 508 Error **errp) 509 { 510 /* 511 * So far the only constraint is that the target has the 512 * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked 513 * by the QOM core 514 */ 515 } 516 517 static bool machine_get_nvdimm(Object *obj, Error **errp) 518 { 519 MachineState *ms = MACHINE(obj); 520 521 return ms->nvdimms_state->is_enabled; 522 } 523 524 static void machine_set_nvdimm(Object *obj, bool value, Error **errp) 525 { 526 MachineState *ms = MACHINE(obj); 527 528 ms->nvdimms_state->is_enabled = value; 529 } 530 531 static bool machine_get_hmat(Object *obj, Error **errp) 532 { 533 MachineState *ms = MACHINE(obj); 534 535 return ms->numa_state->hmat_enabled; 536 } 537 538 static void machine_set_hmat(Object *obj, bool value, Error **errp) 539 { 540 MachineState *ms = MACHINE(obj); 541 542 ms->numa_state->hmat_enabled = value; 543 } 544 545 static void machine_get_mem(Object *obj, Visitor *v, const char *name, 546 void *opaque, Error **errp) 547 { 548 MachineState *ms = MACHINE(obj); 549 MemorySizeConfiguration mem = { 550 .has_size = true, 551 .size = ms->ram_size, 552 .has_max_size = !!ms->ram_slots, 553 .max_size = ms->maxram_size, 554 .has_slots = !!ms->ram_slots, 555 .slots = ms->ram_slots, 556 }; 557 MemorySizeConfiguration *p_mem = &mem; 558 559 visit_type_MemorySizeConfiguration(v, name, &p_mem, &error_abort); 560 } 561 562 static void machine_set_mem(Object *obj, Visitor *v, const char *name, 563 void *opaque, Error **errp) 564 { 565 ERRP_GUARD(); 566 MachineState *ms = MACHINE(obj); 567 MachineClass *mc = MACHINE_GET_CLASS(obj); 568 MemorySizeConfiguration *mem; 569 570 if (!visit_type_MemorySizeConfiguration(v, name, &mem, errp)) { 571 return; 572 } 573 574 if (!mem->has_size) { 575 mem->has_size = true; 576 mem->size = mc->default_ram_size; 577 } 578 mem->size = QEMU_ALIGN_UP(mem->size, 8192); 579 if (mc->fixup_ram_size) { 580 mem->size = mc->fixup_ram_size(mem->size); 581 } 582 if ((ram_addr_t)mem->size != mem->size) { 583 error_setg(errp, "ram size too large"); 584 goto out_free; 585 } 586 587 if (mem->has_max_size) { 588 if (mem->max_size < mem->size) { 589 error_setg(errp, "invalid value of maxmem: " 590 "maximum memory size (0x%" PRIx64 ") must be at least " 591 "the initial memory size (0x%" PRIx64 ")", 592 mem->max_size, mem->size); 593 goto out_free; 594 } 595 if (mem->has_slots && mem->slots && mem->max_size == mem->size) { 596 error_setg(errp, "invalid value of maxmem: " 597 "memory slots were specified but maximum memory size " 598 "(0x%" PRIx64 ") is equal to the initial memory size " 599 "(0x%" PRIx64 ")", mem->max_size, mem->size); 600 goto out_free; 601 } 602 ms->maxram_size = mem->max_size; 603 } else { 604 if (mem->has_slots) { 605 error_setg(errp, "slots specified but no max-size"); 606 goto out_free; 607 } 608 ms->maxram_size = mem->size; 609 } 610 ms->ram_size = mem->size; 611 ms->ram_slots = mem->has_slots ? mem->slots : 0; 612 out_free: 613 qapi_free_MemorySizeConfiguration(mem); 614 } 615 616 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp) 617 { 618 MachineState *ms = MACHINE(obj); 619 620 return g_strdup(ms->nvdimms_state->persistence_string); 621 } 622 623 static void machine_set_nvdimm_persistence(Object *obj, const char *value, 624 Error **errp) 625 { 626 MachineState *ms = MACHINE(obj); 627 NVDIMMState *nvdimms_state = ms->nvdimms_state; 628 629 if (strcmp(value, "cpu") == 0) { 630 nvdimms_state->persistence = 3; 631 } else if (strcmp(value, "mem-ctrl") == 0) { 632 nvdimms_state->persistence = 2; 633 } else { 634 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option", 635 value); 636 return; 637 } 638 639 g_free(nvdimms_state->persistence_string); 640 nvdimms_state->persistence_string = g_strdup(value); 641 } 642 643 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type) 644 { 645 QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); 646 } 647 648 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev) 649 { 650 Object *obj = OBJECT(dev); 651 652 if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) { 653 return false; 654 } 655 656 return device_type_is_dynamic_sysbus(mc, object_get_typename(obj)); 657 } 658 659 bool device_type_is_dynamic_sysbus(MachineClass *mc, const char *type) 660 { 661 bool allowed = false; 662 strList *wl; 663 ObjectClass *klass = object_class_by_name(type); 664 665 for (wl = mc->allowed_dynamic_sysbus_devices; 666 !allowed && wl; 667 wl = wl->next) { 668 allowed |= !!object_class_dynamic_cast(klass, wl->value); 669 } 670 671 return allowed; 672 } 673 674 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine) 675 { 676 int i; 677 HotpluggableCPUList *head = NULL; 678 MachineClass *mc = MACHINE_GET_CLASS(machine); 679 680 /* force board to initialize possible_cpus if it hasn't been done yet */ 681 mc->possible_cpu_arch_ids(machine); 682 683 for (i = 0; i < machine->possible_cpus->len; i++) { 684 Object *cpu; 685 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); 686 687 cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type); 688 cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count; 689 cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props, 690 sizeof(*cpu_item->props)); 691 692 cpu = machine->possible_cpus->cpus[i].cpu; 693 if (cpu) { 694 cpu_item->qom_path = object_get_canonical_path(cpu); 695 } 696 QAPI_LIST_PREPEND(head, cpu_item); 697 } 698 return head; 699 } 700 701 /** 702 * machine_set_cpu_numa_node: 703 * @machine: machine object to modify 704 * @props: specifies which cpu objects to assign to 705 * numa node specified by @props.node_id 706 * @errp: if an error occurs, a pointer to an area to store the error 707 * 708 * Associate NUMA node specified by @props.node_id with cpu slots that 709 * match socket/core/thread-ids specified by @props. It's recommended to use 710 * query-hotpluggable-cpus.props values to specify affected cpu slots, 711 * which would lead to exact 1:1 mapping of cpu slots to NUMA node. 712 * 713 * However for CLI convenience it's possible to pass in subset of properties, 714 * which would affect all cpu slots that match it. 715 * Ex for pc machine: 716 * -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \ 717 * -numa cpu,node-id=0,socket_id=0 \ 718 * -numa cpu,node-id=1,socket_id=1 719 * will assign all child cores of socket 0 to node 0 and 720 * of socket 1 to node 1. 721 * 722 * On attempt of reassigning (already assigned) cpu slot to another NUMA node, 723 * return error. 724 * Empty subset is disallowed and function will return with error in this case. 725 */ 726 void machine_set_cpu_numa_node(MachineState *machine, 727 const CpuInstanceProperties *props, Error **errp) 728 { 729 MachineClass *mc = MACHINE_GET_CLASS(machine); 730 NodeInfo *numa_info = machine->numa_state->nodes; 731 bool match = false; 732 int i; 733 734 if (!mc->possible_cpu_arch_ids) { 735 error_setg(errp, "mapping of CPUs to NUMA node is not supported"); 736 return; 737 } 738 739 /* disabling node mapping is not supported, forbid it */ 740 assert(props->has_node_id); 741 742 /* force board to initialize possible_cpus if it hasn't been done yet */ 743 mc->possible_cpu_arch_ids(machine); 744 745 for (i = 0; i < machine->possible_cpus->len; i++) { 746 CPUArchId *slot = &machine->possible_cpus->cpus[i]; 747 748 /* reject unsupported by board properties */ 749 if (props->has_thread_id && !slot->props.has_thread_id) { 750 error_setg(errp, "thread-id is not supported"); 751 return; 752 } 753 754 if (props->has_core_id && !slot->props.has_core_id) { 755 error_setg(errp, "core-id is not supported"); 756 return; 757 } 758 759 if (props->has_cluster_id && !slot->props.has_cluster_id) { 760 error_setg(errp, "cluster-id is not supported"); 761 return; 762 } 763 764 if (props->has_socket_id && !slot->props.has_socket_id) { 765 error_setg(errp, "socket-id is not supported"); 766 return; 767 } 768 769 if (props->has_die_id && !slot->props.has_die_id) { 770 error_setg(errp, "die-id is not supported"); 771 return; 772 } 773 774 /* skip slots with explicit mismatch */ 775 if (props->has_thread_id && props->thread_id != slot->props.thread_id) { 776 continue; 777 } 778 779 if (props->has_core_id && props->core_id != slot->props.core_id) { 780 continue; 781 } 782 783 if (props->has_cluster_id && 784 props->cluster_id != slot->props.cluster_id) { 785 continue; 786 } 787 788 if (props->has_die_id && props->die_id != slot->props.die_id) { 789 continue; 790 } 791 792 if (props->has_socket_id && props->socket_id != slot->props.socket_id) { 793 continue; 794 } 795 796 /* reject assignment if slot is already assigned, for compatibility 797 * of legacy cpu_index mapping with SPAPR core based mapping do not 798 * error out if cpu thread and matched core have the same node-id */ 799 if (slot->props.has_node_id && 800 slot->props.node_id != props->node_id) { 801 error_setg(errp, "CPU is already assigned to node-id: %" PRId64, 802 slot->props.node_id); 803 return; 804 } 805 806 /* assign slot to node as it's matched '-numa cpu' key */ 807 match = true; 808 slot->props.node_id = props->node_id; 809 slot->props.has_node_id = props->has_node_id; 810 811 if (machine->numa_state->hmat_enabled) { 812 if ((numa_info[props->node_id].initiator < MAX_NODES) && 813 (props->node_id != numa_info[props->node_id].initiator)) { 814 error_setg(errp, "The initiator of CPU NUMA node %" PRId64 815 " should be itself (got %" PRIu16 ")", 816 props->node_id, numa_info[props->node_id].initiator); 817 return; 818 } 819 numa_info[props->node_id].has_cpu = true; 820 numa_info[props->node_id].initiator = props->node_id; 821 } 822 } 823 824 if (!match) { 825 error_setg(errp, "no match found"); 826 } 827 } 828 829 static void machine_get_smp(Object *obj, Visitor *v, const char *name, 830 void *opaque, Error **errp) 831 { 832 MachineState *ms = MACHINE(obj); 833 SMPConfiguration *config = &(SMPConfiguration){ 834 .has_cpus = true, .cpus = ms->smp.cpus, 835 .has_sockets = true, .sockets = ms->smp.sockets, 836 .has_dies = true, .dies = ms->smp.dies, 837 .has_clusters = true, .clusters = ms->smp.clusters, 838 .has_cores = true, .cores = ms->smp.cores, 839 .has_threads = true, .threads = ms->smp.threads, 840 .has_maxcpus = true, .maxcpus = ms->smp.max_cpus, 841 }; 842 843 if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) { 844 return; 845 } 846 } 847 848 static void machine_set_smp(Object *obj, Visitor *v, const char *name, 849 void *opaque, Error **errp) 850 { 851 MachineState *ms = MACHINE(obj); 852 g_autoptr(SMPConfiguration) config = NULL; 853 854 if (!visit_type_SMPConfiguration(v, name, &config, errp)) { 855 return; 856 } 857 858 machine_parse_smp_config(ms, config, errp); 859 } 860 861 static void machine_get_boot(Object *obj, Visitor *v, const char *name, 862 void *opaque, Error **errp) 863 { 864 MachineState *ms = MACHINE(obj); 865 BootConfiguration *config = &ms->boot_config; 866 visit_type_BootConfiguration(v, name, &config, &error_abort); 867 } 868 869 static void machine_free_boot_config(MachineState *ms) 870 { 871 g_free(ms->boot_config.order); 872 g_free(ms->boot_config.once); 873 g_free(ms->boot_config.splash); 874 } 875 876 static void machine_copy_boot_config(MachineState *ms, BootConfiguration *config) 877 { 878 MachineClass *machine_class = MACHINE_GET_CLASS(ms); 879 880 machine_free_boot_config(ms); 881 ms->boot_config = *config; 882 if (!config->order) { 883 ms->boot_config.order = g_strdup(machine_class->default_boot_order); 884 } 885 } 886 887 static void machine_set_boot(Object *obj, Visitor *v, const char *name, 888 void *opaque, Error **errp) 889 { 890 ERRP_GUARD(); 891 MachineState *ms = MACHINE(obj); 892 BootConfiguration *config = NULL; 893 894 if (!visit_type_BootConfiguration(v, name, &config, errp)) { 895 return; 896 } 897 if (config->order) { 898 validate_bootdevices(config->order, errp); 899 if (*errp) { 900 goto out_free; 901 } 902 } 903 if (config->once) { 904 validate_bootdevices(config->once, errp); 905 if (*errp) { 906 goto out_free; 907 } 908 } 909 910 machine_copy_boot_config(ms, config); 911 /* Strings live in ms->boot_config. */ 912 free(config); 913 return; 914 915 out_free: 916 qapi_free_BootConfiguration(config); 917 } 918 919 static void machine_class_init(ObjectClass *oc, void *data) 920 { 921 MachineClass *mc = MACHINE_CLASS(oc); 922 923 /* Default 128 MB as guest ram size */ 924 mc->default_ram_size = 128 * MiB; 925 mc->rom_file_has_mr = true; 926 927 /* numa node memory size aligned on 8MB by default. 928 * On Linux, each node's border has to be 8MB aligned 929 */ 930 mc->numa_mem_align_shift = 23; 931 932 object_class_property_add_str(oc, "kernel", 933 machine_get_kernel, machine_set_kernel); 934 object_class_property_set_description(oc, "kernel", 935 "Linux kernel image file"); 936 937 object_class_property_add_str(oc, "initrd", 938 machine_get_initrd, machine_set_initrd); 939 object_class_property_set_description(oc, "initrd", 940 "Linux initial ramdisk file"); 941 942 object_class_property_add_str(oc, "append", 943 machine_get_append, machine_set_append); 944 object_class_property_set_description(oc, "append", 945 "Linux kernel command line"); 946 947 object_class_property_add_str(oc, "dtb", 948 machine_get_dtb, machine_set_dtb); 949 object_class_property_set_description(oc, "dtb", 950 "Linux kernel device tree file"); 951 952 object_class_property_add_str(oc, "dumpdtb", 953 machine_get_dumpdtb, machine_set_dumpdtb); 954 object_class_property_set_description(oc, "dumpdtb", 955 "Dump current dtb to a file and quit"); 956 957 object_class_property_add(oc, "boot", "BootConfiguration", 958 machine_get_boot, machine_set_boot, 959 NULL, NULL); 960 object_class_property_set_description(oc, "boot", 961 "Boot configuration"); 962 963 object_class_property_add(oc, "smp", "SMPConfiguration", 964 machine_get_smp, machine_set_smp, 965 NULL, NULL); 966 object_class_property_set_description(oc, "smp", 967 "CPU topology"); 968 969 object_class_property_add(oc, "phandle-start", "int", 970 machine_get_phandle_start, machine_set_phandle_start, 971 NULL, NULL); 972 object_class_property_set_description(oc, "phandle-start", 973 "The first phandle ID we may generate dynamically"); 974 975 object_class_property_add_str(oc, "dt-compatible", 976 machine_get_dt_compatible, machine_set_dt_compatible); 977 object_class_property_set_description(oc, "dt-compatible", 978 "Overrides the \"compatible\" property of the dt root node"); 979 980 object_class_property_add_bool(oc, "dump-guest-core", 981 machine_get_dump_guest_core, machine_set_dump_guest_core); 982 object_class_property_set_description(oc, "dump-guest-core", 983 "Include guest memory in a core dump"); 984 985 object_class_property_add_bool(oc, "mem-merge", 986 machine_get_mem_merge, machine_set_mem_merge); 987 object_class_property_set_description(oc, "mem-merge", 988 "Enable/disable memory merge support"); 989 990 object_class_property_add_bool(oc, "usb", 991 machine_get_usb, machine_set_usb); 992 object_class_property_set_description(oc, "usb", 993 "Set on/off to enable/disable usb"); 994 995 object_class_property_add_bool(oc, "graphics", 996 machine_get_graphics, machine_set_graphics); 997 object_class_property_set_description(oc, "graphics", 998 "Set on/off to enable/disable graphics emulation"); 999 1000 object_class_property_add_str(oc, "firmware", 1001 machine_get_firmware, machine_set_firmware); 1002 object_class_property_set_description(oc, "firmware", 1003 "Firmware image"); 1004 1005 object_class_property_add_bool(oc, "suppress-vmdesc", 1006 machine_get_suppress_vmdesc, machine_set_suppress_vmdesc); 1007 object_class_property_set_description(oc, "suppress-vmdesc", 1008 "Set on to disable self-describing migration"); 1009 1010 object_class_property_add_link(oc, "confidential-guest-support", 1011 TYPE_CONFIDENTIAL_GUEST_SUPPORT, 1012 offsetof(MachineState, cgs), 1013 machine_check_confidential_guest_support, 1014 OBJ_PROP_LINK_STRONG); 1015 object_class_property_set_description(oc, "confidential-guest-support", 1016 "Set confidential guest scheme to support"); 1017 1018 /* For compatibility */ 1019 object_class_property_add_str(oc, "memory-encryption", 1020 machine_get_memory_encryption, machine_set_memory_encryption); 1021 object_class_property_set_description(oc, "memory-encryption", 1022 "Set memory encryption object to use"); 1023 1024 object_class_property_add_link(oc, "memory-backend", TYPE_MEMORY_BACKEND, 1025 offsetof(MachineState, memdev), object_property_allow_set_link, 1026 OBJ_PROP_LINK_STRONG); 1027 object_class_property_set_description(oc, "memory-backend", 1028 "Set RAM backend" 1029 "Valid value is ID of hostmem based backend"); 1030 1031 object_class_property_add(oc, "memory", "MemorySizeConfiguration", 1032 machine_get_mem, machine_set_mem, 1033 NULL, NULL); 1034 object_class_property_set_description(oc, "memory", 1035 "Memory size configuration"); 1036 } 1037 1038 static void machine_class_base_init(ObjectClass *oc, void *data) 1039 { 1040 MachineClass *mc = MACHINE_CLASS(oc); 1041 mc->max_cpus = mc->max_cpus ?: 1; 1042 mc->min_cpus = mc->min_cpus ?: 1; 1043 mc->default_cpus = mc->default_cpus ?: 1; 1044 1045 if (!object_class_is_abstract(oc)) { 1046 const char *cname = object_class_get_name(oc); 1047 assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX)); 1048 mc->name = g_strndup(cname, 1049 strlen(cname) - strlen(TYPE_MACHINE_SUFFIX)); 1050 mc->compat_props = g_ptr_array_new(); 1051 } 1052 } 1053 1054 static void machine_initfn(Object *obj) 1055 { 1056 MachineState *ms = MACHINE(obj); 1057 MachineClass *mc = MACHINE_GET_CLASS(obj); 1058 1059 container_get(obj, "/peripheral"); 1060 container_get(obj, "/peripheral-anon"); 1061 1062 ms->dump_guest_core = true; 1063 ms->mem_merge = true; 1064 ms->enable_graphics = true; 1065 ms->kernel_cmdline = g_strdup(""); 1066 ms->ram_size = mc->default_ram_size; 1067 ms->maxram_size = mc->default_ram_size; 1068 1069 if (mc->nvdimm_supported) { 1070 Object *obj = OBJECT(ms); 1071 1072 ms->nvdimms_state = g_new0(NVDIMMState, 1); 1073 object_property_add_bool(obj, "nvdimm", 1074 machine_get_nvdimm, machine_set_nvdimm); 1075 object_property_set_description(obj, "nvdimm", 1076 "Set on/off to enable/disable " 1077 "NVDIMM instantiation"); 1078 1079 object_property_add_str(obj, "nvdimm-persistence", 1080 machine_get_nvdimm_persistence, 1081 machine_set_nvdimm_persistence); 1082 object_property_set_description(obj, "nvdimm-persistence", 1083 "Set NVDIMM persistence" 1084 "Valid values are cpu, mem-ctrl"); 1085 } 1086 1087 if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { 1088 ms->numa_state = g_new0(NumaState, 1); 1089 object_property_add_bool(obj, "hmat", 1090 machine_get_hmat, machine_set_hmat); 1091 object_property_set_description(obj, "hmat", 1092 "Set on/off to enable/disable " 1093 "ACPI Heterogeneous Memory Attribute " 1094 "Table (HMAT)"); 1095 } 1096 1097 /* default to mc->default_cpus */ 1098 ms->smp.cpus = mc->default_cpus; 1099 ms->smp.max_cpus = mc->default_cpus; 1100 ms->smp.sockets = 1; 1101 ms->smp.dies = 1; 1102 ms->smp.clusters = 1; 1103 ms->smp.cores = 1; 1104 ms->smp.threads = 1; 1105 1106 machine_copy_boot_config(ms, &(BootConfiguration){ 0 }); 1107 } 1108 1109 static void machine_finalize(Object *obj) 1110 { 1111 MachineState *ms = MACHINE(obj); 1112 1113 machine_free_boot_config(ms); 1114 g_free(ms->kernel_filename); 1115 g_free(ms->initrd_filename); 1116 g_free(ms->kernel_cmdline); 1117 g_free(ms->dtb); 1118 g_free(ms->dumpdtb); 1119 g_free(ms->dt_compatible); 1120 g_free(ms->firmware); 1121 g_free(ms->device_memory); 1122 g_free(ms->nvdimms_state); 1123 g_free(ms->numa_state); 1124 } 1125 1126 bool machine_usb(MachineState *machine) 1127 { 1128 return machine->usb; 1129 } 1130 1131 int machine_phandle_start(MachineState *machine) 1132 { 1133 return machine->phandle_start; 1134 } 1135 1136 bool machine_dump_guest_core(MachineState *machine) 1137 { 1138 return machine->dump_guest_core; 1139 } 1140 1141 bool machine_mem_merge(MachineState *machine) 1142 { 1143 return machine->mem_merge; 1144 } 1145 1146 static char *cpu_slot_to_string(const CPUArchId *cpu) 1147 { 1148 GString *s = g_string_new(NULL); 1149 if (cpu->props.has_socket_id) { 1150 g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id); 1151 } 1152 if (cpu->props.has_die_id) { 1153 if (s->len) { 1154 g_string_append_printf(s, ", "); 1155 } 1156 g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); 1157 } 1158 if (cpu->props.has_cluster_id) { 1159 if (s->len) { 1160 g_string_append_printf(s, ", "); 1161 } 1162 g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id); 1163 } 1164 if (cpu->props.has_core_id) { 1165 if (s->len) { 1166 g_string_append_printf(s, ", "); 1167 } 1168 g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id); 1169 } 1170 if (cpu->props.has_thread_id) { 1171 if (s->len) { 1172 g_string_append_printf(s, ", "); 1173 } 1174 g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id); 1175 } 1176 return g_string_free(s, false); 1177 } 1178 1179 static void numa_validate_initiator(NumaState *numa_state) 1180 { 1181 int i; 1182 NodeInfo *numa_info = numa_state->nodes; 1183 1184 for (i = 0; i < numa_state->num_nodes; i++) { 1185 if (numa_info[i].initiator == MAX_NODES) { 1186 continue; 1187 } 1188 1189 if (!numa_info[numa_info[i].initiator].present) { 1190 error_report("NUMA node %" PRIu16 " is missing, use " 1191 "'-numa node' option to declare it first", 1192 numa_info[i].initiator); 1193 exit(1); 1194 } 1195 1196 if (!numa_info[numa_info[i].initiator].has_cpu) { 1197 error_report("The initiator of NUMA node %d is invalid", i); 1198 exit(1); 1199 } 1200 } 1201 } 1202 1203 static void machine_numa_finish_cpu_init(MachineState *machine) 1204 { 1205 int i; 1206 bool default_mapping; 1207 GString *s = g_string_new(NULL); 1208 MachineClass *mc = MACHINE_GET_CLASS(machine); 1209 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine); 1210 1211 assert(machine->numa_state->num_nodes); 1212 for (i = 0; i < possible_cpus->len; i++) { 1213 if (possible_cpus->cpus[i].props.has_node_id) { 1214 break; 1215 } 1216 } 1217 default_mapping = (i == possible_cpus->len); 1218 1219 for (i = 0; i < possible_cpus->len; i++) { 1220 const CPUArchId *cpu_slot = &possible_cpus->cpus[i]; 1221 1222 if (!cpu_slot->props.has_node_id) { 1223 /* fetch default mapping from board and enable it */ 1224 CpuInstanceProperties props = cpu_slot->props; 1225 1226 props.node_id = mc->get_default_cpu_node_id(machine, i); 1227 if (!default_mapping) { 1228 /* record slots with not set mapping, 1229 * TODO: make it hard error in future */ 1230 char *cpu_str = cpu_slot_to_string(cpu_slot); 1231 g_string_append_printf(s, "%sCPU %d [%s]", 1232 s->len ? ", " : "", i, cpu_str); 1233 g_free(cpu_str); 1234 1235 /* non mapped cpus used to fallback to node 0 */ 1236 props.node_id = 0; 1237 } 1238 1239 props.has_node_id = true; 1240 machine_set_cpu_numa_node(machine, &props, &error_fatal); 1241 } 1242 } 1243 1244 if (machine->numa_state->hmat_enabled) { 1245 numa_validate_initiator(machine->numa_state); 1246 } 1247 1248 if (s->len && !qtest_enabled()) { 1249 warn_report("CPU(s) not present in any NUMA nodes: %s", 1250 s->str); 1251 warn_report("All CPU(s) up to maxcpus should be described " 1252 "in NUMA config, ability to start up with partial NUMA " 1253 "mappings is obsoleted and will be removed in future"); 1254 } 1255 g_string_free(s, true); 1256 } 1257 1258 MemoryRegion *machine_consume_memdev(MachineState *machine, 1259 HostMemoryBackend *backend) 1260 { 1261 MemoryRegion *ret = host_memory_backend_get_memory(backend); 1262 1263 if (host_memory_backend_is_mapped(backend)) { 1264 error_report("memory backend %s can't be used multiple times.", 1265 object_get_canonical_path_component(OBJECT(backend))); 1266 exit(EXIT_FAILURE); 1267 } 1268 host_memory_backend_set_mapped(backend, true); 1269 vmstate_register_ram_global(ret); 1270 return ret; 1271 } 1272 1273 static bool create_default_memdev(MachineState *ms, const char *path, Error **errp) 1274 { 1275 Object *obj; 1276 MachineClass *mc = MACHINE_GET_CLASS(ms); 1277 bool r = false; 1278 1279 obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM); 1280 if (path) { 1281 if (!object_property_set_str(obj, "mem-path", path, errp)) { 1282 goto out; 1283 } 1284 } 1285 if (!object_property_set_int(obj, "size", ms->ram_size, errp)) { 1286 goto out; 1287 } 1288 object_property_add_child(object_get_objects_root(), mc->default_ram_id, 1289 obj); 1290 /* Ensure backend's memory region name is equal to mc->default_ram_id */ 1291 if (!object_property_set_bool(obj, "x-use-canonical-path-for-ramblock-id", 1292 false, errp)) { 1293 goto out; 1294 } 1295 if (!user_creatable_complete(USER_CREATABLE(obj), errp)) { 1296 goto out; 1297 } 1298 r = object_property_set_link(OBJECT(ms), "memory-backend", obj, errp); 1299 1300 out: 1301 object_unref(obj); 1302 return r; 1303 } 1304 1305 1306 void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp) 1307 { 1308 MachineClass *machine_class = MACHINE_GET_CLASS(machine); 1309 ObjectClass *oc = object_class_by_name(machine->cpu_type); 1310 CPUClass *cc; 1311 1312 /* This checkpoint is required by replay to separate prior clock 1313 reading from the other reads, because timer polling functions query 1314 clock values from the log. */ 1315 replay_checkpoint(CHECKPOINT_INIT); 1316 1317 if (!xen_enabled()) { 1318 /* On 32-bit hosts, QEMU is limited by virtual address space */ 1319 if (machine->ram_size > (2047 << 20) && HOST_LONG_BITS == 32) { 1320 error_setg(errp, "at most 2047 MB RAM can be simulated"); 1321 return; 1322 } 1323 } 1324 1325 if (machine->memdev) { 1326 ram_addr_t backend_size = object_property_get_uint(OBJECT(machine->memdev), 1327 "size", &error_abort); 1328 if (backend_size != machine->ram_size) { 1329 error_setg(errp, "Machine memory size does not match the size of the memory backend"); 1330 return; 1331 } 1332 } else if (machine_class->default_ram_id && machine->ram_size && 1333 numa_uses_legacy_mem()) { 1334 if (!create_default_memdev(current_machine, mem_path, errp)) { 1335 return; 1336 } 1337 } 1338 1339 if (machine->numa_state) { 1340 numa_complete_configuration(machine); 1341 if (machine->numa_state->num_nodes) { 1342 machine_numa_finish_cpu_init(machine); 1343 } 1344 } 1345 1346 if (!machine->ram && machine->memdev) { 1347 machine->ram = machine_consume_memdev(machine, machine->memdev); 1348 } 1349 1350 /* If the machine supports the valid_cpu_types check and the user 1351 * specified a CPU with -cpu check here that the user CPU is supported. 1352 */ 1353 if (machine_class->valid_cpu_types && machine->cpu_type) { 1354 int i; 1355 1356 for (i = 0; machine_class->valid_cpu_types[i]; i++) { 1357 if (object_class_dynamic_cast(oc, 1358 machine_class->valid_cpu_types[i])) { 1359 /* The user specificed CPU is in the valid field, we are 1360 * good to go. 1361 */ 1362 break; 1363 } 1364 } 1365 1366 if (!machine_class->valid_cpu_types[i]) { 1367 /* The user specified CPU is not valid */ 1368 error_report("Invalid CPU type: %s", machine->cpu_type); 1369 error_printf("The valid types are: %s", 1370 machine_class->valid_cpu_types[0]); 1371 for (i = 1; machine_class->valid_cpu_types[i]; i++) { 1372 error_printf(", %s", machine_class->valid_cpu_types[i]); 1373 } 1374 error_printf("\n"); 1375 1376 exit(1); 1377 } 1378 } 1379 1380 /* Check if CPU type is deprecated and warn if so */ 1381 cc = CPU_CLASS(oc); 1382 if (cc && cc->deprecation_note) { 1383 warn_report("CPU model %s is deprecated -- %s", machine->cpu_type, 1384 cc->deprecation_note); 1385 } 1386 1387 if (machine->cgs) { 1388 /* 1389 * With confidential guests, the host can't see the real 1390 * contents of RAM, so there's no point in it trying to merge 1391 * areas. 1392 */ 1393 machine_set_mem_merge(OBJECT(machine), false, &error_abort); 1394 1395 /* 1396 * Virtio devices can't count on directly accessing guest 1397 * memory, so they need iommu_platform=on to use normal DMA 1398 * mechanisms. That requires also disabling legacy virtio 1399 * support for those virtio pci devices which allow it. 1400 */ 1401 object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy", 1402 "on", true); 1403 object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform", 1404 "on", false); 1405 } 1406 1407 accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator)); 1408 machine_class->init(machine); 1409 phase_advance(PHASE_MACHINE_INITIALIZED); 1410 } 1411 1412 static NotifierList machine_init_done_notifiers = 1413 NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers); 1414 1415 void qemu_add_machine_init_done_notifier(Notifier *notify) 1416 { 1417 notifier_list_add(&machine_init_done_notifiers, notify); 1418 if (phase_check(PHASE_MACHINE_READY)) { 1419 notify->notify(notify, NULL); 1420 } 1421 } 1422 1423 void qemu_remove_machine_init_done_notifier(Notifier *notify) 1424 { 1425 notifier_remove(notify); 1426 } 1427 1428 void qdev_machine_creation_done(void) 1429 { 1430 cpu_synchronize_all_post_init(); 1431 1432 if (current_machine->boot_config.once) { 1433 qemu_boot_set(current_machine->boot_config.once, &error_fatal); 1434 qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_config.order)); 1435 } 1436 1437 /* 1438 * ok, initial machine setup is done, starting from now we can 1439 * only create hotpluggable devices 1440 */ 1441 phase_advance(PHASE_MACHINE_READY); 1442 qdev_assert_realized_properly(); 1443 1444 /* TODO: once all bus devices are qdevified, this should be done 1445 * when bus is created by qdev.c */ 1446 /* 1447 * TODO: If we had a main 'reset container' that the whole system 1448 * lived in, we could reset that using the multi-phase reset 1449 * APIs. For the moment, we just reset the sysbus, which will cause 1450 * all devices hanging off it (and all their child buses, recursively) 1451 * to be reset. Note that this will *not* reset any Device objects 1452 * which are not attached to some part of the qbus tree! 1453 */ 1454 qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default()); 1455 1456 notifier_list_notify(&machine_init_done_notifiers, NULL); 1457 1458 if (rom_check_and_register_reset() != 0) { 1459 exit(1); 1460 } 1461 1462 replay_start(); 1463 1464 /* This checkpoint is required by replay to separate prior clock 1465 reading from the other reads, because timer polling functions query 1466 clock values from the log. */ 1467 replay_checkpoint(CHECKPOINT_RESET); 1468 qemu_system_reset(SHUTDOWN_CAUSE_NONE); 1469 register_global_state(); 1470 } 1471 1472 static const TypeInfo machine_info = { 1473 .name = TYPE_MACHINE, 1474 .parent = TYPE_OBJECT, 1475 .abstract = true, 1476 .class_size = sizeof(MachineClass), 1477 .class_init = machine_class_init, 1478 .class_base_init = machine_class_base_init, 1479 .instance_size = sizeof(MachineState), 1480 .instance_init = machine_initfn, 1481 .instance_finalize = machine_finalize, 1482 }; 1483 1484 static void machine_register_types(void) 1485 { 1486 type_register_static(&machine_info); 1487 } 1488 1489 type_init(machine_register_types) 1490