1 /* 2 * QEMU Machine 3 * 4 * Copyright (C) 2014 Red Hat Inc 5 * 6 * Authors: 7 * Marcel Apfelbaum <marcel.a@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/option.h" 15 #include "qapi/qmp/qerror.h" 16 #include "sysemu/replay.h" 17 #include "qemu/units.h" 18 #include "hw/boards.h" 19 #include "hw/loader.h" 20 #include "qapi/error.h" 21 #include "qapi/qapi-visit-common.h" 22 #include "qapi/qapi-visit-machine.h" 23 #include "qapi/visitor.h" 24 #include "qom/object_interfaces.h" 25 #include "hw/sysbus.h" 26 #include "sysemu/cpus.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/numa.h" 31 #include "sysemu/xen.h" 32 #include "qemu/error-report.h" 33 #include "sysemu/qtest.h" 34 #include "hw/pci/pci.h" 35 #include "hw/mem/nvdimm.h" 36 #include "hw/cxl/cxl.h" 37 #include "migration/global_state.h" 38 #include "migration/vmstate.h" 39 #include "exec/confidential-guest-support.h" 40 #include "hw/virtio/virtio.h" 41 #include "hw/virtio/virtio-pci.h" 42 #include "qom/object_interfaces.h" 43 44 GlobalProperty hw_compat_7_0[] = {}; 45 const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0); 46 47 GlobalProperty hw_compat_6_2[] = { 48 { "PIIX4_PM", "x-not-migrate-acpi-index", "on"}, 49 }; 50 const size_t hw_compat_6_2_len = G_N_ELEMENTS(hw_compat_6_2); 51 52 GlobalProperty hw_compat_6_1[] = { 53 { "vhost-user-vsock-device", "seqpacket", "off" }, 54 { "nvme-ns", "shared", "off" }, 55 }; 56 const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1); 57 58 GlobalProperty hw_compat_6_0[] = { 59 { "gpex-pcihost", "allow-unmapped-accesses", "false" }, 60 { "i8042", "extended-state", "false"}, 61 { "nvme-ns", "eui64-default", "off"}, 62 { "e1000", "init-vet", "off" }, 63 { "e1000e", "init-vet", "off" }, 64 { "vhost-vsock-device", "seqpacket", "off" }, 65 }; 66 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0); 67 68 GlobalProperty hw_compat_5_2[] = { 69 { "ICH9-LPC", "smm-compat", "on"}, 70 { "PIIX4_PM", "smm-compat", "on"}, 71 { "virtio-blk-device", "report-discard-granularity", "off" }, 72 { "virtio-net-pci-base", "vectors", "3"}, 73 }; 74 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2); 75 76 GlobalProperty hw_compat_5_1[] = { 77 { "vhost-scsi", "num_queues", "1"}, 78 { "vhost-user-blk", "num-queues", "1"}, 79 { "vhost-user-scsi", "num_queues", "1"}, 80 { "virtio-blk-device", "num-queues", "1"}, 81 { "virtio-scsi-device", "num_queues", "1"}, 82 { "nvme", "use-intel-id", "on"}, 83 { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */ 84 { "pl011", "migrate-clk", "off" }, 85 { "virtio-pci", "x-ats-page-aligned", "off"}, 86 }; 87 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1); 88 89 GlobalProperty hw_compat_5_0[] = { 90 { "pci-host-bridge", "x-config-reg-migration-enabled", "off" }, 91 { "virtio-balloon-device", "page-poison", "false" }, 92 { "vmport", "x-read-set-eax", "off" }, 93 { "vmport", "x-signal-unsupported-cmd", "off" }, 94 { "vmport", "x-report-vmx-type", "off" }, 95 { "vmport", "x-cmds-v2", "off" }, 96 { "virtio-device", "x-disable-legacy-check", "true" }, 97 }; 98 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0); 99 100 GlobalProperty hw_compat_4_2[] = { 101 { "virtio-blk-device", "queue-size", "128"}, 102 { "virtio-scsi-device", "virtqueue_size", "128"}, 103 { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" }, 104 { "virtio-blk-device", "seg-max-adjust", "off"}, 105 { "virtio-scsi-device", "seg_max_adjust", "off"}, 106 { "vhost-blk-device", "seg_max_adjust", "off"}, 107 { "usb-host", "suppress-remote-wake", "off" }, 108 { "usb-redir", "suppress-remote-wake", "off" }, 109 { "qxl", "revision", "4" }, 110 { "qxl-vga", "revision", "4" }, 111 { "fw_cfg", "acpi-mr-restore", "false" }, 112 { "virtio-device", "use-disabled-flag", "false" }, 113 }; 114 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2); 115 116 GlobalProperty hw_compat_4_1[] = { 117 { "virtio-pci", "x-pcie-flr-init", "off" }, 118 }; 119 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1); 120 121 GlobalProperty hw_compat_4_0[] = { 122 { "VGA", "edid", "false" }, 123 { "secondary-vga", "edid", "false" }, 124 { "bochs-display", "edid", "false" }, 125 { "virtio-vga", "edid", "false" }, 126 { "virtio-gpu-device", "edid", "false" }, 127 { "virtio-device", "use-started", "false" }, 128 { "virtio-balloon-device", "qemu-4-0-config-size", "true" }, 129 { "pl031", "migrate-tick-offset", "false" }, 130 }; 131 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0); 132 133 GlobalProperty hw_compat_3_1[] = { 134 { "pcie-root-port", "x-speed", "2_5" }, 135 { "pcie-root-port", "x-width", "1" }, 136 { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" }, 137 { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" }, 138 { "tpm-crb", "ppi", "false" }, 139 { "tpm-tis", "ppi", "false" }, 140 { "usb-kbd", "serial", "42" }, 141 { "usb-mouse", "serial", "42" }, 142 { "usb-tablet", "serial", "42" }, 143 { "virtio-blk-device", "discard", "false" }, 144 { "virtio-blk-device", "write-zeroes", "false" }, 145 { "virtio-balloon-device", "qemu-4-0-config-size", "false" }, 146 { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */ 147 }; 148 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1); 149 150 GlobalProperty hw_compat_3_0[] = {}; 151 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0); 152 153 GlobalProperty hw_compat_2_12[] = { 154 { "migration", "decompress-error-check", "off" }, 155 { "hda-audio", "use-timer", "false" }, 156 { "cirrus-vga", "global-vmstate", "true" }, 157 { "VGA", "global-vmstate", "true" }, 158 { "vmware-svga", "global-vmstate", "true" }, 159 { "qxl-vga", "global-vmstate", "true" }, 160 }; 161 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12); 162 163 GlobalProperty hw_compat_2_11[] = { 164 { "hpet", "hpet-offset-saved", "false" }, 165 { "virtio-blk-pci", "vectors", "2" }, 166 { "vhost-user-blk-pci", "vectors", "2" }, 167 { "e1000", "migrate_tso_props", "off" }, 168 }; 169 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11); 170 171 GlobalProperty hw_compat_2_10[] = { 172 { "virtio-mouse-device", "wheel-axis", "false" }, 173 { "virtio-tablet-device", "wheel-axis", "false" }, 174 }; 175 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10); 176 177 GlobalProperty hw_compat_2_9[] = { 178 { "pci-bridge", "shpc", "off" }, 179 { "intel-iommu", "pt", "off" }, 180 { "virtio-net-device", "x-mtu-bypass-backend", "off" }, 181 { "pcie-root-port", "x-migrate-msix", "false" }, 182 }; 183 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9); 184 185 GlobalProperty hw_compat_2_8[] = { 186 { "fw_cfg_mem", "x-file-slots", "0x10" }, 187 { "fw_cfg_io", "x-file-slots", "0x10" }, 188 { "pflash_cfi01", "old-multiple-chip-handling", "on" }, 189 { "pci-bridge", "shpc", "on" }, 190 { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" }, 191 { "virtio-pci", "x-pcie-deverr-init", "off" }, 192 { "virtio-pci", "x-pcie-lnkctl-init", "off" }, 193 { "virtio-pci", "x-pcie-pm-init", "off" }, 194 { "cirrus-vga", "vgamem_mb", "8" }, 195 { "isa-cirrus-vga", "vgamem_mb", "8" }, 196 }; 197 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8); 198 199 GlobalProperty hw_compat_2_7[] = { 200 { "virtio-pci", "page-per-vq", "on" }, 201 { "virtio-serial-device", "emergency-write", "off" }, 202 { "ioapic", "version", "0x11" }, 203 { "intel-iommu", "x-buggy-eim", "true" }, 204 { "virtio-pci", "x-ignore-backend-features", "on" }, 205 }; 206 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); 207 208 GlobalProperty hw_compat_2_6[] = { 209 { "virtio-mmio", "format_transport_address", "off" }, 210 /* Optional because not all virtio-pci devices support legacy mode */ 211 { "virtio-pci", "disable-modern", "on", .optional = true }, 212 { "virtio-pci", "disable-legacy", "off", .optional = true }, 213 }; 214 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); 215 216 GlobalProperty hw_compat_2_5[] = { 217 { "isa-fdc", "fallback", "144" }, 218 { "pvscsi", "x-old-pci-configuration", "on" }, 219 { "pvscsi", "x-disable-pcie", "on" }, 220 { "vmxnet3", "x-old-msi-offsets", "on" }, 221 { "vmxnet3", "x-disable-pcie", "on" }, 222 }; 223 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5); 224 225 GlobalProperty hw_compat_2_4[] = { 226 /* Optional because the 'scsi' property is Linux-only */ 227 { "virtio-blk-device", "scsi", "true", .optional = true }, 228 { "e1000", "extra_mac_registers", "off" }, 229 { "virtio-pci", "x-disable-pcie", "on" }, 230 { "virtio-pci", "migrate-extra", "off" }, 231 { "fw_cfg_mem", "dma_enabled", "off" }, 232 { "fw_cfg_io", "dma_enabled", "off" } 233 }; 234 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4); 235 236 GlobalProperty hw_compat_2_3[] = { 237 { "virtio-blk-pci", "any_layout", "off" }, 238 { "virtio-balloon-pci", "any_layout", "off" }, 239 { "virtio-serial-pci", "any_layout", "off" }, 240 { "virtio-9p-pci", "any_layout", "off" }, 241 { "virtio-rng-pci", "any_layout", "off" }, 242 { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" }, 243 { "migration", "send-configuration", "off" }, 244 { "migration", "send-section-footer", "off" }, 245 { "migration", "store-global-state", "off" }, 246 }; 247 const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3); 248 249 GlobalProperty hw_compat_2_2[] = {}; 250 const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2); 251 252 GlobalProperty hw_compat_2_1[] = { 253 { "intel-hda", "old_msi_addr", "on" }, 254 { "VGA", "qemu-extended-regs", "off" }, 255 { "secondary-vga", "qemu-extended-regs", "off" }, 256 { "virtio-scsi-pci", "any_layout", "off" }, 257 { "usb-mouse", "usb_version", "1" }, 258 { "usb-kbd", "usb_version", "1" }, 259 { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" }, 260 }; 261 const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1); 262 263 MachineState *current_machine; 264 265 static char *machine_get_kernel(Object *obj, Error **errp) 266 { 267 MachineState *ms = MACHINE(obj); 268 269 return g_strdup(ms->kernel_filename); 270 } 271 272 static void machine_set_kernel(Object *obj, const char *value, Error **errp) 273 { 274 MachineState *ms = MACHINE(obj); 275 276 g_free(ms->kernel_filename); 277 ms->kernel_filename = g_strdup(value); 278 } 279 280 static char *machine_get_initrd(Object *obj, Error **errp) 281 { 282 MachineState *ms = MACHINE(obj); 283 284 return g_strdup(ms->initrd_filename); 285 } 286 287 static void machine_set_initrd(Object *obj, const char *value, Error **errp) 288 { 289 MachineState *ms = MACHINE(obj); 290 291 g_free(ms->initrd_filename); 292 ms->initrd_filename = g_strdup(value); 293 } 294 295 static char *machine_get_append(Object *obj, Error **errp) 296 { 297 MachineState *ms = MACHINE(obj); 298 299 return g_strdup(ms->kernel_cmdline); 300 } 301 302 static void machine_set_append(Object *obj, const char *value, Error **errp) 303 { 304 MachineState *ms = MACHINE(obj); 305 306 g_free(ms->kernel_cmdline); 307 ms->kernel_cmdline = g_strdup(value); 308 } 309 310 static char *machine_get_dtb(Object *obj, Error **errp) 311 { 312 MachineState *ms = MACHINE(obj); 313 314 return g_strdup(ms->dtb); 315 } 316 317 static void machine_set_dtb(Object *obj, const char *value, Error **errp) 318 { 319 MachineState *ms = MACHINE(obj); 320 321 g_free(ms->dtb); 322 ms->dtb = g_strdup(value); 323 } 324 325 static char *machine_get_dumpdtb(Object *obj, Error **errp) 326 { 327 MachineState *ms = MACHINE(obj); 328 329 return g_strdup(ms->dumpdtb); 330 } 331 332 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp) 333 { 334 MachineState *ms = MACHINE(obj); 335 336 g_free(ms->dumpdtb); 337 ms->dumpdtb = g_strdup(value); 338 } 339 340 static void machine_get_phandle_start(Object *obj, Visitor *v, 341 const char *name, void *opaque, 342 Error **errp) 343 { 344 MachineState *ms = MACHINE(obj); 345 int64_t value = ms->phandle_start; 346 347 visit_type_int(v, name, &value, errp); 348 } 349 350 static void machine_set_phandle_start(Object *obj, Visitor *v, 351 const char *name, void *opaque, 352 Error **errp) 353 { 354 MachineState *ms = MACHINE(obj); 355 int64_t value; 356 357 if (!visit_type_int(v, name, &value, errp)) { 358 return; 359 } 360 361 ms->phandle_start = value; 362 } 363 364 static char *machine_get_dt_compatible(Object *obj, Error **errp) 365 { 366 MachineState *ms = MACHINE(obj); 367 368 return g_strdup(ms->dt_compatible); 369 } 370 371 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp) 372 { 373 MachineState *ms = MACHINE(obj); 374 375 g_free(ms->dt_compatible); 376 ms->dt_compatible = g_strdup(value); 377 } 378 379 static bool machine_get_dump_guest_core(Object *obj, Error **errp) 380 { 381 MachineState *ms = MACHINE(obj); 382 383 return ms->dump_guest_core; 384 } 385 386 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp) 387 { 388 MachineState *ms = MACHINE(obj); 389 390 ms->dump_guest_core = value; 391 } 392 393 static bool machine_get_mem_merge(Object *obj, Error **errp) 394 { 395 MachineState *ms = MACHINE(obj); 396 397 return ms->mem_merge; 398 } 399 400 static void machine_set_mem_merge(Object *obj, bool value, Error **errp) 401 { 402 MachineState *ms = MACHINE(obj); 403 404 ms->mem_merge = value; 405 } 406 407 static bool machine_get_usb(Object *obj, Error **errp) 408 { 409 MachineState *ms = MACHINE(obj); 410 411 return ms->usb; 412 } 413 414 static void machine_set_usb(Object *obj, bool value, Error **errp) 415 { 416 MachineState *ms = MACHINE(obj); 417 418 ms->usb = value; 419 ms->usb_disabled = !value; 420 } 421 422 static bool machine_get_graphics(Object *obj, Error **errp) 423 { 424 MachineState *ms = MACHINE(obj); 425 426 return ms->enable_graphics; 427 } 428 429 static void machine_set_graphics(Object *obj, bool value, Error **errp) 430 { 431 MachineState *ms = MACHINE(obj); 432 433 ms->enable_graphics = value; 434 } 435 436 static char *machine_get_firmware(Object *obj, Error **errp) 437 { 438 MachineState *ms = MACHINE(obj); 439 440 return g_strdup(ms->firmware); 441 } 442 443 static void machine_set_firmware(Object *obj, const char *value, Error **errp) 444 { 445 MachineState *ms = MACHINE(obj); 446 447 g_free(ms->firmware); 448 ms->firmware = g_strdup(value); 449 } 450 451 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp) 452 { 453 MachineState *ms = MACHINE(obj); 454 455 ms->suppress_vmdesc = value; 456 } 457 458 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp) 459 { 460 MachineState *ms = MACHINE(obj); 461 462 return ms->suppress_vmdesc; 463 } 464 465 static char *machine_get_memory_encryption(Object *obj, Error **errp) 466 { 467 MachineState *ms = MACHINE(obj); 468 469 if (ms->cgs) { 470 return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs))); 471 } 472 473 return NULL; 474 } 475 476 static void machine_set_memory_encryption(Object *obj, const char *value, 477 Error **errp) 478 { 479 Object *cgs = 480 object_resolve_path_component(object_get_objects_root(), value); 481 482 if (!cgs) { 483 error_setg(errp, "No such memory encryption object '%s'", value); 484 return; 485 } 486 487 object_property_set_link(obj, "confidential-guest-support", cgs, errp); 488 } 489 490 static void machine_check_confidential_guest_support(const Object *obj, 491 const char *name, 492 Object *new_target, 493 Error **errp) 494 { 495 /* 496 * So far the only constraint is that the target has the 497 * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked 498 * by the QOM core 499 */ 500 } 501 502 static bool machine_get_nvdimm(Object *obj, Error **errp) 503 { 504 MachineState *ms = MACHINE(obj); 505 506 return ms->nvdimms_state->is_enabled; 507 } 508 509 static void machine_set_nvdimm(Object *obj, bool value, Error **errp) 510 { 511 MachineState *ms = MACHINE(obj); 512 513 ms->nvdimms_state->is_enabled = value; 514 } 515 516 static bool machine_get_hmat(Object *obj, Error **errp) 517 { 518 MachineState *ms = MACHINE(obj); 519 520 return ms->numa_state->hmat_enabled; 521 } 522 523 static void machine_set_hmat(Object *obj, bool value, Error **errp) 524 { 525 MachineState *ms = MACHINE(obj); 526 527 ms->numa_state->hmat_enabled = value; 528 } 529 530 static void machine_get_mem(Object *obj, Visitor *v, const char *name, 531 void *opaque, Error **errp) 532 { 533 MachineState *ms = MACHINE(obj); 534 MemorySizeConfiguration mem = { 535 .has_size = true, 536 .size = ms->ram_size, 537 .has_max_size = !!ms->ram_slots, 538 .max_size = ms->maxram_size, 539 .has_slots = !!ms->ram_slots, 540 .slots = ms->ram_slots, 541 }; 542 MemorySizeConfiguration *p_mem = &mem; 543 544 visit_type_MemorySizeConfiguration(v, name, &p_mem, &error_abort); 545 } 546 547 static void machine_set_mem(Object *obj, Visitor *v, const char *name, 548 void *opaque, Error **errp) 549 { 550 MachineState *ms = MACHINE(obj); 551 MachineClass *mc = MACHINE_GET_CLASS(obj); 552 MemorySizeConfiguration *mem; 553 554 ERRP_GUARD(); 555 556 if (!visit_type_MemorySizeConfiguration(v, name, &mem, errp)) { 557 return; 558 } 559 560 if (!mem->has_size) { 561 mem->has_size = true; 562 mem->size = mc->default_ram_size; 563 } 564 mem->size = QEMU_ALIGN_UP(mem->size, 8192); 565 if (mc->fixup_ram_size) { 566 mem->size = mc->fixup_ram_size(mem->size); 567 } 568 if ((ram_addr_t)mem->size != mem->size) { 569 error_setg(errp, "ram size too large"); 570 goto out_free; 571 } 572 573 if (mem->has_max_size) { 574 if (mem->max_size < mem->size) { 575 error_setg(errp, "invalid value of maxmem: " 576 "maximum memory size (0x%" PRIx64 ") must be at least " 577 "the initial memory size (0x%" PRIx64 ")", 578 mem->max_size, mem->size); 579 goto out_free; 580 } 581 if (mem->has_slots && mem->slots && mem->max_size == mem->size) { 582 error_setg(errp, "invalid value of maxmem: " 583 "memory slots were specified but maximum memory size " 584 "(0x%" PRIx64 ") is equal to the initial memory size " 585 "(0x%" PRIx64 ")", mem->max_size, mem->size); 586 goto out_free; 587 } 588 ms->maxram_size = mem->max_size; 589 } else { 590 if (mem->has_slots) { 591 error_setg(errp, "slots specified but no max-size"); 592 goto out_free; 593 } 594 ms->maxram_size = mem->size; 595 } 596 ms->ram_size = mem->size; 597 ms->ram_slots = mem->has_slots ? mem->slots : 0; 598 out_free: 599 qapi_free_MemorySizeConfiguration(mem); 600 } 601 602 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp) 603 { 604 MachineState *ms = MACHINE(obj); 605 606 return g_strdup(ms->nvdimms_state->persistence_string); 607 } 608 609 static void machine_set_nvdimm_persistence(Object *obj, const char *value, 610 Error **errp) 611 { 612 MachineState *ms = MACHINE(obj); 613 NVDIMMState *nvdimms_state = ms->nvdimms_state; 614 615 if (strcmp(value, "cpu") == 0) { 616 nvdimms_state->persistence = 3; 617 } else if (strcmp(value, "mem-ctrl") == 0) { 618 nvdimms_state->persistence = 2; 619 } else { 620 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option", 621 value); 622 return; 623 } 624 625 g_free(nvdimms_state->persistence_string); 626 nvdimms_state->persistence_string = g_strdup(value); 627 } 628 629 static bool machine_get_cxl(Object *obj, Error **errp) 630 { 631 MachineState *ms = MACHINE(obj); 632 633 return ms->cxl_devices_state->is_enabled; 634 } 635 636 static void machine_set_cxl(Object *obj, bool value, Error **errp) 637 { 638 MachineState *ms = MACHINE(obj); 639 640 ms->cxl_devices_state->is_enabled = value; 641 } 642 643 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type) 644 { 645 QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); 646 } 647 648 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev) 649 { 650 Object *obj = OBJECT(dev); 651 652 if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) { 653 return false; 654 } 655 656 return device_type_is_dynamic_sysbus(mc, object_get_typename(obj)); 657 } 658 659 bool device_type_is_dynamic_sysbus(MachineClass *mc, const char *type) 660 { 661 bool allowed = false; 662 strList *wl; 663 ObjectClass *klass = object_class_by_name(type); 664 665 for (wl = mc->allowed_dynamic_sysbus_devices; 666 !allowed && wl; 667 wl = wl->next) { 668 allowed |= !!object_class_dynamic_cast(klass, wl->value); 669 } 670 671 return allowed; 672 } 673 674 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine) 675 { 676 int i; 677 HotpluggableCPUList *head = NULL; 678 MachineClass *mc = MACHINE_GET_CLASS(machine); 679 680 /* force board to initialize possible_cpus if it hasn't been done yet */ 681 mc->possible_cpu_arch_ids(machine); 682 683 for (i = 0; i < machine->possible_cpus->len; i++) { 684 Object *cpu; 685 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); 686 687 cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type); 688 cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count; 689 cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props, 690 sizeof(*cpu_item->props)); 691 692 cpu = machine->possible_cpus->cpus[i].cpu; 693 if (cpu) { 694 cpu_item->has_qom_path = true; 695 cpu_item->qom_path = object_get_canonical_path(cpu); 696 } 697 QAPI_LIST_PREPEND(head, cpu_item); 698 } 699 return head; 700 } 701 702 /** 703 * machine_set_cpu_numa_node: 704 * @machine: machine object to modify 705 * @props: specifies which cpu objects to assign to 706 * numa node specified by @props.node_id 707 * @errp: if an error occurs, a pointer to an area to store the error 708 * 709 * Associate NUMA node specified by @props.node_id with cpu slots that 710 * match socket/core/thread-ids specified by @props. It's recommended to use 711 * query-hotpluggable-cpus.props values to specify affected cpu slots, 712 * which would lead to exact 1:1 mapping of cpu slots to NUMA node. 713 * 714 * However for CLI convenience it's possible to pass in subset of properties, 715 * which would affect all cpu slots that match it. 716 * Ex for pc machine: 717 * -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \ 718 * -numa cpu,node-id=0,socket_id=0 \ 719 * -numa cpu,node-id=1,socket_id=1 720 * will assign all child cores of socket 0 to node 0 and 721 * of socket 1 to node 1. 722 * 723 * On attempt of reassigning (already assigned) cpu slot to another NUMA node, 724 * return error. 725 * Empty subset is disallowed and function will return with error in this case. 726 */ 727 void machine_set_cpu_numa_node(MachineState *machine, 728 const CpuInstanceProperties *props, Error **errp) 729 { 730 MachineClass *mc = MACHINE_GET_CLASS(machine); 731 NodeInfo *numa_info = machine->numa_state->nodes; 732 bool match = false; 733 int i; 734 735 if (!mc->possible_cpu_arch_ids) { 736 error_setg(errp, "mapping of CPUs to NUMA node is not supported"); 737 return; 738 } 739 740 /* disabling node mapping is not supported, forbid it */ 741 assert(props->has_node_id); 742 743 /* force board to initialize possible_cpus if it hasn't been done yet */ 744 mc->possible_cpu_arch_ids(machine); 745 746 for (i = 0; i < machine->possible_cpus->len; i++) { 747 CPUArchId *slot = &machine->possible_cpus->cpus[i]; 748 749 /* reject unsupported by board properties */ 750 if (props->has_thread_id && !slot->props.has_thread_id) { 751 error_setg(errp, "thread-id is not supported"); 752 return; 753 } 754 755 if (props->has_core_id && !slot->props.has_core_id) { 756 error_setg(errp, "core-id is not supported"); 757 return; 758 } 759 760 if (props->has_cluster_id && !slot->props.has_cluster_id) { 761 error_setg(errp, "cluster-id is not supported"); 762 return; 763 } 764 765 if (props->has_socket_id && !slot->props.has_socket_id) { 766 error_setg(errp, "socket-id is not supported"); 767 return; 768 } 769 770 if (props->has_die_id && !slot->props.has_die_id) { 771 error_setg(errp, "die-id is not supported"); 772 return; 773 } 774 775 /* skip slots with explicit mismatch */ 776 if (props->has_thread_id && props->thread_id != slot->props.thread_id) { 777 continue; 778 } 779 780 if (props->has_core_id && props->core_id != slot->props.core_id) { 781 continue; 782 } 783 784 if (props->has_cluster_id && 785 props->cluster_id != slot->props.cluster_id) { 786 continue; 787 } 788 789 if (props->has_die_id && props->die_id != slot->props.die_id) { 790 continue; 791 } 792 793 if (props->has_socket_id && props->socket_id != slot->props.socket_id) { 794 continue; 795 } 796 797 /* reject assignment if slot is already assigned, for compatibility 798 * of legacy cpu_index mapping with SPAPR core based mapping do not 799 * error out if cpu thread and matched core have the same node-id */ 800 if (slot->props.has_node_id && 801 slot->props.node_id != props->node_id) { 802 error_setg(errp, "CPU is already assigned to node-id: %" PRId64, 803 slot->props.node_id); 804 return; 805 } 806 807 /* assign slot to node as it's matched '-numa cpu' key */ 808 match = true; 809 slot->props.node_id = props->node_id; 810 slot->props.has_node_id = props->has_node_id; 811 812 if (machine->numa_state->hmat_enabled) { 813 if ((numa_info[props->node_id].initiator < MAX_NODES) && 814 (props->node_id != numa_info[props->node_id].initiator)) { 815 error_setg(errp, "The initiator of CPU NUMA node %" PRId64 816 " should be itself (got %" PRIu16 ")", 817 props->node_id, numa_info[props->node_id].initiator); 818 return; 819 } 820 numa_info[props->node_id].has_cpu = true; 821 numa_info[props->node_id].initiator = props->node_id; 822 } 823 } 824 825 if (!match) { 826 error_setg(errp, "no match found"); 827 } 828 } 829 830 static void machine_get_smp(Object *obj, Visitor *v, const char *name, 831 void *opaque, Error **errp) 832 { 833 MachineState *ms = MACHINE(obj); 834 SMPConfiguration *config = &(SMPConfiguration){ 835 .has_cpus = true, .cpus = ms->smp.cpus, 836 .has_sockets = true, .sockets = ms->smp.sockets, 837 .has_dies = true, .dies = ms->smp.dies, 838 .has_clusters = true, .clusters = ms->smp.clusters, 839 .has_cores = true, .cores = ms->smp.cores, 840 .has_threads = true, .threads = ms->smp.threads, 841 .has_maxcpus = true, .maxcpus = ms->smp.max_cpus, 842 }; 843 844 if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) { 845 return; 846 } 847 } 848 849 static void machine_set_smp(Object *obj, Visitor *v, const char *name, 850 void *opaque, Error **errp) 851 { 852 MachineState *ms = MACHINE(obj); 853 g_autoptr(SMPConfiguration) config = NULL; 854 855 if (!visit_type_SMPConfiguration(v, name, &config, errp)) { 856 return; 857 } 858 859 machine_parse_smp_config(ms, config, errp); 860 } 861 862 static void machine_get_boot(Object *obj, Visitor *v, const char *name, 863 void *opaque, Error **errp) 864 { 865 MachineState *ms = MACHINE(obj); 866 BootConfiguration *config = &ms->boot_config; 867 visit_type_BootConfiguration(v, name, &config, &error_abort); 868 } 869 870 static void machine_free_boot_config(MachineState *ms) 871 { 872 g_free(ms->boot_config.order); 873 g_free(ms->boot_config.once); 874 g_free(ms->boot_config.splash); 875 } 876 877 static void machine_copy_boot_config(MachineState *ms, BootConfiguration *config) 878 { 879 MachineClass *machine_class = MACHINE_GET_CLASS(ms); 880 881 machine_free_boot_config(ms); 882 ms->boot_config = *config; 883 if (!config->has_order) { 884 ms->boot_config.has_order = true; 885 ms->boot_config.order = g_strdup(machine_class->default_boot_order); 886 } 887 } 888 889 static void machine_set_boot(Object *obj, Visitor *v, const char *name, 890 void *opaque, Error **errp) 891 { 892 ERRP_GUARD(); 893 MachineState *ms = MACHINE(obj); 894 BootConfiguration *config = NULL; 895 896 if (!visit_type_BootConfiguration(v, name, &config, errp)) { 897 return; 898 } 899 if (config->has_order) { 900 validate_bootdevices(config->order, errp); 901 if (*errp) { 902 goto out_free; 903 } 904 } 905 if (config->has_once) { 906 validate_bootdevices(config->once, errp); 907 if (*errp) { 908 goto out_free; 909 } 910 } 911 912 machine_copy_boot_config(ms, config); 913 /* Strings live in ms->boot_config. */ 914 free(config); 915 return; 916 917 out_free: 918 qapi_free_BootConfiguration(config); 919 } 920 921 static void machine_class_init(ObjectClass *oc, void *data) 922 { 923 MachineClass *mc = MACHINE_CLASS(oc); 924 925 /* Default 128 MB as guest ram size */ 926 mc->default_ram_size = 128 * MiB; 927 mc->rom_file_has_mr = true; 928 929 /* Few machines support CXL, so default to off */ 930 mc->cxl_supported = false; 931 /* numa node memory size aligned on 8MB by default. 932 * On Linux, each node's border has to be 8MB aligned 933 */ 934 mc->numa_mem_align_shift = 23; 935 936 object_class_property_add_str(oc, "kernel", 937 machine_get_kernel, machine_set_kernel); 938 object_class_property_set_description(oc, "kernel", 939 "Linux kernel image file"); 940 941 object_class_property_add_str(oc, "initrd", 942 machine_get_initrd, machine_set_initrd); 943 object_class_property_set_description(oc, "initrd", 944 "Linux initial ramdisk file"); 945 946 object_class_property_add_str(oc, "append", 947 machine_get_append, machine_set_append); 948 object_class_property_set_description(oc, "append", 949 "Linux kernel command line"); 950 951 object_class_property_add_str(oc, "dtb", 952 machine_get_dtb, machine_set_dtb); 953 object_class_property_set_description(oc, "dtb", 954 "Linux kernel device tree file"); 955 956 object_class_property_add_str(oc, "dumpdtb", 957 machine_get_dumpdtb, machine_set_dumpdtb); 958 object_class_property_set_description(oc, "dumpdtb", 959 "Dump current dtb to a file and quit"); 960 961 object_class_property_add(oc, "boot", "BootConfiguration", 962 machine_get_boot, machine_set_boot, 963 NULL, NULL); 964 object_class_property_set_description(oc, "boot", 965 "Boot configuration"); 966 967 object_class_property_add(oc, "smp", "SMPConfiguration", 968 machine_get_smp, machine_set_smp, 969 NULL, NULL); 970 object_class_property_set_description(oc, "smp", 971 "CPU topology"); 972 973 object_class_property_add(oc, "phandle-start", "int", 974 machine_get_phandle_start, machine_set_phandle_start, 975 NULL, NULL); 976 object_class_property_set_description(oc, "phandle-start", 977 "The first phandle ID we may generate dynamically"); 978 979 object_class_property_add_str(oc, "dt-compatible", 980 machine_get_dt_compatible, machine_set_dt_compatible); 981 object_class_property_set_description(oc, "dt-compatible", 982 "Overrides the \"compatible\" property of the dt root node"); 983 984 object_class_property_add_bool(oc, "dump-guest-core", 985 machine_get_dump_guest_core, machine_set_dump_guest_core); 986 object_class_property_set_description(oc, "dump-guest-core", 987 "Include guest memory in a core dump"); 988 989 object_class_property_add_bool(oc, "mem-merge", 990 machine_get_mem_merge, machine_set_mem_merge); 991 object_class_property_set_description(oc, "mem-merge", 992 "Enable/disable memory merge support"); 993 994 object_class_property_add_bool(oc, "usb", 995 machine_get_usb, machine_set_usb); 996 object_class_property_set_description(oc, "usb", 997 "Set on/off to enable/disable usb"); 998 999 object_class_property_add_bool(oc, "graphics", 1000 machine_get_graphics, machine_set_graphics); 1001 object_class_property_set_description(oc, "graphics", 1002 "Set on/off to enable/disable graphics emulation"); 1003 1004 object_class_property_add_str(oc, "firmware", 1005 machine_get_firmware, machine_set_firmware); 1006 object_class_property_set_description(oc, "firmware", 1007 "Firmware image"); 1008 1009 object_class_property_add_bool(oc, "suppress-vmdesc", 1010 machine_get_suppress_vmdesc, machine_set_suppress_vmdesc); 1011 object_class_property_set_description(oc, "suppress-vmdesc", 1012 "Set on to disable self-describing migration"); 1013 1014 object_class_property_add_link(oc, "confidential-guest-support", 1015 TYPE_CONFIDENTIAL_GUEST_SUPPORT, 1016 offsetof(MachineState, cgs), 1017 machine_check_confidential_guest_support, 1018 OBJ_PROP_LINK_STRONG); 1019 object_class_property_set_description(oc, "confidential-guest-support", 1020 "Set confidential guest scheme to support"); 1021 1022 /* For compatibility */ 1023 object_class_property_add_str(oc, "memory-encryption", 1024 machine_get_memory_encryption, machine_set_memory_encryption); 1025 object_class_property_set_description(oc, "memory-encryption", 1026 "Set memory encryption object to use"); 1027 1028 object_class_property_add_link(oc, "memory-backend", TYPE_MEMORY_BACKEND, 1029 offsetof(MachineState, memdev), object_property_allow_set_link, 1030 OBJ_PROP_LINK_STRONG); 1031 object_class_property_set_description(oc, "memory-backend", 1032 "Set RAM backend" 1033 "Valid value is ID of hostmem based backend"); 1034 1035 object_class_property_add(oc, "memory", "MemorySizeConfiguration", 1036 machine_get_mem, machine_set_mem, 1037 NULL, NULL); 1038 object_class_property_set_description(oc, "memory", 1039 "Memory size configuration"); 1040 } 1041 1042 static void machine_class_base_init(ObjectClass *oc, void *data) 1043 { 1044 MachineClass *mc = MACHINE_CLASS(oc); 1045 mc->max_cpus = mc->max_cpus ?: 1; 1046 mc->min_cpus = mc->min_cpus ?: 1; 1047 mc->default_cpus = mc->default_cpus ?: 1; 1048 1049 if (!object_class_is_abstract(oc)) { 1050 const char *cname = object_class_get_name(oc); 1051 assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX)); 1052 mc->name = g_strndup(cname, 1053 strlen(cname) - strlen(TYPE_MACHINE_SUFFIX)); 1054 mc->compat_props = g_ptr_array_new(); 1055 } 1056 } 1057 1058 static void machine_initfn(Object *obj) 1059 { 1060 MachineState *ms = MACHINE(obj); 1061 MachineClass *mc = MACHINE_GET_CLASS(obj); 1062 1063 container_get(obj, "/peripheral"); 1064 container_get(obj, "/peripheral-anon"); 1065 1066 ms->dump_guest_core = true; 1067 ms->mem_merge = true; 1068 ms->enable_graphics = true; 1069 ms->kernel_cmdline = g_strdup(""); 1070 ms->ram_size = mc->default_ram_size; 1071 ms->maxram_size = mc->default_ram_size; 1072 1073 if (mc->nvdimm_supported) { 1074 Object *obj = OBJECT(ms); 1075 1076 ms->nvdimms_state = g_new0(NVDIMMState, 1); 1077 object_property_add_bool(obj, "nvdimm", 1078 machine_get_nvdimm, machine_set_nvdimm); 1079 object_property_set_description(obj, "nvdimm", 1080 "Set on/off to enable/disable " 1081 "NVDIMM instantiation"); 1082 1083 object_property_add_str(obj, "nvdimm-persistence", 1084 machine_get_nvdimm_persistence, 1085 machine_set_nvdimm_persistence); 1086 object_property_set_description(obj, "nvdimm-persistence", 1087 "Set NVDIMM persistence" 1088 "Valid values are cpu, mem-ctrl"); 1089 } 1090 1091 if (mc->cxl_supported) { 1092 Object *obj = OBJECT(ms); 1093 1094 ms->cxl_devices_state = g_new0(CXLState, 1); 1095 object_property_add_bool(obj, "cxl", machine_get_cxl, machine_set_cxl); 1096 object_property_set_description(obj, "cxl", 1097 "Set on/off to enable/disable " 1098 "CXL instantiation"); 1099 } 1100 1101 if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { 1102 ms->numa_state = g_new0(NumaState, 1); 1103 object_property_add_bool(obj, "hmat", 1104 machine_get_hmat, machine_set_hmat); 1105 object_property_set_description(obj, "hmat", 1106 "Set on/off to enable/disable " 1107 "ACPI Heterogeneous Memory Attribute " 1108 "Table (HMAT)"); 1109 } 1110 1111 /* default to mc->default_cpus */ 1112 ms->smp.cpus = mc->default_cpus; 1113 ms->smp.max_cpus = mc->default_cpus; 1114 ms->smp.sockets = 1; 1115 ms->smp.dies = 1; 1116 ms->smp.clusters = 1; 1117 ms->smp.cores = 1; 1118 ms->smp.threads = 1; 1119 1120 machine_copy_boot_config(ms, &(BootConfiguration){ 0 }); 1121 } 1122 1123 static void machine_finalize(Object *obj) 1124 { 1125 MachineState *ms = MACHINE(obj); 1126 1127 machine_free_boot_config(ms); 1128 g_free(ms->kernel_filename); 1129 g_free(ms->initrd_filename); 1130 g_free(ms->kernel_cmdline); 1131 g_free(ms->dtb); 1132 g_free(ms->dumpdtb); 1133 g_free(ms->dt_compatible); 1134 g_free(ms->firmware); 1135 g_free(ms->device_memory); 1136 g_free(ms->nvdimms_state); 1137 g_free(ms->numa_state); 1138 g_free(ms->cxl_devices_state); 1139 } 1140 1141 bool machine_usb(MachineState *machine) 1142 { 1143 return machine->usb; 1144 } 1145 1146 int machine_phandle_start(MachineState *machine) 1147 { 1148 return machine->phandle_start; 1149 } 1150 1151 bool machine_dump_guest_core(MachineState *machine) 1152 { 1153 return machine->dump_guest_core; 1154 } 1155 1156 bool machine_mem_merge(MachineState *machine) 1157 { 1158 return machine->mem_merge; 1159 } 1160 1161 static char *cpu_slot_to_string(const CPUArchId *cpu) 1162 { 1163 GString *s = g_string_new(NULL); 1164 if (cpu->props.has_socket_id) { 1165 g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id); 1166 } 1167 if (cpu->props.has_die_id) { 1168 if (s->len) { 1169 g_string_append_printf(s, ", "); 1170 } 1171 g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); 1172 } 1173 if (cpu->props.has_cluster_id) { 1174 if (s->len) { 1175 g_string_append_printf(s, ", "); 1176 } 1177 g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id); 1178 } 1179 if (cpu->props.has_core_id) { 1180 if (s->len) { 1181 g_string_append_printf(s, ", "); 1182 } 1183 g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id); 1184 } 1185 if (cpu->props.has_thread_id) { 1186 if (s->len) { 1187 g_string_append_printf(s, ", "); 1188 } 1189 g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id); 1190 } 1191 return g_string_free(s, false); 1192 } 1193 1194 static void numa_validate_initiator(NumaState *numa_state) 1195 { 1196 int i; 1197 NodeInfo *numa_info = numa_state->nodes; 1198 1199 for (i = 0; i < numa_state->num_nodes; i++) { 1200 if (numa_info[i].initiator == MAX_NODES) { 1201 error_report("The initiator of NUMA node %d is missing, use " 1202 "'-numa node,initiator' option to declare it", i); 1203 exit(1); 1204 } 1205 1206 if (!numa_info[numa_info[i].initiator].present) { 1207 error_report("NUMA node %" PRIu16 " is missing, use " 1208 "'-numa node' option to declare it first", 1209 numa_info[i].initiator); 1210 exit(1); 1211 } 1212 1213 if (!numa_info[numa_info[i].initiator].has_cpu) { 1214 error_report("The initiator of NUMA node %d is invalid", i); 1215 exit(1); 1216 } 1217 } 1218 } 1219 1220 static void machine_numa_finish_cpu_init(MachineState *machine) 1221 { 1222 int i; 1223 bool default_mapping; 1224 GString *s = g_string_new(NULL); 1225 MachineClass *mc = MACHINE_GET_CLASS(machine); 1226 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine); 1227 1228 assert(machine->numa_state->num_nodes); 1229 for (i = 0; i < possible_cpus->len; i++) { 1230 if (possible_cpus->cpus[i].props.has_node_id) { 1231 break; 1232 } 1233 } 1234 default_mapping = (i == possible_cpus->len); 1235 1236 for (i = 0; i < possible_cpus->len; i++) { 1237 const CPUArchId *cpu_slot = &possible_cpus->cpus[i]; 1238 1239 if (!cpu_slot->props.has_node_id) { 1240 /* fetch default mapping from board and enable it */ 1241 CpuInstanceProperties props = cpu_slot->props; 1242 1243 props.node_id = mc->get_default_cpu_node_id(machine, i); 1244 if (!default_mapping) { 1245 /* record slots with not set mapping, 1246 * TODO: make it hard error in future */ 1247 char *cpu_str = cpu_slot_to_string(cpu_slot); 1248 g_string_append_printf(s, "%sCPU %d [%s]", 1249 s->len ? ", " : "", i, cpu_str); 1250 g_free(cpu_str); 1251 1252 /* non mapped cpus used to fallback to node 0 */ 1253 props.node_id = 0; 1254 } 1255 1256 props.has_node_id = true; 1257 machine_set_cpu_numa_node(machine, &props, &error_fatal); 1258 } 1259 } 1260 1261 if (machine->numa_state->hmat_enabled) { 1262 numa_validate_initiator(machine->numa_state); 1263 } 1264 1265 if (s->len && !qtest_enabled()) { 1266 warn_report("CPU(s) not present in any NUMA nodes: %s", 1267 s->str); 1268 warn_report("All CPU(s) up to maxcpus should be described " 1269 "in NUMA config, ability to start up with partial NUMA " 1270 "mappings is obsoleted and will be removed in future"); 1271 } 1272 g_string_free(s, true); 1273 } 1274 1275 MemoryRegion *machine_consume_memdev(MachineState *machine, 1276 HostMemoryBackend *backend) 1277 { 1278 MemoryRegion *ret = host_memory_backend_get_memory(backend); 1279 1280 if (host_memory_backend_is_mapped(backend)) { 1281 error_report("memory backend %s can't be used multiple times.", 1282 object_get_canonical_path_component(OBJECT(backend))); 1283 exit(EXIT_FAILURE); 1284 } 1285 host_memory_backend_set_mapped(backend, true); 1286 vmstate_register_ram_global(ret); 1287 return ret; 1288 } 1289 1290 static bool create_default_memdev(MachineState *ms, const char *path, Error **errp) 1291 { 1292 Object *obj; 1293 MachineClass *mc = MACHINE_GET_CLASS(ms); 1294 bool r = false; 1295 1296 obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM); 1297 if (path) { 1298 if (!object_property_set_str(obj, "mem-path", path, errp)) { 1299 goto out; 1300 } 1301 } 1302 if (!object_property_set_int(obj, "size", ms->ram_size, errp)) { 1303 goto out; 1304 } 1305 object_property_add_child(object_get_objects_root(), mc->default_ram_id, 1306 obj); 1307 /* Ensure backend's memory region name is equal to mc->default_ram_id */ 1308 if (!object_property_set_bool(obj, "x-use-canonical-path-for-ramblock-id", 1309 false, errp)) { 1310 goto out; 1311 } 1312 if (!user_creatable_complete(USER_CREATABLE(obj), errp)) { 1313 goto out; 1314 } 1315 r = object_property_set_link(OBJECT(ms), "memory-backend", obj, errp); 1316 1317 out: 1318 object_unref(obj); 1319 return r; 1320 } 1321 1322 1323 void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp) 1324 { 1325 MachineClass *machine_class = MACHINE_GET_CLASS(machine); 1326 ObjectClass *oc = object_class_by_name(machine->cpu_type); 1327 CPUClass *cc; 1328 1329 /* This checkpoint is required by replay to separate prior clock 1330 reading from the other reads, because timer polling functions query 1331 clock values from the log. */ 1332 replay_checkpoint(CHECKPOINT_INIT); 1333 1334 if (!xen_enabled()) { 1335 /* On 32-bit hosts, QEMU is limited by virtual address space */ 1336 if (machine->ram_size > (2047 << 20) && HOST_LONG_BITS == 32) { 1337 error_setg(errp, "at most 2047 MB RAM can be simulated"); 1338 return; 1339 } 1340 } 1341 1342 if (machine->memdev) { 1343 ram_addr_t backend_size = object_property_get_uint(OBJECT(machine->memdev), 1344 "size", &error_abort); 1345 if (backend_size != machine->ram_size) { 1346 error_setg(errp, "Machine memory size does not match the size of the memory backend"); 1347 return; 1348 } 1349 } else if (machine_class->default_ram_id && machine->ram_size && 1350 numa_uses_legacy_mem()) { 1351 if (!create_default_memdev(current_machine, mem_path, errp)) { 1352 return; 1353 } 1354 } 1355 1356 if (machine->numa_state) { 1357 numa_complete_configuration(machine); 1358 if (machine->numa_state->num_nodes) { 1359 machine_numa_finish_cpu_init(machine); 1360 } 1361 } 1362 1363 if (!machine->ram && machine->memdev) { 1364 machine->ram = machine_consume_memdev(machine, machine->memdev); 1365 } 1366 1367 /* If the machine supports the valid_cpu_types check and the user 1368 * specified a CPU with -cpu check here that the user CPU is supported. 1369 */ 1370 if (machine_class->valid_cpu_types && machine->cpu_type) { 1371 int i; 1372 1373 for (i = 0; machine_class->valid_cpu_types[i]; i++) { 1374 if (object_class_dynamic_cast(oc, 1375 machine_class->valid_cpu_types[i])) { 1376 /* The user specificed CPU is in the valid field, we are 1377 * good to go. 1378 */ 1379 break; 1380 } 1381 } 1382 1383 if (!machine_class->valid_cpu_types[i]) { 1384 /* The user specified CPU is not valid */ 1385 error_report("Invalid CPU type: %s", machine->cpu_type); 1386 error_printf("The valid types are: %s", 1387 machine_class->valid_cpu_types[0]); 1388 for (i = 1; machine_class->valid_cpu_types[i]; i++) { 1389 error_printf(", %s", machine_class->valid_cpu_types[i]); 1390 } 1391 error_printf("\n"); 1392 1393 exit(1); 1394 } 1395 } 1396 1397 /* Check if CPU type is deprecated and warn if so */ 1398 cc = CPU_CLASS(oc); 1399 if (cc && cc->deprecation_note) { 1400 warn_report("CPU model %s is deprecated -- %s", machine->cpu_type, 1401 cc->deprecation_note); 1402 } 1403 1404 if (machine->cgs) { 1405 /* 1406 * With confidential guests, the host can't see the real 1407 * contents of RAM, so there's no point in it trying to merge 1408 * areas. 1409 */ 1410 machine_set_mem_merge(OBJECT(machine), false, &error_abort); 1411 1412 /* 1413 * Virtio devices can't count on directly accessing guest 1414 * memory, so they need iommu_platform=on to use normal DMA 1415 * mechanisms. That requires also disabling legacy virtio 1416 * support for those virtio pci devices which allow it. 1417 */ 1418 object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy", 1419 "on", true); 1420 object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform", 1421 "on", false); 1422 } 1423 1424 accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator)); 1425 machine_class->init(machine); 1426 phase_advance(PHASE_MACHINE_INITIALIZED); 1427 } 1428 1429 static NotifierList machine_init_done_notifiers = 1430 NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers); 1431 1432 void qemu_add_machine_init_done_notifier(Notifier *notify) 1433 { 1434 notifier_list_add(&machine_init_done_notifiers, notify); 1435 if (phase_check(PHASE_MACHINE_READY)) { 1436 notify->notify(notify, NULL); 1437 } 1438 } 1439 1440 void qemu_remove_machine_init_done_notifier(Notifier *notify) 1441 { 1442 notifier_remove(notify); 1443 } 1444 1445 void qdev_machine_creation_done(void) 1446 { 1447 cpu_synchronize_all_post_init(); 1448 1449 if (current_machine->boot_config.has_once) { 1450 qemu_boot_set(current_machine->boot_config.once, &error_fatal); 1451 qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_config.order)); 1452 } 1453 1454 /* 1455 * ok, initial machine setup is done, starting from now we can 1456 * only create hotpluggable devices 1457 */ 1458 phase_advance(PHASE_MACHINE_READY); 1459 qdev_assert_realized_properly(); 1460 1461 /* TODO: once all bus devices are qdevified, this should be done 1462 * when bus is created by qdev.c */ 1463 /* 1464 * TODO: If we had a main 'reset container' that the whole system 1465 * lived in, we could reset that using the multi-phase reset 1466 * APIs. For the moment, we just reset the sysbus, which will cause 1467 * all devices hanging off it (and all their child buses, recursively) 1468 * to be reset. Note that this will *not* reset any Device objects 1469 * which are not attached to some part of the qbus tree! 1470 */ 1471 qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default()); 1472 1473 notifier_list_notify(&machine_init_done_notifiers, NULL); 1474 1475 if (rom_check_and_register_reset() != 0) { 1476 exit(1); 1477 } 1478 1479 replay_start(); 1480 1481 /* This checkpoint is required by replay to separate prior clock 1482 reading from the other reads, because timer polling functions query 1483 clock values from the log. */ 1484 replay_checkpoint(CHECKPOINT_RESET); 1485 qemu_system_reset(SHUTDOWN_CAUSE_NONE); 1486 register_global_state(); 1487 } 1488 1489 static const TypeInfo machine_info = { 1490 .name = TYPE_MACHINE, 1491 .parent = TYPE_OBJECT, 1492 .abstract = true, 1493 .class_size = sizeof(MachineClass), 1494 .class_init = machine_class_init, 1495 .class_base_init = machine_class_base_init, 1496 .instance_size = sizeof(MachineState), 1497 .instance_init = machine_initfn, 1498 .instance_finalize = machine_finalize, 1499 }; 1500 1501 static void machine_register_types(void) 1502 { 1503 type_register_static(&machine_info); 1504 } 1505 1506 type_init(machine_register_types) 1507