1 /* 2 * QEMU Machine 3 * 4 * Copyright (C) 2014 Red Hat Inc 5 * 6 * Authors: 7 * Marcel Apfelbaum <marcel.a@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/option.h" 15 #include "qemu/accel.h" 16 #include "sysemu/replay.h" 17 #include "qemu/units.h" 18 #include "hw/boards.h" 19 #include "hw/loader.h" 20 #include "qapi/error.h" 21 #include "qapi/qapi-visit-common.h" 22 #include "qapi/qapi-visit-machine.h" 23 #include "qapi/visitor.h" 24 #include "qom/object_interfaces.h" 25 #include "hw/sysbus.h" 26 #include "sysemu/cpus.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/numa.h" 31 #include "sysemu/xen.h" 32 #include "qemu/error-report.h" 33 #include "sysemu/qtest.h" 34 #include "hw/pci/pci.h" 35 #include "hw/mem/nvdimm.h" 36 #include "migration/global_state.h" 37 #include "migration/vmstate.h" 38 #include "exec/confidential-guest-support.h" 39 #include "hw/virtio/virtio.h" 40 #include "hw/virtio/virtio-pci.h" 41 #include "hw/virtio/virtio-net.h" 42 #include "audio/audio.h" 43 44 GlobalProperty hw_compat_8_1[] = {}; 45 const size_t hw_compat_8_1_len = G_N_ELEMENTS(hw_compat_8_1); 46 47 GlobalProperty hw_compat_8_0[] = { 48 { "migration", "multifd-flush-after-each-section", "on"}, 49 { TYPE_PCI_DEVICE, "x-pcie-ari-nextfn-1", "on" }, 50 { TYPE_VIRTIO_NET, "host_uso", "off"}, 51 { TYPE_VIRTIO_NET, "guest_uso4", "off"}, 52 { TYPE_VIRTIO_NET, "guest_uso6", "off"}, 53 }; 54 const size_t hw_compat_8_0_len = G_N_ELEMENTS(hw_compat_8_0); 55 56 GlobalProperty hw_compat_7_2[] = { 57 { "e1000e", "migrate-timadj", "off" }, 58 { "virtio-mem", "x-early-migration", "false" }, 59 { "migration", "x-preempt-pre-7-2", "true" }, 60 { TYPE_PCI_DEVICE, "x-pcie-err-unc-mask", "off" }, 61 }; 62 const size_t hw_compat_7_2_len = G_N_ELEMENTS(hw_compat_7_2); 63 64 GlobalProperty hw_compat_7_1[] = { 65 { "virtio-device", "queue_reset", "false" }, 66 { "virtio-rng-pci", "vectors", "0" }, 67 { "virtio-rng-pci-transitional", "vectors", "0" }, 68 { "virtio-rng-pci-non-transitional", "vectors", "0" }, 69 }; 70 const size_t hw_compat_7_1_len = G_N_ELEMENTS(hw_compat_7_1); 71 72 GlobalProperty hw_compat_7_0[] = { 73 { "arm-gicv3-common", "force-8-bit-prio", "on" }, 74 { "nvme-ns", "eui64-default", "on"}, 75 }; 76 const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0); 77 78 GlobalProperty hw_compat_6_2[] = { 79 { "PIIX4_PM", "x-not-migrate-acpi-index", "on"}, 80 }; 81 const size_t hw_compat_6_2_len = G_N_ELEMENTS(hw_compat_6_2); 82 83 GlobalProperty hw_compat_6_1[] = { 84 { "vhost-user-vsock-device", "seqpacket", "off" }, 85 { "nvme-ns", "shared", "off" }, 86 }; 87 const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1); 88 89 GlobalProperty hw_compat_6_0[] = { 90 { "gpex-pcihost", "allow-unmapped-accesses", "false" }, 91 { "i8042", "extended-state", "false"}, 92 { "nvme-ns", "eui64-default", "off"}, 93 { "e1000", "init-vet", "off" }, 94 { "e1000e", "init-vet", "off" }, 95 { "vhost-vsock-device", "seqpacket", "off" }, 96 }; 97 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0); 98 99 GlobalProperty hw_compat_5_2[] = { 100 { "ICH9-LPC", "smm-compat", "on"}, 101 { "PIIX4_PM", "smm-compat", "on"}, 102 { "virtio-blk-device", "report-discard-granularity", "off" }, 103 { "virtio-net-pci-base", "vectors", "3"}, 104 }; 105 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2); 106 107 GlobalProperty hw_compat_5_1[] = { 108 { "vhost-scsi", "num_queues", "1"}, 109 { "vhost-user-blk", "num-queues", "1"}, 110 { "vhost-user-scsi", "num_queues", "1"}, 111 { "virtio-blk-device", "num-queues", "1"}, 112 { "virtio-scsi-device", "num_queues", "1"}, 113 { "nvme", "use-intel-id", "on"}, 114 { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */ 115 { "pl011", "migrate-clk", "off" }, 116 { "virtio-pci", "x-ats-page-aligned", "off"}, 117 }; 118 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1); 119 120 GlobalProperty hw_compat_5_0[] = { 121 { "pci-host-bridge", "x-config-reg-migration-enabled", "off" }, 122 { "virtio-balloon-device", "page-poison", "false" }, 123 { "vmport", "x-read-set-eax", "off" }, 124 { "vmport", "x-signal-unsupported-cmd", "off" }, 125 { "vmport", "x-report-vmx-type", "off" }, 126 { "vmport", "x-cmds-v2", "off" }, 127 { "virtio-device", "x-disable-legacy-check", "true" }, 128 }; 129 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0); 130 131 GlobalProperty hw_compat_4_2[] = { 132 { "virtio-blk-device", "queue-size", "128"}, 133 { "virtio-scsi-device", "virtqueue_size", "128"}, 134 { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" }, 135 { "virtio-blk-device", "seg-max-adjust", "off"}, 136 { "virtio-scsi-device", "seg_max_adjust", "off"}, 137 { "vhost-blk-device", "seg_max_adjust", "off"}, 138 { "usb-host", "suppress-remote-wake", "off" }, 139 { "usb-redir", "suppress-remote-wake", "off" }, 140 { "qxl", "revision", "4" }, 141 { "qxl-vga", "revision", "4" }, 142 { "fw_cfg", "acpi-mr-restore", "false" }, 143 { "virtio-device", "use-disabled-flag", "false" }, 144 }; 145 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2); 146 147 GlobalProperty hw_compat_4_1[] = { 148 { "virtio-pci", "x-pcie-flr-init", "off" }, 149 }; 150 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1); 151 152 GlobalProperty hw_compat_4_0[] = { 153 { "VGA", "edid", "false" }, 154 { "secondary-vga", "edid", "false" }, 155 { "bochs-display", "edid", "false" }, 156 { "virtio-vga", "edid", "false" }, 157 { "virtio-gpu-device", "edid", "false" }, 158 { "virtio-device", "use-started", "false" }, 159 { "virtio-balloon-device", "qemu-4-0-config-size", "true" }, 160 { "pl031", "migrate-tick-offset", "false" }, 161 }; 162 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0); 163 164 GlobalProperty hw_compat_3_1[] = { 165 { "pcie-root-port", "x-speed", "2_5" }, 166 { "pcie-root-port", "x-width", "1" }, 167 { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" }, 168 { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" }, 169 { "tpm-crb", "ppi", "false" }, 170 { "tpm-tis", "ppi", "false" }, 171 { "usb-kbd", "serial", "42" }, 172 { "usb-mouse", "serial", "42" }, 173 { "usb-tablet", "serial", "42" }, 174 { "virtio-blk-device", "discard", "false" }, 175 { "virtio-blk-device", "write-zeroes", "false" }, 176 { "virtio-balloon-device", "qemu-4-0-config-size", "false" }, 177 { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */ 178 }; 179 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1); 180 181 GlobalProperty hw_compat_3_0[] = {}; 182 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0); 183 184 GlobalProperty hw_compat_2_12[] = { 185 { "migration", "decompress-error-check", "off" }, 186 { "hda-audio", "use-timer", "false" }, 187 { "cirrus-vga", "global-vmstate", "true" }, 188 { "VGA", "global-vmstate", "true" }, 189 { "vmware-svga", "global-vmstate", "true" }, 190 { "qxl-vga", "global-vmstate", "true" }, 191 }; 192 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12); 193 194 GlobalProperty hw_compat_2_11[] = { 195 { "hpet", "hpet-offset-saved", "false" }, 196 { "virtio-blk-pci", "vectors", "2" }, 197 { "vhost-user-blk-pci", "vectors", "2" }, 198 { "e1000", "migrate_tso_props", "off" }, 199 }; 200 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11); 201 202 GlobalProperty hw_compat_2_10[] = { 203 { "virtio-mouse-device", "wheel-axis", "false" }, 204 { "virtio-tablet-device", "wheel-axis", "false" }, 205 }; 206 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10); 207 208 GlobalProperty hw_compat_2_9[] = { 209 { "pci-bridge", "shpc", "off" }, 210 { "intel-iommu", "pt", "off" }, 211 { "virtio-net-device", "x-mtu-bypass-backend", "off" }, 212 { "pcie-root-port", "x-migrate-msix", "false" }, 213 }; 214 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9); 215 216 GlobalProperty hw_compat_2_8[] = { 217 { "fw_cfg_mem", "x-file-slots", "0x10" }, 218 { "fw_cfg_io", "x-file-slots", "0x10" }, 219 { "pflash_cfi01", "old-multiple-chip-handling", "on" }, 220 { "pci-bridge", "shpc", "on" }, 221 { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" }, 222 { "virtio-pci", "x-pcie-deverr-init", "off" }, 223 { "virtio-pci", "x-pcie-lnkctl-init", "off" }, 224 { "virtio-pci", "x-pcie-pm-init", "off" }, 225 { "cirrus-vga", "vgamem_mb", "8" }, 226 { "isa-cirrus-vga", "vgamem_mb", "8" }, 227 }; 228 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8); 229 230 GlobalProperty hw_compat_2_7[] = { 231 { "virtio-pci", "page-per-vq", "on" }, 232 { "virtio-serial-device", "emergency-write", "off" }, 233 { "ioapic", "version", "0x11" }, 234 { "intel-iommu", "x-buggy-eim", "true" }, 235 { "virtio-pci", "x-ignore-backend-features", "on" }, 236 }; 237 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); 238 239 GlobalProperty hw_compat_2_6[] = { 240 { "virtio-mmio", "format_transport_address", "off" }, 241 /* Optional because not all virtio-pci devices support legacy mode */ 242 { "virtio-pci", "disable-modern", "on", .optional = true }, 243 { "virtio-pci", "disable-legacy", "off", .optional = true }, 244 }; 245 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); 246 247 GlobalProperty hw_compat_2_5[] = { 248 { "isa-fdc", "fallback", "144" }, 249 { "pvscsi", "x-old-pci-configuration", "on" }, 250 { "pvscsi", "x-disable-pcie", "on" }, 251 { "vmxnet3", "x-old-msi-offsets", "on" }, 252 { "vmxnet3", "x-disable-pcie", "on" }, 253 }; 254 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5); 255 256 GlobalProperty hw_compat_2_4[] = { 257 /* Optional because the 'scsi' property is Linux-only */ 258 { "virtio-blk-device", "scsi", "true", .optional = true }, 259 { "e1000", "extra_mac_registers", "off" }, 260 { "virtio-pci", "x-disable-pcie", "on" }, 261 { "virtio-pci", "migrate-extra", "off" }, 262 { "fw_cfg_mem", "dma_enabled", "off" }, 263 { "fw_cfg_io", "dma_enabled", "off" } 264 }; 265 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4); 266 267 GlobalProperty hw_compat_2_3[] = { 268 { "virtio-blk-pci", "any_layout", "off" }, 269 { "virtio-balloon-pci", "any_layout", "off" }, 270 { "virtio-serial-pci", "any_layout", "off" }, 271 { "virtio-9p-pci", "any_layout", "off" }, 272 { "virtio-rng-pci", "any_layout", "off" }, 273 { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" }, 274 { "migration", "send-configuration", "off" }, 275 { "migration", "send-section-footer", "off" }, 276 { "migration", "store-global-state", "off" }, 277 }; 278 const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3); 279 280 GlobalProperty hw_compat_2_2[] = {}; 281 const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2); 282 283 GlobalProperty hw_compat_2_1[] = { 284 { "intel-hda", "old_msi_addr", "on" }, 285 { "VGA", "qemu-extended-regs", "off" }, 286 { "secondary-vga", "qemu-extended-regs", "off" }, 287 { "virtio-scsi-pci", "any_layout", "off" }, 288 { "usb-mouse", "usb_version", "1" }, 289 { "usb-kbd", "usb_version", "1" }, 290 { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" }, 291 }; 292 const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1); 293 294 MachineState *current_machine; 295 296 static char *machine_get_kernel(Object *obj, Error **errp) 297 { 298 MachineState *ms = MACHINE(obj); 299 300 return g_strdup(ms->kernel_filename); 301 } 302 303 static void machine_set_kernel(Object *obj, const char *value, Error **errp) 304 { 305 MachineState *ms = MACHINE(obj); 306 307 g_free(ms->kernel_filename); 308 ms->kernel_filename = g_strdup(value); 309 } 310 311 static char *machine_get_initrd(Object *obj, Error **errp) 312 { 313 MachineState *ms = MACHINE(obj); 314 315 return g_strdup(ms->initrd_filename); 316 } 317 318 static void machine_set_initrd(Object *obj, const char *value, Error **errp) 319 { 320 MachineState *ms = MACHINE(obj); 321 322 g_free(ms->initrd_filename); 323 ms->initrd_filename = g_strdup(value); 324 } 325 326 static char *machine_get_append(Object *obj, Error **errp) 327 { 328 MachineState *ms = MACHINE(obj); 329 330 return g_strdup(ms->kernel_cmdline); 331 } 332 333 static void machine_set_append(Object *obj, const char *value, Error **errp) 334 { 335 MachineState *ms = MACHINE(obj); 336 337 g_free(ms->kernel_cmdline); 338 ms->kernel_cmdline = g_strdup(value); 339 } 340 341 static char *machine_get_dtb(Object *obj, Error **errp) 342 { 343 MachineState *ms = MACHINE(obj); 344 345 return g_strdup(ms->dtb); 346 } 347 348 static void machine_set_dtb(Object *obj, const char *value, Error **errp) 349 { 350 MachineState *ms = MACHINE(obj); 351 352 g_free(ms->dtb); 353 ms->dtb = g_strdup(value); 354 } 355 356 static char *machine_get_dumpdtb(Object *obj, Error **errp) 357 { 358 MachineState *ms = MACHINE(obj); 359 360 return g_strdup(ms->dumpdtb); 361 } 362 363 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp) 364 { 365 MachineState *ms = MACHINE(obj); 366 367 g_free(ms->dumpdtb); 368 ms->dumpdtb = g_strdup(value); 369 } 370 371 static void machine_get_phandle_start(Object *obj, Visitor *v, 372 const char *name, void *opaque, 373 Error **errp) 374 { 375 MachineState *ms = MACHINE(obj); 376 int64_t value = ms->phandle_start; 377 378 visit_type_int(v, name, &value, errp); 379 } 380 381 static void machine_set_phandle_start(Object *obj, Visitor *v, 382 const char *name, void *opaque, 383 Error **errp) 384 { 385 MachineState *ms = MACHINE(obj); 386 int64_t value; 387 388 if (!visit_type_int(v, name, &value, errp)) { 389 return; 390 } 391 392 ms->phandle_start = value; 393 } 394 395 static char *machine_get_dt_compatible(Object *obj, Error **errp) 396 { 397 MachineState *ms = MACHINE(obj); 398 399 return g_strdup(ms->dt_compatible); 400 } 401 402 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp) 403 { 404 MachineState *ms = MACHINE(obj); 405 406 g_free(ms->dt_compatible); 407 ms->dt_compatible = g_strdup(value); 408 } 409 410 static bool machine_get_dump_guest_core(Object *obj, Error **errp) 411 { 412 MachineState *ms = MACHINE(obj); 413 414 return ms->dump_guest_core; 415 } 416 417 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp) 418 { 419 MachineState *ms = MACHINE(obj); 420 421 ms->dump_guest_core = value; 422 } 423 424 static bool machine_get_mem_merge(Object *obj, Error **errp) 425 { 426 MachineState *ms = MACHINE(obj); 427 428 return ms->mem_merge; 429 } 430 431 static void machine_set_mem_merge(Object *obj, bool value, Error **errp) 432 { 433 MachineState *ms = MACHINE(obj); 434 435 ms->mem_merge = value; 436 } 437 438 static bool machine_get_usb(Object *obj, Error **errp) 439 { 440 MachineState *ms = MACHINE(obj); 441 442 return ms->usb; 443 } 444 445 static void machine_set_usb(Object *obj, bool value, Error **errp) 446 { 447 MachineState *ms = MACHINE(obj); 448 449 ms->usb = value; 450 ms->usb_disabled = !value; 451 } 452 453 static bool machine_get_graphics(Object *obj, Error **errp) 454 { 455 MachineState *ms = MACHINE(obj); 456 457 return ms->enable_graphics; 458 } 459 460 static void machine_set_graphics(Object *obj, bool value, Error **errp) 461 { 462 MachineState *ms = MACHINE(obj); 463 464 ms->enable_graphics = value; 465 } 466 467 static char *machine_get_firmware(Object *obj, Error **errp) 468 { 469 MachineState *ms = MACHINE(obj); 470 471 return g_strdup(ms->firmware); 472 } 473 474 static void machine_set_firmware(Object *obj, const char *value, Error **errp) 475 { 476 MachineState *ms = MACHINE(obj); 477 478 g_free(ms->firmware); 479 ms->firmware = g_strdup(value); 480 } 481 482 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp) 483 { 484 MachineState *ms = MACHINE(obj); 485 486 ms->suppress_vmdesc = value; 487 } 488 489 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp) 490 { 491 MachineState *ms = MACHINE(obj); 492 493 return ms->suppress_vmdesc; 494 } 495 496 static char *machine_get_memory_encryption(Object *obj, Error **errp) 497 { 498 MachineState *ms = MACHINE(obj); 499 500 if (ms->cgs) { 501 return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs))); 502 } 503 504 return NULL; 505 } 506 507 static void machine_set_memory_encryption(Object *obj, const char *value, 508 Error **errp) 509 { 510 Object *cgs = 511 object_resolve_path_component(object_get_objects_root(), value); 512 513 if (!cgs) { 514 error_setg(errp, "No such memory encryption object '%s'", value); 515 return; 516 } 517 518 object_property_set_link(obj, "confidential-guest-support", cgs, errp); 519 } 520 521 static void machine_check_confidential_guest_support(const Object *obj, 522 const char *name, 523 Object *new_target, 524 Error **errp) 525 { 526 /* 527 * So far the only constraint is that the target has the 528 * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked 529 * by the QOM core 530 */ 531 } 532 533 static bool machine_get_nvdimm(Object *obj, Error **errp) 534 { 535 MachineState *ms = MACHINE(obj); 536 537 return ms->nvdimms_state->is_enabled; 538 } 539 540 static void machine_set_nvdimm(Object *obj, bool value, Error **errp) 541 { 542 MachineState *ms = MACHINE(obj); 543 544 ms->nvdimms_state->is_enabled = value; 545 } 546 547 static bool machine_get_hmat(Object *obj, Error **errp) 548 { 549 MachineState *ms = MACHINE(obj); 550 551 return ms->numa_state->hmat_enabled; 552 } 553 554 static void machine_set_hmat(Object *obj, bool value, Error **errp) 555 { 556 MachineState *ms = MACHINE(obj); 557 558 ms->numa_state->hmat_enabled = value; 559 } 560 561 static void machine_get_mem(Object *obj, Visitor *v, const char *name, 562 void *opaque, Error **errp) 563 { 564 MachineState *ms = MACHINE(obj); 565 MemorySizeConfiguration mem = { 566 .has_size = true, 567 .size = ms->ram_size, 568 .has_max_size = !!ms->ram_slots, 569 .max_size = ms->maxram_size, 570 .has_slots = !!ms->ram_slots, 571 .slots = ms->ram_slots, 572 }; 573 MemorySizeConfiguration *p_mem = &mem; 574 575 visit_type_MemorySizeConfiguration(v, name, &p_mem, &error_abort); 576 } 577 578 static void machine_set_mem(Object *obj, Visitor *v, const char *name, 579 void *opaque, Error **errp) 580 { 581 ERRP_GUARD(); 582 MachineState *ms = MACHINE(obj); 583 MachineClass *mc = MACHINE_GET_CLASS(obj); 584 MemorySizeConfiguration *mem; 585 586 if (!visit_type_MemorySizeConfiguration(v, name, &mem, errp)) { 587 return; 588 } 589 590 if (!mem->has_size) { 591 mem->has_size = true; 592 mem->size = mc->default_ram_size; 593 } 594 mem->size = QEMU_ALIGN_UP(mem->size, 8192); 595 if (mc->fixup_ram_size) { 596 mem->size = mc->fixup_ram_size(mem->size); 597 } 598 if ((ram_addr_t)mem->size != mem->size) { 599 error_setg(errp, "ram size too large"); 600 goto out_free; 601 } 602 603 if (mem->has_max_size) { 604 if (mem->max_size < mem->size) { 605 error_setg(errp, "invalid value of maxmem: " 606 "maximum memory size (0x%" PRIx64 ") must be at least " 607 "the initial memory size (0x%" PRIx64 ")", 608 mem->max_size, mem->size); 609 goto out_free; 610 } 611 if (mem->has_slots && mem->slots && mem->max_size == mem->size) { 612 error_setg(errp, "invalid value of maxmem: " 613 "memory slots were specified but maximum memory size " 614 "(0x%" PRIx64 ") is equal to the initial memory size " 615 "(0x%" PRIx64 ")", mem->max_size, mem->size); 616 goto out_free; 617 } 618 ms->maxram_size = mem->max_size; 619 } else { 620 if (mem->has_slots) { 621 error_setg(errp, "slots specified but no max-size"); 622 goto out_free; 623 } 624 ms->maxram_size = mem->size; 625 } 626 ms->ram_size = mem->size; 627 ms->ram_slots = mem->has_slots ? mem->slots : 0; 628 out_free: 629 qapi_free_MemorySizeConfiguration(mem); 630 } 631 632 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp) 633 { 634 MachineState *ms = MACHINE(obj); 635 636 return g_strdup(ms->nvdimms_state->persistence_string); 637 } 638 639 static void machine_set_nvdimm_persistence(Object *obj, const char *value, 640 Error **errp) 641 { 642 MachineState *ms = MACHINE(obj); 643 NVDIMMState *nvdimms_state = ms->nvdimms_state; 644 645 if (strcmp(value, "cpu") == 0) { 646 nvdimms_state->persistence = 3; 647 } else if (strcmp(value, "mem-ctrl") == 0) { 648 nvdimms_state->persistence = 2; 649 } else { 650 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option", 651 value); 652 return; 653 } 654 655 g_free(nvdimms_state->persistence_string); 656 nvdimms_state->persistence_string = g_strdup(value); 657 } 658 659 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type) 660 { 661 QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); 662 } 663 664 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev) 665 { 666 Object *obj = OBJECT(dev); 667 668 if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) { 669 return false; 670 } 671 672 return device_type_is_dynamic_sysbus(mc, object_get_typename(obj)); 673 } 674 675 bool device_type_is_dynamic_sysbus(MachineClass *mc, const char *type) 676 { 677 bool allowed = false; 678 strList *wl; 679 ObjectClass *klass = object_class_by_name(type); 680 681 for (wl = mc->allowed_dynamic_sysbus_devices; 682 !allowed && wl; 683 wl = wl->next) { 684 allowed |= !!object_class_dynamic_cast(klass, wl->value); 685 } 686 687 return allowed; 688 } 689 690 static char *machine_get_audiodev(Object *obj, Error **errp) 691 { 692 MachineState *ms = MACHINE(obj); 693 694 return g_strdup(ms->audiodev); 695 } 696 697 static void machine_set_audiodev(Object *obj, const char *value, 698 Error **errp) 699 { 700 MachineState *ms = MACHINE(obj); 701 702 if (!audio_state_by_name(value, errp)) { 703 return; 704 } 705 706 g_free(ms->audiodev); 707 ms->audiodev = g_strdup(value); 708 } 709 710 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine) 711 { 712 int i; 713 HotpluggableCPUList *head = NULL; 714 MachineClass *mc = MACHINE_GET_CLASS(machine); 715 716 /* force board to initialize possible_cpus if it hasn't been done yet */ 717 mc->possible_cpu_arch_ids(machine); 718 719 for (i = 0; i < machine->possible_cpus->len; i++) { 720 Object *cpu; 721 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); 722 723 cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type); 724 cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count; 725 cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props, 726 sizeof(*cpu_item->props)); 727 728 cpu = machine->possible_cpus->cpus[i].cpu; 729 if (cpu) { 730 cpu_item->qom_path = object_get_canonical_path(cpu); 731 } 732 QAPI_LIST_PREPEND(head, cpu_item); 733 } 734 return head; 735 } 736 737 /** 738 * machine_set_cpu_numa_node: 739 * @machine: machine object to modify 740 * @props: specifies which cpu objects to assign to 741 * numa node specified by @props.node_id 742 * @errp: if an error occurs, a pointer to an area to store the error 743 * 744 * Associate NUMA node specified by @props.node_id with cpu slots that 745 * match socket/core/thread-ids specified by @props. It's recommended to use 746 * query-hotpluggable-cpus.props values to specify affected cpu slots, 747 * which would lead to exact 1:1 mapping of cpu slots to NUMA node. 748 * 749 * However for CLI convenience it's possible to pass in subset of properties, 750 * which would affect all cpu slots that match it. 751 * Ex for pc machine: 752 * -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \ 753 * -numa cpu,node-id=0,socket_id=0 \ 754 * -numa cpu,node-id=1,socket_id=1 755 * will assign all child cores of socket 0 to node 0 and 756 * of socket 1 to node 1. 757 * 758 * On attempt of reassigning (already assigned) cpu slot to another NUMA node, 759 * return error. 760 * Empty subset is disallowed and function will return with error in this case. 761 */ 762 void machine_set_cpu_numa_node(MachineState *machine, 763 const CpuInstanceProperties *props, Error **errp) 764 { 765 MachineClass *mc = MACHINE_GET_CLASS(machine); 766 NodeInfo *numa_info = machine->numa_state->nodes; 767 bool match = false; 768 int i; 769 770 if (!mc->possible_cpu_arch_ids) { 771 error_setg(errp, "mapping of CPUs to NUMA node is not supported"); 772 return; 773 } 774 775 /* disabling node mapping is not supported, forbid it */ 776 assert(props->has_node_id); 777 778 /* force board to initialize possible_cpus if it hasn't been done yet */ 779 mc->possible_cpu_arch_ids(machine); 780 781 for (i = 0; i < machine->possible_cpus->len; i++) { 782 CPUArchId *slot = &machine->possible_cpus->cpus[i]; 783 784 /* reject unsupported by board properties */ 785 if (props->has_thread_id && !slot->props.has_thread_id) { 786 error_setg(errp, "thread-id is not supported"); 787 return; 788 } 789 790 if (props->has_core_id && !slot->props.has_core_id) { 791 error_setg(errp, "core-id is not supported"); 792 return; 793 } 794 795 if (props->has_cluster_id && !slot->props.has_cluster_id) { 796 error_setg(errp, "cluster-id is not supported"); 797 return; 798 } 799 800 if (props->has_socket_id && !slot->props.has_socket_id) { 801 error_setg(errp, "socket-id is not supported"); 802 return; 803 } 804 805 if (props->has_die_id && !slot->props.has_die_id) { 806 error_setg(errp, "die-id is not supported"); 807 return; 808 } 809 810 /* skip slots with explicit mismatch */ 811 if (props->has_thread_id && props->thread_id != slot->props.thread_id) { 812 continue; 813 } 814 815 if (props->has_core_id && props->core_id != slot->props.core_id) { 816 continue; 817 } 818 819 if (props->has_cluster_id && 820 props->cluster_id != slot->props.cluster_id) { 821 continue; 822 } 823 824 if (props->has_die_id && props->die_id != slot->props.die_id) { 825 continue; 826 } 827 828 if (props->has_socket_id && props->socket_id != slot->props.socket_id) { 829 continue; 830 } 831 832 /* reject assignment if slot is already assigned, for compatibility 833 * of legacy cpu_index mapping with SPAPR core based mapping do not 834 * error out if cpu thread and matched core have the same node-id */ 835 if (slot->props.has_node_id && 836 slot->props.node_id != props->node_id) { 837 error_setg(errp, "CPU is already assigned to node-id: %" PRId64, 838 slot->props.node_id); 839 return; 840 } 841 842 /* assign slot to node as it's matched '-numa cpu' key */ 843 match = true; 844 slot->props.node_id = props->node_id; 845 slot->props.has_node_id = props->has_node_id; 846 847 if (machine->numa_state->hmat_enabled) { 848 if ((numa_info[props->node_id].initiator < MAX_NODES) && 849 (props->node_id != numa_info[props->node_id].initiator)) { 850 error_setg(errp, "The initiator of CPU NUMA node %" PRId64 851 " should be itself (got %" PRIu16 ")", 852 props->node_id, numa_info[props->node_id].initiator); 853 return; 854 } 855 numa_info[props->node_id].has_cpu = true; 856 numa_info[props->node_id].initiator = props->node_id; 857 } 858 } 859 860 if (!match) { 861 error_setg(errp, "no match found"); 862 } 863 } 864 865 static void machine_get_smp(Object *obj, Visitor *v, const char *name, 866 void *opaque, Error **errp) 867 { 868 MachineState *ms = MACHINE(obj); 869 SMPConfiguration *config = &(SMPConfiguration){ 870 .has_cpus = true, .cpus = ms->smp.cpus, 871 .has_sockets = true, .sockets = ms->smp.sockets, 872 .has_dies = true, .dies = ms->smp.dies, 873 .has_clusters = true, .clusters = ms->smp.clusters, 874 .has_cores = true, .cores = ms->smp.cores, 875 .has_threads = true, .threads = ms->smp.threads, 876 .has_maxcpus = true, .maxcpus = ms->smp.max_cpus, 877 }; 878 879 if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) { 880 return; 881 } 882 } 883 884 static void machine_set_smp(Object *obj, Visitor *v, const char *name, 885 void *opaque, Error **errp) 886 { 887 MachineState *ms = MACHINE(obj); 888 g_autoptr(SMPConfiguration) config = NULL; 889 890 if (!visit_type_SMPConfiguration(v, name, &config, errp)) { 891 return; 892 } 893 894 machine_parse_smp_config(ms, config, errp); 895 } 896 897 static void machine_get_boot(Object *obj, Visitor *v, const char *name, 898 void *opaque, Error **errp) 899 { 900 MachineState *ms = MACHINE(obj); 901 BootConfiguration *config = &ms->boot_config; 902 visit_type_BootConfiguration(v, name, &config, &error_abort); 903 } 904 905 static void machine_free_boot_config(MachineState *ms) 906 { 907 g_free(ms->boot_config.order); 908 g_free(ms->boot_config.once); 909 g_free(ms->boot_config.splash); 910 } 911 912 static void machine_copy_boot_config(MachineState *ms, BootConfiguration *config) 913 { 914 MachineClass *machine_class = MACHINE_GET_CLASS(ms); 915 916 machine_free_boot_config(ms); 917 ms->boot_config = *config; 918 if (!config->order) { 919 ms->boot_config.order = g_strdup(machine_class->default_boot_order); 920 } 921 } 922 923 static void machine_set_boot(Object *obj, Visitor *v, const char *name, 924 void *opaque, Error **errp) 925 { 926 ERRP_GUARD(); 927 MachineState *ms = MACHINE(obj); 928 BootConfiguration *config = NULL; 929 930 if (!visit_type_BootConfiguration(v, name, &config, errp)) { 931 return; 932 } 933 if (config->order) { 934 validate_bootdevices(config->order, errp); 935 if (*errp) { 936 goto out_free; 937 } 938 } 939 if (config->once) { 940 validate_bootdevices(config->once, errp); 941 if (*errp) { 942 goto out_free; 943 } 944 } 945 946 machine_copy_boot_config(ms, config); 947 /* Strings live in ms->boot_config. */ 948 free(config); 949 return; 950 951 out_free: 952 qapi_free_BootConfiguration(config); 953 } 954 955 void machine_add_audiodev_property(MachineClass *mc) 956 { 957 ObjectClass *oc = OBJECT_CLASS(mc); 958 959 object_class_property_add_str(oc, "audiodev", 960 machine_get_audiodev, 961 machine_set_audiodev); 962 object_class_property_set_description(oc, "audiodev", 963 "Audiodev to use for default machine devices"); 964 } 965 966 static void machine_class_init(ObjectClass *oc, void *data) 967 { 968 MachineClass *mc = MACHINE_CLASS(oc); 969 970 /* Default 128 MB as guest ram size */ 971 mc->default_ram_size = 128 * MiB; 972 mc->rom_file_has_mr = true; 973 974 /* numa node memory size aligned on 8MB by default. 975 * On Linux, each node's border has to be 8MB aligned 976 */ 977 mc->numa_mem_align_shift = 23; 978 979 object_class_property_add_str(oc, "kernel", 980 machine_get_kernel, machine_set_kernel); 981 object_class_property_set_description(oc, "kernel", 982 "Linux kernel image file"); 983 984 object_class_property_add_str(oc, "initrd", 985 machine_get_initrd, machine_set_initrd); 986 object_class_property_set_description(oc, "initrd", 987 "Linux initial ramdisk file"); 988 989 object_class_property_add_str(oc, "append", 990 machine_get_append, machine_set_append); 991 object_class_property_set_description(oc, "append", 992 "Linux kernel command line"); 993 994 object_class_property_add_str(oc, "dtb", 995 machine_get_dtb, machine_set_dtb); 996 object_class_property_set_description(oc, "dtb", 997 "Linux kernel device tree file"); 998 999 object_class_property_add_str(oc, "dumpdtb", 1000 machine_get_dumpdtb, machine_set_dumpdtb); 1001 object_class_property_set_description(oc, "dumpdtb", 1002 "Dump current dtb to a file and quit"); 1003 1004 object_class_property_add(oc, "boot", "BootConfiguration", 1005 machine_get_boot, machine_set_boot, 1006 NULL, NULL); 1007 object_class_property_set_description(oc, "boot", 1008 "Boot configuration"); 1009 1010 object_class_property_add(oc, "smp", "SMPConfiguration", 1011 machine_get_smp, machine_set_smp, 1012 NULL, NULL); 1013 object_class_property_set_description(oc, "smp", 1014 "CPU topology"); 1015 1016 object_class_property_add(oc, "phandle-start", "int", 1017 machine_get_phandle_start, machine_set_phandle_start, 1018 NULL, NULL); 1019 object_class_property_set_description(oc, "phandle-start", 1020 "The first phandle ID we may generate dynamically"); 1021 1022 object_class_property_add_str(oc, "dt-compatible", 1023 machine_get_dt_compatible, machine_set_dt_compatible); 1024 object_class_property_set_description(oc, "dt-compatible", 1025 "Overrides the \"compatible\" property of the dt root node"); 1026 1027 object_class_property_add_bool(oc, "dump-guest-core", 1028 machine_get_dump_guest_core, machine_set_dump_guest_core); 1029 object_class_property_set_description(oc, "dump-guest-core", 1030 "Include guest memory in a core dump"); 1031 1032 object_class_property_add_bool(oc, "mem-merge", 1033 machine_get_mem_merge, machine_set_mem_merge); 1034 object_class_property_set_description(oc, "mem-merge", 1035 "Enable/disable memory merge support"); 1036 1037 object_class_property_add_bool(oc, "usb", 1038 machine_get_usb, machine_set_usb); 1039 object_class_property_set_description(oc, "usb", 1040 "Set on/off to enable/disable usb"); 1041 1042 object_class_property_add_bool(oc, "graphics", 1043 machine_get_graphics, machine_set_graphics); 1044 object_class_property_set_description(oc, "graphics", 1045 "Set on/off to enable/disable graphics emulation"); 1046 1047 object_class_property_add_str(oc, "firmware", 1048 machine_get_firmware, machine_set_firmware); 1049 object_class_property_set_description(oc, "firmware", 1050 "Firmware image"); 1051 1052 object_class_property_add_bool(oc, "suppress-vmdesc", 1053 machine_get_suppress_vmdesc, machine_set_suppress_vmdesc); 1054 object_class_property_set_description(oc, "suppress-vmdesc", 1055 "Set on to disable self-describing migration"); 1056 1057 object_class_property_add_link(oc, "confidential-guest-support", 1058 TYPE_CONFIDENTIAL_GUEST_SUPPORT, 1059 offsetof(MachineState, cgs), 1060 machine_check_confidential_guest_support, 1061 OBJ_PROP_LINK_STRONG); 1062 object_class_property_set_description(oc, "confidential-guest-support", 1063 "Set confidential guest scheme to support"); 1064 1065 /* For compatibility */ 1066 object_class_property_add_str(oc, "memory-encryption", 1067 machine_get_memory_encryption, machine_set_memory_encryption); 1068 object_class_property_set_description(oc, "memory-encryption", 1069 "Set memory encryption object to use"); 1070 1071 object_class_property_add_link(oc, "memory-backend", TYPE_MEMORY_BACKEND, 1072 offsetof(MachineState, memdev), object_property_allow_set_link, 1073 OBJ_PROP_LINK_STRONG); 1074 object_class_property_set_description(oc, "memory-backend", 1075 "Set RAM backend" 1076 "Valid value is ID of hostmem based backend"); 1077 1078 object_class_property_add(oc, "memory", "MemorySizeConfiguration", 1079 machine_get_mem, machine_set_mem, 1080 NULL, NULL); 1081 object_class_property_set_description(oc, "memory", 1082 "Memory size configuration"); 1083 } 1084 1085 static void machine_class_base_init(ObjectClass *oc, void *data) 1086 { 1087 MachineClass *mc = MACHINE_CLASS(oc); 1088 mc->max_cpus = mc->max_cpus ?: 1; 1089 mc->min_cpus = mc->min_cpus ?: 1; 1090 mc->default_cpus = mc->default_cpus ?: 1; 1091 1092 if (!object_class_is_abstract(oc)) { 1093 const char *cname = object_class_get_name(oc); 1094 assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX)); 1095 mc->name = g_strndup(cname, 1096 strlen(cname) - strlen(TYPE_MACHINE_SUFFIX)); 1097 mc->compat_props = g_ptr_array_new(); 1098 } 1099 } 1100 1101 static void machine_initfn(Object *obj) 1102 { 1103 MachineState *ms = MACHINE(obj); 1104 MachineClass *mc = MACHINE_GET_CLASS(obj); 1105 1106 container_get(obj, "/peripheral"); 1107 container_get(obj, "/peripheral-anon"); 1108 1109 ms->dump_guest_core = true; 1110 ms->mem_merge = true; 1111 ms->enable_graphics = true; 1112 ms->kernel_cmdline = g_strdup(""); 1113 ms->ram_size = mc->default_ram_size; 1114 ms->maxram_size = mc->default_ram_size; 1115 1116 if (mc->nvdimm_supported) { 1117 ms->nvdimms_state = g_new0(NVDIMMState, 1); 1118 object_property_add_bool(obj, "nvdimm", 1119 machine_get_nvdimm, machine_set_nvdimm); 1120 object_property_set_description(obj, "nvdimm", 1121 "Set on/off to enable/disable " 1122 "NVDIMM instantiation"); 1123 1124 object_property_add_str(obj, "nvdimm-persistence", 1125 machine_get_nvdimm_persistence, 1126 machine_set_nvdimm_persistence); 1127 object_property_set_description(obj, "nvdimm-persistence", 1128 "Set NVDIMM persistence" 1129 "Valid values are cpu, mem-ctrl"); 1130 } 1131 1132 if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { 1133 ms->numa_state = g_new0(NumaState, 1); 1134 object_property_add_bool(obj, "hmat", 1135 machine_get_hmat, machine_set_hmat); 1136 object_property_set_description(obj, "hmat", 1137 "Set on/off to enable/disable " 1138 "ACPI Heterogeneous Memory Attribute " 1139 "Table (HMAT)"); 1140 } 1141 1142 /* default to mc->default_cpus */ 1143 ms->smp.cpus = mc->default_cpus; 1144 ms->smp.max_cpus = mc->default_cpus; 1145 ms->smp.sockets = 1; 1146 ms->smp.dies = 1; 1147 ms->smp.clusters = 1; 1148 ms->smp.cores = 1; 1149 ms->smp.threads = 1; 1150 1151 machine_copy_boot_config(ms, &(BootConfiguration){ 0 }); 1152 } 1153 1154 static void machine_finalize(Object *obj) 1155 { 1156 MachineState *ms = MACHINE(obj); 1157 1158 machine_free_boot_config(ms); 1159 g_free(ms->kernel_filename); 1160 g_free(ms->initrd_filename); 1161 g_free(ms->kernel_cmdline); 1162 g_free(ms->dtb); 1163 g_free(ms->dumpdtb); 1164 g_free(ms->dt_compatible); 1165 g_free(ms->firmware); 1166 g_free(ms->device_memory); 1167 g_free(ms->nvdimms_state); 1168 g_free(ms->numa_state); 1169 g_free(ms->audiodev); 1170 } 1171 1172 bool machine_usb(MachineState *machine) 1173 { 1174 return machine->usb; 1175 } 1176 1177 int machine_phandle_start(MachineState *machine) 1178 { 1179 return machine->phandle_start; 1180 } 1181 1182 bool machine_dump_guest_core(MachineState *machine) 1183 { 1184 return machine->dump_guest_core; 1185 } 1186 1187 bool machine_mem_merge(MachineState *machine) 1188 { 1189 return machine->mem_merge; 1190 } 1191 1192 static char *cpu_slot_to_string(const CPUArchId *cpu) 1193 { 1194 GString *s = g_string_new(NULL); 1195 if (cpu->props.has_socket_id) { 1196 g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id); 1197 } 1198 if (cpu->props.has_die_id) { 1199 if (s->len) { 1200 g_string_append_printf(s, ", "); 1201 } 1202 g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); 1203 } 1204 if (cpu->props.has_cluster_id) { 1205 if (s->len) { 1206 g_string_append_printf(s, ", "); 1207 } 1208 g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id); 1209 } 1210 if (cpu->props.has_core_id) { 1211 if (s->len) { 1212 g_string_append_printf(s, ", "); 1213 } 1214 g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id); 1215 } 1216 if (cpu->props.has_thread_id) { 1217 if (s->len) { 1218 g_string_append_printf(s, ", "); 1219 } 1220 g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id); 1221 } 1222 return g_string_free(s, false); 1223 } 1224 1225 static void numa_validate_initiator(NumaState *numa_state) 1226 { 1227 int i; 1228 NodeInfo *numa_info = numa_state->nodes; 1229 1230 for (i = 0; i < numa_state->num_nodes; i++) { 1231 if (numa_info[i].initiator == MAX_NODES) { 1232 continue; 1233 } 1234 1235 if (!numa_info[numa_info[i].initiator].present) { 1236 error_report("NUMA node %" PRIu16 " is missing, use " 1237 "'-numa node' option to declare it first", 1238 numa_info[i].initiator); 1239 exit(1); 1240 } 1241 1242 if (!numa_info[numa_info[i].initiator].has_cpu) { 1243 error_report("The initiator of NUMA node %d is invalid", i); 1244 exit(1); 1245 } 1246 } 1247 } 1248 1249 static void machine_numa_finish_cpu_init(MachineState *machine) 1250 { 1251 int i; 1252 bool default_mapping; 1253 GString *s = g_string_new(NULL); 1254 MachineClass *mc = MACHINE_GET_CLASS(machine); 1255 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine); 1256 1257 assert(machine->numa_state->num_nodes); 1258 for (i = 0; i < possible_cpus->len; i++) { 1259 if (possible_cpus->cpus[i].props.has_node_id) { 1260 break; 1261 } 1262 } 1263 default_mapping = (i == possible_cpus->len); 1264 1265 for (i = 0; i < possible_cpus->len; i++) { 1266 const CPUArchId *cpu_slot = &possible_cpus->cpus[i]; 1267 1268 if (!cpu_slot->props.has_node_id) { 1269 /* fetch default mapping from board and enable it */ 1270 CpuInstanceProperties props = cpu_slot->props; 1271 1272 props.node_id = mc->get_default_cpu_node_id(machine, i); 1273 if (!default_mapping) { 1274 /* record slots with not set mapping, 1275 * TODO: make it hard error in future */ 1276 char *cpu_str = cpu_slot_to_string(cpu_slot); 1277 g_string_append_printf(s, "%sCPU %d [%s]", 1278 s->len ? ", " : "", i, cpu_str); 1279 g_free(cpu_str); 1280 1281 /* non mapped cpus used to fallback to node 0 */ 1282 props.node_id = 0; 1283 } 1284 1285 props.has_node_id = true; 1286 machine_set_cpu_numa_node(machine, &props, &error_fatal); 1287 } 1288 } 1289 1290 if (machine->numa_state->hmat_enabled) { 1291 numa_validate_initiator(machine->numa_state); 1292 } 1293 1294 if (s->len && !qtest_enabled()) { 1295 warn_report("CPU(s) not present in any NUMA nodes: %s", 1296 s->str); 1297 warn_report("All CPU(s) up to maxcpus should be described " 1298 "in NUMA config, ability to start up with partial NUMA " 1299 "mappings is obsoleted and will be removed in future"); 1300 } 1301 g_string_free(s, true); 1302 } 1303 1304 static void validate_cpu_cluster_to_numa_boundary(MachineState *ms) 1305 { 1306 MachineClass *mc = MACHINE_GET_CLASS(ms); 1307 NumaState *state = ms->numa_state; 1308 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1309 const CPUArchId *cpus = possible_cpus->cpus; 1310 int i, j; 1311 1312 if (state->num_nodes <= 1 || possible_cpus->len <= 1) { 1313 return; 1314 } 1315 1316 /* 1317 * The Linux scheduling domain can't be parsed when the multiple CPUs 1318 * in one cluster have been associated with different NUMA nodes. However, 1319 * it's fine to associate one NUMA node with CPUs in different clusters. 1320 */ 1321 for (i = 0; i < possible_cpus->len; i++) { 1322 for (j = i + 1; j < possible_cpus->len; j++) { 1323 if (cpus[i].props.has_socket_id && 1324 cpus[i].props.has_cluster_id && 1325 cpus[i].props.has_node_id && 1326 cpus[j].props.has_socket_id && 1327 cpus[j].props.has_cluster_id && 1328 cpus[j].props.has_node_id && 1329 cpus[i].props.socket_id == cpus[j].props.socket_id && 1330 cpus[i].props.cluster_id == cpus[j].props.cluster_id && 1331 cpus[i].props.node_id != cpus[j].props.node_id) { 1332 warn_report("CPU-%d and CPU-%d in socket-%" PRId64 "-cluster-%" PRId64 1333 " have been associated with node-%" PRId64 " and node-%" PRId64 1334 " respectively. It can cause OSes like Linux to" 1335 " misbehave", i, j, cpus[i].props.socket_id, 1336 cpus[i].props.cluster_id, cpus[i].props.node_id, 1337 cpus[j].props.node_id); 1338 } 1339 } 1340 } 1341 } 1342 1343 MemoryRegion *machine_consume_memdev(MachineState *machine, 1344 HostMemoryBackend *backend) 1345 { 1346 MemoryRegion *ret = host_memory_backend_get_memory(backend); 1347 1348 if (host_memory_backend_is_mapped(backend)) { 1349 error_report("memory backend %s can't be used multiple times.", 1350 object_get_canonical_path_component(OBJECT(backend))); 1351 exit(EXIT_FAILURE); 1352 } 1353 host_memory_backend_set_mapped(backend, true); 1354 vmstate_register_ram_global(ret); 1355 return ret; 1356 } 1357 1358 static bool create_default_memdev(MachineState *ms, const char *path, Error **errp) 1359 { 1360 Object *obj; 1361 MachineClass *mc = MACHINE_GET_CLASS(ms); 1362 bool r = false; 1363 1364 obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM); 1365 if (path) { 1366 if (!object_property_set_str(obj, "mem-path", path, errp)) { 1367 goto out; 1368 } 1369 } 1370 if (!object_property_set_int(obj, "size", ms->ram_size, errp)) { 1371 goto out; 1372 } 1373 object_property_add_child(object_get_objects_root(), mc->default_ram_id, 1374 obj); 1375 /* Ensure backend's memory region name is equal to mc->default_ram_id */ 1376 if (!object_property_set_bool(obj, "x-use-canonical-path-for-ramblock-id", 1377 false, errp)) { 1378 goto out; 1379 } 1380 if (!user_creatable_complete(USER_CREATABLE(obj), errp)) { 1381 goto out; 1382 } 1383 r = object_property_set_link(OBJECT(ms), "memory-backend", obj, errp); 1384 1385 out: 1386 object_unref(obj); 1387 return r; 1388 } 1389 1390 1391 void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp) 1392 { 1393 ERRP_GUARD(); 1394 MachineClass *machine_class = MACHINE_GET_CLASS(machine); 1395 ObjectClass *oc = object_class_by_name(machine->cpu_type); 1396 CPUClass *cc; 1397 1398 /* This checkpoint is required by replay to separate prior clock 1399 reading from the other reads, because timer polling functions query 1400 clock values from the log. */ 1401 replay_checkpoint(CHECKPOINT_INIT); 1402 1403 if (!xen_enabled()) { 1404 /* On 32-bit hosts, QEMU is limited by virtual address space */ 1405 if (machine->ram_size > (2047 << 20) && HOST_LONG_BITS == 32) { 1406 error_setg(errp, "at most 2047 MB RAM can be simulated"); 1407 return; 1408 } 1409 } 1410 1411 if (machine->memdev) { 1412 ram_addr_t backend_size = object_property_get_uint(OBJECT(machine->memdev), 1413 "size", &error_abort); 1414 if (backend_size != machine->ram_size) { 1415 error_setg(errp, "Machine memory size does not match the size of the memory backend"); 1416 return; 1417 } 1418 } else if (machine_class->default_ram_id && machine->ram_size && 1419 numa_uses_legacy_mem()) { 1420 if (object_property_find(object_get_objects_root(), 1421 machine_class->default_ram_id)) { 1422 error_setg(errp, "object's id '%s' is reserved for the default" 1423 " RAM backend, it can't be used for any other purposes", 1424 machine_class->default_ram_id); 1425 error_append_hint(errp, 1426 "Change the object's 'id' to something else or disable" 1427 " automatic creation of the default RAM backend by setting" 1428 " 'memory-backend=%s' with '-machine'.\n", 1429 machine_class->default_ram_id); 1430 return; 1431 } 1432 if (!create_default_memdev(current_machine, mem_path, errp)) { 1433 return; 1434 } 1435 } 1436 1437 if (machine->numa_state) { 1438 numa_complete_configuration(machine); 1439 if (machine->numa_state->num_nodes) { 1440 machine_numa_finish_cpu_init(machine); 1441 if (machine_class->cpu_cluster_has_numa_boundary) { 1442 validate_cpu_cluster_to_numa_boundary(machine); 1443 } 1444 } 1445 } 1446 1447 if (!machine->ram && machine->memdev) { 1448 machine->ram = machine_consume_memdev(machine, machine->memdev); 1449 } 1450 1451 /* If the machine supports the valid_cpu_types check and the user 1452 * specified a CPU with -cpu check here that the user CPU is supported. 1453 */ 1454 if (machine_class->valid_cpu_types && machine->cpu_type) { 1455 int i; 1456 1457 for (i = 0; machine_class->valid_cpu_types[i]; i++) { 1458 if (object_class_dynamic_cast(oc, 1459 machine_class->valid_cpu_types[i])) { 1460 /* The user specified CPU is in the valid field, we are 1461 * good to go. 1462 */ 1463 break; 1464 } 1465 } 1466 1467 if (!machine_class->valid_cpu_types[i]) { 1468 /* The user specified CPU is not valid */ 1469 error_report("Invalid CPU type: %s", machine->cpu_type); 1470 error_printf("The valid types are: %s", 1471 machine_class->valid_cpu_types[0]); 1472 for (i = 1; machine_class->valid_cpu_types[i]; i++) { 1473 error_printf(", %s", machine_class->valid_cpu_types[i]); 1474 } 1475 error_printf("\n"); 1476 1477 exit(1); 1478 } 1479 } 1480 1481 /* Check if CPU type is deprecated and warn if so */ 1482 cc = CPU_CLASS(oc); 1483 if (cc && cc->deprecation_note) { 1484 warn_report("CPU model %s is deprecated -- %s", machine->cpu_type, 1485 cc->deprecation_note); 1486 } 1487 1488 if (machine->cgs) { 1489 /* 1490 * With confidential guests, the host can't see the real 1491 * contents of RAM, so there's no point in it trying to merge 1492 * areas. 1493 */ 1494 machine_set_mem_merge(OBJECT(machine), false, &error_abort); 1495 1496 /* 1497 * Virtio devices can't count on directly accessing guest 1498 * memory, so they need iommu_platform=on to use normal DMA 1499 * mechanisms. That requires also disabling legacy virtio 1500 * support for those virtio pci devices which allow it. 1501 */ 1502 object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy", 1503 "on", true); 1504 object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform", 1505 "on", false); 1506 } 1507 1508 accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator)); 1509 machine_class->init(machine); 1510 phase_advance(PHASE_MACHINE_INITIALIZED); 1511 } 1512 1513 static NotifierList machine_init_done_notifiers = 1514 NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers); 1515 1516 void qemu_add_machine_init_done_notifier(Notifier *notify) 1517 { 1518 notifier_list_add(&machine_init_done_notifiers, notify); 1519 if (phase_check(PHASE_MACHINE_READY)) { 1520 notify->notify(notify, NULL); 1521 } 1522 } 1523 1524 void qemu_remove_machine_init_done_notifier(Notifier *notify) 1525 { 1526 notifier_remove(notify); 1527 } 1528 1529 void qdev_machine_creation_done(void) 1530 { 1531 cpu_synchronize_all_post_init(); 1532 1533 if (current_machine->boot_config.once) { 1534 qemu_boot_set(current_machine->boot_config.once, &error_fatal); 1535 qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_config.order)); 1536 } 1537 1538 /* 1539 * ok, initial machine setup is done, starting from now we can 1540 * only create hotpluggable devices 1541 */ 1542 phase_advance(PHASE_MACHINE_READY); 1543 qdev_assert_realized_properly(); 1544 1545 /* TODO: once all bus devices are qdevified, this should be done 1546 * when bus is created by qdev.c */ 1547 /* 1548 * TODO: If we had a main 'reset container' that the whole system 1549 * lived in, we could reset that using the multi-phase reset 1550 * APIs. For the moment, we just reset the sysbus, which will cause 1551 * all devices hanging off it (and all their child buses, recursively) 1552 * to be reset. Note that this will *not* reset any Device objects 1553 * which are not attached to some part of the qbus tree! 1554 */ 1555 qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default()); 1556 1557 notifier_list_notify(&machine_init_done_notifiers, NULL); 1558 1559 if (rom_check_and_register_reset() != 0) { 1560 exit(1); 1561 } 1562 1563 replay_start(); 1564 1565 /* This checkpoint is required by replay to separate prior clock 1566 reading from the other reads, because timer polling functions query 1567 clock values from the log. */ 1568 replay_checkpoint(CHECKPOINT_RESET); 1569 qemu_system_reset(SHUTDOWN_CAUSE_NONE); 1570 register_global_state(); 1571 } 1572 1573 static const TypeInfo machine_info = { 1574 .name = TYPE_MACHINE, 1575 .parent = TYPE_OBJECT, 1576 .abstract = true, 1577 .class_size = sizeof(MachineClass), 1578 .class_init = machine_class_init, 1579 .class_base_init = machine_class_base_init, 1580 .instance_size = sizeof(MachineState), 1581 .instance_init = machine_initfn, 1582 .instance_finalize = machine_finalize, 1583 }; 1584 1585 static void machine_register_types(void) 1586 { 1587 type_register_static(&machine_info); 1588 } 1589 1590 type_init(machine_register_types) 1591